path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.759348                       # Number of seconds simulated
sim_ticks                                51759347706500                       # Number of ticks simulated
final_tick                               51759347706500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 706961                       # Simulator instruction rate (inst/s)
host_op_rate                                   830795                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            43773319280                       # Simulator tick rate (ticks/s)
host_mem_usage                                 670816                       # Number of bytes of host memory used
host_seconds                                  1182.44                       # Real time elapsed on the host
sim_insts                                   835939132                       # Number of instructions simulated
sim_ops                                     982366087                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       152192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       158144                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           4715828                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          36073224                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        410496                       # Number of bytes read from this memory
system.physmem.bytes_read::total             41509884                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      4715828                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         4715828                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     62909632                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          62930212                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         2378                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         2471                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             114092                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             563657                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6414                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                689012                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          982963                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               985536                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           2940                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           3055                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst                91111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               696941                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7931                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  801978                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           91111                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              91111                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1215426                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 398                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1215823                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1215426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          2940                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          3055                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               91111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              697339                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2017802                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        689012                       # Number of read requests accepted
system.physmem.writeReqs                       985536                       # Number of write requests accepted
system.physmem.readBursts                      689012                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     985536                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 44056384                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     40384                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  62928960                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  41509884                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               62930212                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      631                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               41424                       # Per bank write bursts
system.physmem.perBankRdBursts::1               42196                       # Per bank write bursts
system.physmem.perBankRdBursts::2               39305                       # Per bank write bursts
system.physmem.perBankRdBursts::3               41228                       # Per bank write bursts
system.physmem.perBankRdBursts::4               37796                       # Per bank write bursts
system.physmem.perBankRdBursts::5               46284                       # Per bank write bursts
system.physmem.perBankRdBursts::6               37646                       # Per bank write bursts
system.physmem.perBankRdBursts::7               36984                       # Per bank write bursts
system.physmem.perBankRdBursts::8               37874                       # Per bank write bursts
system.physmem.perBankRdBursts::9               85067                       # Per bank write bursts
system.physmem.perBankRdBursts::10              43899                       # Per bank write bursts
system.physmem.perBankRdBursts::11              46232                       # Per bank write bursts
system.physmem.perBankRdBursts::12              39321                       # Per bank write bursts
system.physmem.perBankRdBursts::13              40035                       # Per bank write bursts
system.physmem.perBankRdBursts::14              35465                       # Per bank write bursts
system.physmem.perBankRdBursts::15              37625                       # Per bank write bursts
system.physmem.perBankWrBursts::0               61899                       # Per bank write bursts
system.physmem.perBankWrBursts::1               62487                       # Per bank write bursts
system.physmem.perBankWrBursts::2               61087                       # Per bank write bursts
system.physmem.perBankWrBursts::3               63695                       # Per bank write bursts
system.physmem.perBankWrBursts::4               58991                       # Per bank write bursts
system.physmem.perBankWrBursts::5               64628                       # Per bank write bursts
system.physmem.perBankWrBursts::6               58592                       # Per bank write bursts
system.physmem.perBankWrBursts::7               59025                       # Per bank write bursts
system.physmem.perBankWrBursts::8               60354                       # Per bank write bursts
system.physmem.perBankWrBursts::9               64900                       # Per bank write bursts
system.physmem.perBankWrBursts::10              63044                       # Per bank write bursts
system.physmem.perBankWrBursts::11              64791                       # Per bank write bursts
system.physmem.perBankWrBursts::12              60176                       # Per bank write bursts
system.physmem.perBankWrBursts::13              61598                       # Per bank write bursts
system.physmem.perBankWrBursts::14              57895                       # Per bank write bursts
system.physmem.perBankWrBursts::15              60103                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
system.physmem.totGap                    51759344769500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  645896                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 982963                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    659454                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     23139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       405                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       555                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       545                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       668                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       47                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    31865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    37580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    54935                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    54491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    57672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    55206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    58598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    55686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    56443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    55845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    56872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    59532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    57169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    57139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    58902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    55823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    54603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    54399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2302                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      467                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      317                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       47                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       438828                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      243.797169                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     147.013209                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     285.979705                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         194919     44.42%     44.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       116778     26.61%     71.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        38832      8.85%     79.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        20430      4.66%     84.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        13130      2.99%     87.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         8793      2.00%     89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7414      1.69%     91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5819      1.33%     92.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        32713      7.45%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         438828                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         52143                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        13.201312                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      141.003763                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          52140     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           52143                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         52143                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.857085                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.140227                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.284435                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           48446     92.91%     92.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1855      3.56%     96.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             116      0.22%     96.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             101      0.19%     96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              48      0.09%     96.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             101      0.19%     97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             252      0.48%     97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              24      0.05%     97.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             307      0.59%     98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              75      0.14%     98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              29      0.06%     98.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              51      0.10%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             313      0.60%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              41      0.08%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              37      0.07%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             129      0.25%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             166      0.32%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            15      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           52143                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9222624910                       # Total ticks spent queuing
system.physmem.totMemAccLat               22129768660                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   3441905000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13397.56                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32147.56                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.85                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.22                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.22                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.01                       # Average write queue length when enqueuing
system.physmem.readRowHits                     507228                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    725589                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.68                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.79                       # Row buffer hit rate for writes
system.physmem.avgGap                     30909442.29                       # Average gap between requests
system.physmem.pageHitRate                      73.75                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1651557600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  901147500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                2518331400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3177817920                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3380668873920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1280908967265                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29932003411500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34601830107105                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.513662                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49794254360042                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1728358320000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    236733614958                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1665982080                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  909018000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                2851001400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3193739280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3380668873920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1282600048680                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29930520006750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34602408670110                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.524840                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49791748874504                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1728358320000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    239239854996                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    186389                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                186389                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        11673                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       145933                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore           20                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       186369                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean     0.214628                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev    70.564506                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047       186367    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       186369                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       157626                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       156391     99.22%     99.22% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071            5      0.00%     99.22% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         1058      0.67%     99.89% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143           24      0.02%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           78      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           18      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           45      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       157626                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples  -5176298892                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     1.304609                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      1576748204    -30.46%    -30.46% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1     -6753047096    130.46%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total  -5176298892                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        145934     92.59%     92.59% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         11673      7.41%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       157607                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       186389                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       186389                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       157607                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       157607                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       343996                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    157302470                       # DTB read hits
system.cpu.dtb.read_misses                     138254                       # DTB read misses
system.cpu.dtb.write_hits                   142797891                       # DTB write hits
system.cpu.dtb.write_misses                     48135                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               38509                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1009                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    71109                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   6989                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     18784                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                157440724                       # DTB read accesses
system.cpu.dtb.write_accesses               142846026                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         300100361                       # DTB hits
system.cpu.dtb.misses                          186389                       # DTB misses
system.cpu.dtb.accesses                     300286750                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    119383                       # Table walker walks requested
system.cpu.itb.walker.walksLong                119383                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1122                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       107813                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       119383                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          119383    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       119383                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       108935                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28686.574563                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       107446     98.63%     98.63% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071            3      0.00%     98.64% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         1285      1.18%     99.82% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           37      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           72      0.07%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           42      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           32      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       108935                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   1449611704                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      1449611704    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   1449611704                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        107813     98.97%     98.97% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1122      1.03%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       108935                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       119383                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       119383                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       108935                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       108935                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       228318                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    836454912                       # ITB inst hits
system.cpu.itb.inst_misses                     119383                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               38509                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1009                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    50925                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                836574295                       # ITB inst accesses
system.cpu.itb.hits                         836454912                       # DTB hits
system.cpu.itb.misses                          119383                       # DTB misses
system.cpu.itb.accesses                     836574295                       # DTB accesses
system.cpu.numPwrStateTransitions               32056                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16028                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3133878336.314075                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    60741761061.559830                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         6738     42.04%     42.04% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9255     57.74%     99.78% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::8e+11-8.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988775138696                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16028                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    1529545732058                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                     103518695413                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16028                       # number of quiesce instructions executed
system.cpu.committedInsts                   835939132                       # Number of instructions committed
system.cpu.committedOps                     982366087                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             902933087                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 900158                       # Number of float alu accesses
system.cpu.num_func_calls                    50090187                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    126876498                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    902933087                       # number of integer instructions
system.cpu.num_fp_insts                        900158                       # number of float instructions
system.cpu.num_int_register_reads          1308206945                       # number of times the integer registers were read
system.cpu.num_int_register_writes          715740470                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              1453094                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              759824                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            216985275                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           216380044                       # number of times the CC registers were written
system.cpu.num_mem_refs                     300079118                       # number of memory refs
system.cpu.num_load_insts                   157292666                       # Number of load instructions
system.cpu.num_store_insts                  142786452                       # Number of store instructions
system.cpu.num_idle_cycles               100459603948.882050                       # Number of idle cycles
system.cpu.num_busy_cycles               3059091464.117941                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.029551                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.970449                       # Percentage of idle cycles
system.cpu.Branches                         186526742                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 680504734     69.23%     69.23% # Class of executed instruction
system.cpu.op_class::IntMult                  2132093      0.22%     69.45% # Class of executed instruction
system.cpu.op_class::IntDiv                     96706      0.01%     69.46% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   8      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                  13      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                  21      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.46% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc             112297      0.01%     69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.47% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.47% # Class of executed instruction
system.cpu.op_class::MemRead                157292666     16.00%     85.47% # Class of executed instruction
system.cpu.op_class::MemWrite               142786452     14.53%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  982924991                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           9370067                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.942718                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           290532688                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9370579                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             31.004774                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        5830299500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.942718                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999888                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1209437211                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1209437211                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    147248395                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       147248395                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    135579268                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      135579268                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       373548                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        373548                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       331872                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       331872                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3336329                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3336329                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3621011                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3621011                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     283159535                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        283159535                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    283533083                       # number of overall hits
system.cpu.dcache.overall_hits::total       283533083                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      4886658                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       4886658                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1993718                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1993718                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1137538                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1137538                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1221988                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1221988                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       286320                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       286320                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      8102364                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        8102364                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9239902                       # number of overall misses
system.cpu.dcache.overall_misses::total       9239902                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  84160893500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  84160893500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  69982072000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  69982072000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  48119896000                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  48119896000                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4409003500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4409003500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       162000                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       162000                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 202262861500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 202262861500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 202262861500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 202262861500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    152135053                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    152135053                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    137572986                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    137572986                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1511086                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1511086                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1553860                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1553860                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3622649                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3622649                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3621013                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3621013                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    291261899                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    291261899                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    292772985                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    292772985                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032121                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032121                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014492                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.014492                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.752795                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.752795                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.786421                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.786421                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079036                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079036                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.027818                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.027818                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.031560                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.031560                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        81000                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        81000                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24963.438016                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 21890.152244                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      7310347                       # number of writebacks
system.cpu.dcache.writebacks::total           7310347                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21149                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        21149                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21212                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        21212                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        69210                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        69210                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        42361                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        42361                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        42361                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        42361                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      4865509                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      4865509                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1972506                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1972506                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1135773                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1135773                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1221988                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1221988                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       217110                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       217110                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8060003                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8060003                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9195776                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9195776                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67410                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  78024875000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  78024875000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  67036106500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  67036106500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21307541000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21307541000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  46897908000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  46897908000                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   2989370500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   2989370500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       160000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       160000                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 191958889500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 213266430500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6199627500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6199627500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6199627500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6199627500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031982                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031982                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014338                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014338                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.751627                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.751627                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.786421                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.786421                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.059931                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.059931                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027673                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.027673                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031409                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.031409                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        80000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        80000                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          13316326                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.820794                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           823138069                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          13316838                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             61.811826                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       49363844500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.820794                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999650                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999650                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         849771755                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        849771755                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    823138069                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       823138069                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     823138069                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        823138069                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    823138069                       # number of overall hits
system.cpu.icache.overall_hits::total       823138069                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     13316843                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      13316843                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     13316843                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       13316843                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     13316843                       # number of overall misses
system.cpu.icache.overall_misses::total      13316843                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 182043679500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 182043679500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 182043679500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 182043679500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 182043679500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    836454912                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    836454912                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    836454912                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    836454912                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    836454912                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    836454912                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015921                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015921                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015921                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015921                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015921                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015921                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13670.182903                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13670.182903                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     13316326                       # number of writebacks
system.cpu.icache.writebacks::total          13316326                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13316843                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     13316843                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     13316843                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     13316843                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     13316843                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     13316843                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168726836500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 168726836500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168726836500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 168726836500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168726836500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 168726836500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   5436787000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   5436787000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   5436787000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015921                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.015921                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015921                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.015921                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12670.182903                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12670.182903                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12670.182903                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12670.182903                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1029342                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65301.929117                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           41597878                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1091508                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            38.110466                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      12385503500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38086.632918                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   236.862091                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   354.562935                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7802.558346                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 18821.312827                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.581156                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.003614                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.005410                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.119058                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.287190                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996428                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          232                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        61934                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          229                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          403                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2431                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5392                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53675                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.003540                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.945038                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        371610075                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       371610075                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       312133                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       242520                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         554653                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      7310347                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      7310347                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     13314767                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     13314767                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         8998                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         8998                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1590193                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1590193                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13245839                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     13245839                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5993599                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      5993599                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       742035                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       742035                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       312133                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       242520                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     13245839                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7583792                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        21384284                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       312133                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       242520                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     13245839                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7583792                       # number of overall hits
system.cpu.l2cache.overall_hits::total       21384284                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         2378                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         2471                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4849                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        33265                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        33265                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       340050                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       340050                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        71004                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        71004                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       224793                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       224793                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       479953                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       479953                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         2378                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         2471                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        71004                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       564843                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        640696                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         2378                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         2471                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        71004                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       564843                       # number of overall misses
system.cpu.l2cache.overall_misses::total       640696                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    324181000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    343851000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    668032000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1328369000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1328369000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       157000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       157000                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  44644302500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  44644302500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   9404933500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   9404933500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  29984552500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  29984552500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data       542500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total       542500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    324181000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    343851000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   9404933500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  74628855000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  84701820500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    324181000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    343851000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   9404933500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  74628855000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  84701820500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       314511                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       244991                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       559502                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      7310347                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      7310347                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     13314767                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     13314767                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        42263                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        42263                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1930243                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1930243                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13316843                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     13316843                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6218392                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6218392                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1221988                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1221988                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       314511                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       244991                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     13316843                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8148635                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     22024980                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       314511                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       244991                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     13316843                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8148635                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     22024980                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010086                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.008667                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.787095                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.787095                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.176170                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.176170                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005332                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005332                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.036150                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.036150                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.392764                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.392764                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010086                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005332                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.069317                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.029090                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.007561                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010086                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005332                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.069317                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.029090                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136325.063078                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139154.593282                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137766.962260                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39932.932512                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39932.932512                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        78500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        78500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131287.465079                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131287.465079                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132456.389781                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132456.389781                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133387.394180                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133387.394180                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data     1.130319                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total     1.130319                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136325.063078                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139154.593282                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132456.389781                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132123.182902                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 132202.823960                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136325.063078                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139154.593282                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132456.389781                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132123.182902                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 132202.823960                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks       876332                       # number of writebacks
system.cpu.l2cache.writebacks::total           876332                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2378                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         2471                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4849                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33265                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        33265                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       340050                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       340050                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        71004                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        71004                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       224793                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       224793                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       479953                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       479953                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         2378                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         2471                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        71004                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       564843                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       640696                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         2378                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         2471                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        71004                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       564843                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       640696                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76827                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33708                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67410                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110535                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    319141000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    619542000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2260005000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2260005000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       137000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       137000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  41243802500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  41243802500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   8694893500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   8694893500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27736359527                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27736359527                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  32474021500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  32474021500                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    319141000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   8694893500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  68980162027                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  78294597527                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    300401000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    319141000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   8694893500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  68980162027                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  78294597527                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777547500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10675272000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5777547500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10675272000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008667                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.787095                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.787095                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.176170                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.176170                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005332                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.036150                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.036150                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.392764                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.392764                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.069317                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.029090                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.007561                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010086                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005332                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.069317                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.029090                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        68500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        68500                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     45899412                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     23211953                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1753                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2701                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2701                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq         979874                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      20515947                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33708                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33708                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      8293329                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     13316326                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2221598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        42266                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        42268                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1930243                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1930243                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     13316843                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6227282                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1328652                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1221988                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40036262                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     28331504                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       601742                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       860807                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          69830315                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1704695316                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    989618926                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1959928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2516088                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2698790258                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1604803                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              65712840                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     25003730                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.019507                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.138299                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           24515981     98.05%     98.05% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             487749      1.95%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       25003730                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    43858380000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1560894                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   20018389500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   12905646976                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     356751000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     546296000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40338                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40338                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231034                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231034                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353818                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492488                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42150000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               322000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25729000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38601000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           566926866                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147794000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115499                       # number of replacements
system.iocache.tags.tagsinuse               10.446740                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115515                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13171623640000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.847996                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.598744                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.365500                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.287422                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652921                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040010                       # Number of tag accesses
system.iocache.tags.data_accesses             1040010                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8853                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8890                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115517                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115557                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115517                       # number of overall misses
system.iocache.overall_misses::total           115557                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5070500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1655174117                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1660244617                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13409764249                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13409764249                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5421500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15064938366                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15070359866                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5421500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15064938366                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15070359866                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8853                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8890                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115517                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115557                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115517                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115557                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186754.175141                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130413.171793                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130414.945577                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130413.171793                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130414.945577                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33045                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3376                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.788211                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8853                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8890                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115517                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115557                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115517                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115557                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1212524117                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1215744617                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8071395398                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8071395398                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3421500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9283919515                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9287341015                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3421500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9283919515                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9287341015                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80370.215694                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80370.215694                       # average overall mshr miss latency
system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
system.membus.trans_dist::ReadResp             386363                       # Transaction distribution
system.membus.trans_dist::WriteReq              33708                       # Transaction distribution
system.membus.trans_dist::WriteResp             33708                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       982963                       # Transaction distribution
system.membus.trans_dist::CleanEvict           160860                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            33836                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
system.membus.trans_dist::ReadExReq            339489                       # Transaction distribution
system.membus.trans_dist::ReadExResp           339489                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        309536                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        586610                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6930                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2913100                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3042792                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237470                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237470                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                3280262                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13860                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     97205216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     97375042                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7234880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7234880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               104609922                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3136                       # Total snoops (count)
system.membus.snoopTraffic                     200256                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2523850                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2523850    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2523850                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106906000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5727500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          6514212892                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3604018785                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44774812                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------