path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.397579                       # Number of seconds simulated
sim_ticks                                51397578885000                       # Number of ticks simulated
final_tick                               51397578885000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 213094                       # Simulator instruction rate (inst/s)
host_op_rate                                   250423                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11187167929                       # Simulator tick rate (ticks/s)
host_mem_usage                                 682236                       # Number of bytes of host memory used
host_seconds                                  4594.33                       # Real time elapsed on the host
sim_insts                                   979026656                       # Number of instructions simulated
sim_ops                                    1150528336                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       187840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       177856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2851188                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         60331016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        46336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        44800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           415360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          9688384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker        76288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker        60224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          1747072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data         13459648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker       113856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker       106880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst          1985280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data         25411584                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        412224                       # Number of bytes read from this memory
system.physmem.bytes_read::total            117115836                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2851188                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       415360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      1747072                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst      1985280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6998900                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    101778880                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total         101799460                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2935                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2779                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             84957                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            942685                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          724                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          700                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              6490                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            151381                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker         1192                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker          941                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             27298                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            210307                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker         1779                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker         1670                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst             31020                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data            397056                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6441                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1870355                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1590295                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1592868                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3655                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          3460                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               55473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1173810                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           902                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker           872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst                8081                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              188499                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker          1484                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker          1172                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               33991                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              261873                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          2215                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker          2079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst               38626                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data              494412                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8020                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2278626                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          55473                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst           8081                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          33991                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst          38626                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             136172                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1980227                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                400                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1980628                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1980227                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3655                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         3460                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              55473                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1174211                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          902                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker          872                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst               8081                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             188499                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker         1484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker         1172                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              33991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             261873                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         2215                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker         2079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst              38626                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data             494412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8020                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4259253                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        833134                       # Number of read requests accepted
system.physmem.writeReqs                       737289                       # Number of write requests accepted
system.physmem.readBursts                      833134                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     737289                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 53302080                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     18496                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  47184896                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  53320576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               47186496                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      289                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          72650                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               50780                       # Per bank write bursts
system.physmem.perBankRdBursts::1               53589                       # Per bank write bursts
system.physmem.perBankRdBursts::2               52846                       # Per bank write bursts
system.physmem.perBankRdBursts::3               50887                       # Per bank write bursts
system.physmem.perBankRdBursts::4               54092                       # Per bank write bursts
system.physmem.perBankRdBursts::5               57010                       # Per bank write bursts
system.physmem.perBankRdBursts::6               51070                       # Per bank write bursts
system.physmem.perBankRdBursts::7               50979                       # Per bank write bursts
system.physmem.perBankRdBursts::8               47072                       # Per bank write bursts
system.physmem.perBankRdBursts::9               53421                       # Per bank write bursts
system.physmem.perBankRdBursts::10              50826                       # Per bank write bursts
system.physmem.perBankRdBursts::11              55035                       # Per bank write bursts
system.physmem.perBankRdBursts::12              52027                       # Per bank write bursts
system.physmem.perBankRdBursts::13              53888                       # Per bank write bursts
system.physmem.perBankRdBursts::14              49567                       # Per bank write bursts
system.physmem.perBankRdBursts::15              49756                       # Per bank write bursts
system.physmem.perBankWrBursts::0               44616                       # Per bank write bursts
system.physmem.perBankWrBursts::1               46679                       # Per bank write bursts
system.physmem.perBankWrBursts::2               46441                       # Per bank write bursts
system.physmem.perBankWrBursts::3               46533                       # Per bank write bursts
system.physmem.perBankWrBursts::4               48478                       # Per bank write bursts
system.physmem.perBankWrBursts::5               49819                       # Per bank write bursts
system.physmem.perBankWrBursts::6               45666                       # Per bank write bursts
system.physmem.perBankWrBursts::7               46728                       # Per bank write bursts
system.physmem.perBankWrBursts::8               42759                       # Per bank write bursts
system.physmem.perBankWrBursts::9               46487                       # Per bank write bursts
system.physmem.perBankWrBursts::10              43753                       # Per bank write bursts
system.physmem.perBankWrBursts::11              47850                       # Per bank write bursts
system.physmem.perBankWrBursts::12              45610                       # Per bank write bursts
system.physmem.perBankWrBursts::13              46767                       # Per bank write bursts
system.physmem.perBankWrBursts::14              44243                       # Per bank write bursts
system.physmem.perBankWrBursts::15              44835                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          15                       # Number of times write queue was full causing retry
system.physmem.totGap                    51396578546000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  833134                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 737289                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    571213                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    169334                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     57100                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     32959                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       346                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       206                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       433                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       161                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       65                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       46                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       42                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     9918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    10640                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    28561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    34227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    40879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    43831                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    44813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    44612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    46135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    46247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    46174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    49387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    47038                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    46944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    49392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    44847                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    45364                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    43267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      264                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       393907                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      255.102976                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     152.689482                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     290.846029                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         173695     44.10%     44.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        94994     24.12%     68.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        37135      9.43%     77.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        19371      4.92%     82.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15343      3.90%     86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9742      2.47%     88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8567      2.17%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6531      1.66%     92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        28529      7.24%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         393907                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         42633                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        19.534281                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev        9.731161                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31            39808     93.37%     93.37% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63            2621      6.15%     99.52% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95             170      0.40%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127             21      0.05%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159             5      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255             4      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::352-383             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::544-575             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::608-639             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           42633                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         42633                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.293270                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.880471                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        5.837851                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                31      0.07%      0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 7      0.02%      0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               18      0.04%      0.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              54      0.13%      0.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           40522     95.05%     95.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             728      1.71%     97.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             202      0.47%     97.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             312      0.73%     98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              57      0.13%     98.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             185      0.43%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              71      0.17%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              15      0.04%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              39      0.09%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              54      0.13%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              14      0.03%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              19      0.04%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             210      0.49%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              11      0.03%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.02%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              44      0.10%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            11      0.03%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           42633                       # Writes before turning the bus around for reads
system.physmem.totQLat                    19475290366                       # Total ticks spent queuing
system.physmem.totMemAccLat               35091134116                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4164225000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23384.05                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42134.05                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.04                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.04                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.92                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        13.53                       # Average write queue length when enqueuing
system.physmem.readRowHits                     652462                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    523738                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.34                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  71.04                       # Row buffer hit rate for writes
system.physmem.avgGap                     32727856.47                       # Average gap between requests
system.physmem.pageHitRate                      74.91                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1529501400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  832833375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3285765600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               2429740800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3315984618960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1212289072380                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29739570673500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34275922206015                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.648127                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   48905170971226                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1695288660000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    169075280274                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1448412840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  788411250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3210347400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               2347729920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3315984618960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1209778712865                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29729309949000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34262868182235                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.663987                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   48908958102968                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1695288660000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    165299992532                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   119866                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               119866                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       119866                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         119866    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       119866                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 379345082112                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.652647                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -247578241138    -65.26%    -65.26% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1   626923323250    165.26%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 379345082112                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        88729     84.84%     84.84% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        15861     15.16%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       104590                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       119866                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       119866                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104590                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104590                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       224456                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    75642766                       # DTB read hits
system.cpu0.dtb.read_misses                     89640                       # DTB read misses
system.cpu0.dtb.write_hits                   69609144                       # DTB write hits
system.cpu0.dtb.write_misses                    30226                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1263                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              20153                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    452                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   47006                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3911                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     8593                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                75732406                       # DTB read accesses
system.cpu0.dtb.write_accesses               69639370                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        145251910                       # DTB hits
system.cpu0.dtb.misses                         119866                       # DTB misses
system.cpu0.dtb.accesses                    145371776                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    57950                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                57950                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        57950                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          57950    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        57950                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 379345082112                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.652788                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -247631753638    -65.28%    -65.28% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   626976835750    165.28%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 379345082112                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        50452     94.94%     94.94% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2688      5.06%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        53140                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        57950                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        57950                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        53140                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        53140                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       111090                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   405381622                       # ITB inst hits
system.cpu0.itb.inst_misses                     57950                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1263                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              20153                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    452                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   33228                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               405439572                       # ITB inst accesses
system.cpu0.itb.hits                        405381622                       # DTB hits
system.cpu0.itb.misses                          57950                       # DTB misses
system.cpu0.itb.accesses                    405439572                       # DTB accesses
system.cpu0.numCycles                       487302102                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   17144                       # number of quiesce instructions executed
system.cpu0.committedInsts                  405220560                       # Number of instructions committed
system.cpu0.committedOps                    476699664                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            436776878                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                371179                       # Number of float alu accesses
system.cpu0.num_func_calls                   23615839                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     62442452                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   436776878                       # number of integer instructions
system.cpu0.num_fp_insts                       371179                       # number of float instructions
system.cpu0.num_int_register_reads          647764481                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         347118708                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              591811                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             329388                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           109017876                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          108807189                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    145355316                       # number of memory refs
system.cpu0.num_load_insts                   75721514                       # Number of load instructions
system.cpu0.num_store_insts                  69633802                       # Number of store instructions
system.cpu0.num_idle_cycles              473916691.596574                       # Number of idle cycles
system.cpu0.num_busy_cycles              13385410.403426                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.027468                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.972532                       # Percentage of idle cycles
system.cpu0.Branches                         90584626                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                330567149     69.31%     69.31% # Class of executed instruction
system.cpu0.op_class::IntMult                  941893      0.20%     69.51% # Class of executed instruction
system.cpu0.op_class::IntDiv                    42225      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             50408      0.01%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::MemRead                75721514     15.88%     85.40% # Class of executed instruction
system.cpu0.op_class::MemWrite               69633802     14.60%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 476956991                       # Class of executed instruction
system.cpu0.dcache.tags.replacements         11638567                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          335736078                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         11639079                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.845588                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   493.702275                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.106923                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.404077                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data     5.786443                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.964262                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.013881                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010555                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.011302                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          321                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1427343443                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1427343443                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     70546993                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     21833087                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     29621653                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data     49726137                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      171727870                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     65848513                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     20323574                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     26400594                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data     41881288                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     154453969                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       178125                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        52842                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        85285                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data       124641                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       440893                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       129363                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data        44707                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data        62671                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data        98791                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       335532                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1762005                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       548820                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       697386                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data      1176730                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      4184941                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1865727                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       590771                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       751156                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1333509                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4541163                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    136395506                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     42156661                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     56022247                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     91607425                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       326181839                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    136573631                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     42209503                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     56107532                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     91732066                       # number of overall hits
system.cpu0.dcache.overall_hits::total      326622732                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2475648                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       760979                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data      1254924                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data      3959185                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      8450736                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1073288                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       320657                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       740390                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      4437299                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      6571634                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       641779                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       196644                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       265541                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data       463204                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1567168                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       696374                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       111936                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data       158316                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data       281973                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1248599                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       104417                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        42188                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        54084                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       202888                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       403577                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3548936                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1081636                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1995314                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      8396484                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      15022370                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4190715                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1278280                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      2260855                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      8859688                       # number of overall misses
system.cpu0.dcache.overall_misses::total     16589538                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  13138449000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  22320104000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  72359917000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 107818470000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  15766909000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  37704242500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 250636765802                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 304107917302                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   4487202500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   6834071500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  13735050622                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25056324622                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    652172000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    880917500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2926113500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4459203000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        97500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        97500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  28905358000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  60024346500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 322996682802                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 411926387302                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  28905358000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  60024346500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 322996682802                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 411926387302                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     73022641                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     22594066                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     30876577                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data     53685322                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    180178606                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     66921801                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     20644231                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     27140984                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data     46318587                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    161025603                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       819904                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       249486                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       350826                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       587845                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      2008061                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       825737                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       156643                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       220987                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       380764                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1584131                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1866422                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       591008                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       751470                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1379618                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4588518                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1865729                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       590771                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       751156                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1333511                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4541167                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    139944442                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     43238297                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     58017561                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data    100003909                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    341204209                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    140764346                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     43487783                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     58368387                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data    100591754                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    343212270                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033902                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033680                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.040643                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.073748                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.046902                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.016038                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015533                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.027279                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.095800                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.040811                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.782749                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.788197                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.756902                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.787970                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.780438                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.843336                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.714593                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.716404                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.740545                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788192                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055945                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.071383                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.071971                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.147061                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.087954                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.025360                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025016                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.034392                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.083962                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.044028                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029771                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.029394                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.038734                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.088076                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.048336                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17265.192601                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17786.020508                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18276.467758                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12758.470978                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49170.637161                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 50924.840287                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 56484.083178                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 46275.845140                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40087.215016                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 43167.282524                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 48710.517042                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20067.551409                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15458.708638                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16287.950226                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14422.309353                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11049.200029                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        48750                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        24375                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26723.738855                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30082.656915                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 38468.087690                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 27420.865503                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22612.696749                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26549.401222                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 36456.891349                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 24830.491802                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     26241707                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        45127                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          1118476                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            412                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.462021                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   109.531553                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8924778                       # number of writebacks
system.cpu0.dcache.writebacks::total          8924778                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3070                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       177170                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      2166772                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2347012                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4945                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       329293                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      3711119                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      4045357                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           29                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2101                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         2130                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8861                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        11403                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       125299                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       145563                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         8015                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       506463                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      5877891                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      6392369                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         8015                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       506463                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      5877891                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      6392369                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       757909                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      1077754                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1792413                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3628076                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       315712                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       411097                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       726180                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1452989                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       196254                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       262805                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       454839                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       913898                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       111936                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       158287                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       279872                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       550095                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        33327                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        42681                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        77589                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       153597                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      1073621                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      1488851                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data      2518593                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5081065                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1269875                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      1751656                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data      2973432                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5994963                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         7202                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6366                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         6575                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20143                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6701                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         5973                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6301                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18975                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13903                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        12339                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        12876                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        39118                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  12177566500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  17778974500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  32248588000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  62205129000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  15233797500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  19851845000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  42775170792                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  77860813292                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3503817000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   5256863500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   8318157000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17078837500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   4375266500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   6674550500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  13332028122                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24381845122                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    465254000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    623794000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data   1175051500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2264099500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        95500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        95500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  27411364000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  37630819500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  75023758792                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 140065942292                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  30915181000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  42887683000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  83341915792                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 157144779792                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1347374000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1179541000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1196510000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3723425000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1281429000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1132115000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1164905963                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3578449963                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2628803000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2311656000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2361415963                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   7301874963                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033545                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.034905                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.033387                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.020136                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.015293                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015147                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.015678                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.009023                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.786633                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.749104                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.773740                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.455115                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.714593                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.716273                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.735027                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.347253                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056390                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.056797                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.056239                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.033474                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024830                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.025662                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.025185                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.014892                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029201                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030010                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.029559                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.017467                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16067.320087                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16496.319661                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17991.717311                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17145.486754                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48252.196622                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48289.929141                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 58904.363645                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53586.650203                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17853.480693                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20002.905196                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 18288.134922                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18687.903355                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39087.215016                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 42167.395301                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 47636.162682                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 44322.971709                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13960.272452                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14615.262060                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15144.563018                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14740.519021                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        47750                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        47750                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25531.695077                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25275.074202                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 29787.964467                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27566.256738                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24345.058372                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 24484.078495                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28028.862201                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26212.802280                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187083.310192                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185287.621740                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 181978.707224                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184849.575535                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191229.517982                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 189538.757743                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 184876.362958                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188587.613333                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189081.708984                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187345.489910                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 183396.704178                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186662.788563                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         16734603                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.971494                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          650477960                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         16735115                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            38.869046                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11779377500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   475.687206                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     5.486973                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    23.054415                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.742900                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.929077                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.010717                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.045028                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.015123                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        684306607                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       684306607                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    399406332                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    123839702                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     74645872                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst     52586054                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      650477960                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    399406332                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    123839702                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     74645872                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst     52586054                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       650477960                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    399406332                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    123839702                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     74645872                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst     52586054                       # number of overall hits
system.cpu0.icache.overall_hits::total      650477960                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6028430                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1808723                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      4165797                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst      5090569                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17093519                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6028430                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1808723                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      4165797                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst      5090569                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17093519                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6028430                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1808723                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      4165797                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst      5090569                       # number of overall misses
system.cpu0.icache.overall_misses::total     17093519                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  24303980500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  57538187500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  68890776810                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 150732944810                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  24303980500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  57538187500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst  68890776810                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 150732944810                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  24303980500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  57538187500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst  68890776810                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 150732944810                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    405434762                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    125648425                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     78811669                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst     57676623                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    667571479                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    405434762                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    125648425                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     78811669                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst     57676623                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    667571479                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    405434762                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    125648425                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     78811669                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst     57676623                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    667571479                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014869                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014395                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.052858                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.088261                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.025606                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014869                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014395                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.052858                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.088261                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.025606                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014869                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014395                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.052858                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.088261                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.025606                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13437.093740                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.047851                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13533.020928                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8818.134219                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13437.093740                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.047851                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13533.020928                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8818.134219                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13437.093740                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.047851                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13533.020928                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8818.134219                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        66163                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             3838                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    17.238927                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358390                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       358390                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst       358390                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       358390                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst       358390                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       358390                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1808723                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      4165797                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4732179                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10706699                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1808723                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      4165797                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst      4732179                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10706699                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1808723                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      4165797                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst      4732179                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10706699                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  22495257500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  53372390500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  60789325843                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 136656973843                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  22495257500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  53372390500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  60789325843                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 136656973843                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  22495257500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  53372390500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  60789325843                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 136656973843                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016038                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.016038                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014395                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.052858                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.082047                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.016038                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12763.688775                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12763.688775                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12437.093740                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12812.047851                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.948102                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12763.688775                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    42213                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                42213                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         6241                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        31075                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            9                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        42204                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.853000                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev   141.748477                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047        42202    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::6144-8191            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        42204                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        37325                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 26882.732753                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 23412.636165                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 18338.779624                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        37004     99.14%     99.14% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.01%     99.15% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          275      0.74%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143            7      0.02%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           19      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            6      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            7      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        37325                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   2908388356                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.649897                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.477002                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1018236500     35.01%     35.01% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1890151856     64.99%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   2908388356                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        31075     83.28%     83.28% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         6241     16.72%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        37316                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        42213                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        42213                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        37316                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        37316                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        79529                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    23441762                       # DTB read hits
system.cpu1.dtb.read_misses                     32033                       # DTB read misses
system.cpu1.dtb.write_hits                   21401339                       # DTB write hits
system.cpu1.dtb.write_misses                    10180                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1255                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               6610                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   20769                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1303                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2968                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                23473795                       # DTB read accesses
system.cpu1.dtb.write_accesses               21411519                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         44843101                       # DTB hits
system.cpu1.dtb.misses                          42213                       # DTB misses
system.cpu1.dtb.accesses                     44885314                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    21791                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                21791                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1072                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        19067                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        21791                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          21791    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        21791                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        20139                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29400.094344                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25404.974001                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23277.059653                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        19797     98.30%     98.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          293      1.45%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143            9      0.04%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           20      0.10%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           14      0.07%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        20139                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        19067     94.68%     94.68% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         1072      5.32%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        20139                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        21791                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        21791                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        20139                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        20139                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        41930                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   125648425                       # ITB inst hits
system.cpu1.itb.inst_misses                     21791                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1255                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               6610                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   15047                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               125670216                       # ITB inst accesses
system.cpu1.itb.hits                        125648425                       # DTB hits
system.cpu1.itb.misses                          21791                       # DTB misses
system.cpu1.itb.accesses                    125670216                       # DTB accesses
system.cpu1.numCycles                      1254117353                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  125557631                       # Number of instructions committed
system.cpu1.committedOps                    147479999                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            135255426                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                113335                       # Number of float alu accesses
system.cpu1.num_func_calls                    7243553                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     19326205                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   135255426                       # number of integer instructions
system.cpu1.num_fp_insts                       113335                       # number of float instructions
system.cpu1.num_int_register_reads          197658337                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         107430286                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              186014                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              88856                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            33354822                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           33290251                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     44840861                       # number of memory refs
system.cpu1.num_load_insts                   23441337                       # Number of load instructions
system.cpu1.num_store_insts                  21399524                       # Number of store instructions
system.cpu1.num_idle_cycles              1222996834.683689                       # Number of idle cycles
system.cpu1.num_busy_cycles              31120518.316311                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.024815                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.975185                       # Percentage of idle cycles
system.cpu1.Branches                         28029112                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                102409853     69.40%     69.40% # Class of executed instruction
system.cpu1.op_class::IntMult                  296498      0.20%     69.60% # Class of executed instruction
system.cpu1.op_class::IntDiv                    11247      0.01%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             12292      0.01%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::MemRead                23441337     15.88%     85.50% # Class of executed instruction
system.cpu1.op_class::MemWrite               21399524     14.50%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 147570793                       # Class of executed instruction
system.cpu2.branchPred.lookups               45471146                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         31973875                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          2129408                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            32992156                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               23695609                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            71.821948                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                5443991                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            364384                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                   113177                       # Table walker walks requested
system.cpu2.dtb.walker.walksLong               113177                       # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         8706                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        39954                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples       113177                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0         113177    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total       113177                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples        48660                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 26968.937526                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 23542.983422                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 19014.556180                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535        48252     99.16%     99.16% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607          346      0.71%     99.87% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143            8      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679           19      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-393215            9      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751           17      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-524287            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total        48660                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000225500                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000225500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000225500                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K        39954     82.11%     82.11% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M         8706     17.89%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total        48660                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data       113177                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total       113177                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        48660                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        48660                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total       161837                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    32304432                       # DTB read hits
system.cpu2.dtb.read_misses                     94453                       # DTB read misses
system.cpu2.dtb.write_hits                   28220489                       # DTB write hits
system.cpu2.dtb.write_misses                    18724                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1254                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid               8683                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   25531                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      107                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  2547                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                     4198                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                32398885                       # DTB read accesses
system.cpu2.dtb.write_accesses               28239213                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         60524921                       # DTB hits
system.cpu2.dtb.misses                         113177                       # DTB misses
system.cpu2.dtb.accesses                     60638098                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                    29761                       # Table walker walks requested
system.cpu2.itb.walker.walksLong                29761                       # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1942                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3        24191                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples        29761                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0          29761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total        29761                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples        26133                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 29367.313359                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25512.670377                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 21362.014142                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767        13922     53.27%     53.27% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535        11740     44.92%     98.20% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303            1      0.00%     98.20% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839          361      1.38%     99.58% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607           66      0.25%     99.84% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375            4      0.02%     99.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143            6      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911           20      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679            6      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447            4      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::393216-425983            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total        26133                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K        24191     92.57%     92.57% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M         1942      7.43%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total        26133                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        29761                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total        29761                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        26133                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total        26133                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total        55894                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    78881959                       # ITB inst hits
system.cpu2.itb.inst_misses                     29761                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1254                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid               8683                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   18937                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                    67145                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                78911720                       # ITB inst accesses
system.cpu2.itb.hits                         78881959                       # DTB hits
system.cpu2.itb.misses                          29761                       # DTB misses
system.cpu2.itb.accesses                     78911720                       # DTB accesses
system.cpu2.numCycles                      7033284242                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                  166119965                       # Number of instructions committed
system.cpu2.committedOps                    194630787                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                     16695727                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                     1592                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                 95760838731                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             42.338585                       # CPI: cycles per instruction
system.cpu2.ipc                              0.023619                       # IPC: instructions per cycle
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                      311878847                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     6721405395                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               81889340                       # Number of BP lookups
system.cpu3.branchPred.condPredicted         56169669                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect          3380866                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups            55493963                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits               40219158                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            72.474835                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS               10439836                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect            109057                       # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                   587832                       # Table walker walks requested
system.cpu3.dtb.walker.walksLong               587832                       # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2        11030                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        61410                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore       367052                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples       220780                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean  2589.344596                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 16088.611072                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535       219110     99.24%     99.24% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071          781      0.35%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607          609      0.28%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143           97      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679          110      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215           29      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751           21      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287           18      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total       220780                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples       282413                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 23694.059764                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 19376.224176                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 20061.278653                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535       276792     98.01%     98.01% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3971      1.41%     99.42% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607         1088      0.39%     99.80% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143          102      0.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679          289      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215           71      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751           75      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287           16      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::589824-655359            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total       282413                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -34655191100                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean    -0.302186                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -35339735100    101.98%    101.98% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7    378573500     -1.09%    100.88% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11    130659500     -0.38%    100.51% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15     81429500     -0.23%    100.27% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19     31558000     -0.09%    100.18% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23     16139000     -0.05%    100.13% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27     19404500     -0.06%    100.08% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31     22341500     -0.06%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35      4213500     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39       186000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43        24000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47         5000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51         6000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::52-55         2500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::56-59         1500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -34655191100                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K        61410     84.77%     84.77% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M        11030     15.23%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total        72440                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       587832                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       587832                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        72440                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        72440                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total       660272                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                    65734744                       # DTB read hits
system.cpu3.dtb.read_misses                    407673                       # DTB read misses
system.cpu3.dtb.write_hits                   50830095                       # DTB write hits
system.cpu3.dtb.write_misses                   180159                       # DTB write misses
system.cpu3.dtb.flush_tlb                        1253                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid              13974                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                    340                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                   34753                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                       86                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                  6443                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                    35079                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                66142417                       # DTB read accesses
system.cpu3.dtb.write_accesses               51010254                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                        116564839                       # DTB hits
system.cpu3.dtb.misses                         587832                       # DTB misses
system.cpu3.dtb.accesses                    117152671                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                    63234                       # Table walker walks requested
system.cpu3.itb.walker.walksLong                63234                       # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2096                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3        42908                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore         8590                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples        54644                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  2021.164263                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 13009.185259                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767        53981     98.79%     98.79% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535          301      0.55%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303           60      0.11%     99.45% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071           76      0.14%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839          174      0.32%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607           22      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375            8      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143            8      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::294912-327679            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total        54644                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples        53594                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 30266.951524                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 25142.604210                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 25912.141235                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535        52174     97.35%     97.35% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071          327      0.61%     97.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-196607          902      1.68%     99.64% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-262143           65      0.12%     99.76% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679           86      0.16%     99.93% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215           19      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-458751           14      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-524287            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total        53594                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -34657916600                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     0.961535                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev     0.183175                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0    -1283225616      3.70%      3.70% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1   -33417551984     96.42%    100.12% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2       37526500     -0.11%    100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3        4293000     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4         605000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5         220500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6         216000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -34657916600                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K        42908     95.34%     95.34% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M         2096      4.66%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total        45004                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        63234                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total        63234                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        45004                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total        45004                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total       108238                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                    57820095                       # ITB inst hits
system.cpu3.itb.inst_misses                     63234                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                        1253                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid              13974                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                    340                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                   26508                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                   125417                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                57883329                       # ITB inst accesses
system.cpu3.itb.hits                         57820095                       # DTB hits
system.cpu3.itb.misses                          63234                       # DTB misses
system.cpu3.itb.accesses                     57883329                       # DTB accesses
system.cpu3.numCycles                       434126905                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles         146156253                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                     363700570                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   81889340                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches          50658994                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                    264117346                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                7731870                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                   1657260                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles               10621                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles             2103                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles      3389024                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles       101744                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles         6028                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                 57676698                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes              2068277                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                  25207                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples         419306139                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.016419                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.270112                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0               329556532     78.60%     78.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                11088732      2.64%     81.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                11228658      2.68%     83.92% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 8092801      1.93%     85.85% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                18140495      4.33%     90.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                 5492721      1.31%     91.48% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 6039069      1.44%     92.92% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                 5230958      1.25%     94.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                24436173      5.83%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total           419306139                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.188630                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.837775                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles               117967967                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles            225080995                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                 64189505                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles              9003410                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles               3062237                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved            11922856                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred               815112                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts             398264937                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts              2526332                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles               3062237                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles               122799246                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles               19956782                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles     172569750                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                 68252780                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles             32663221                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts             389247398                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                82681                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents               1469691                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents               1381042                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents              19259922                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents            2209                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands          374365889                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            605949673                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups       460740509                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups           465469                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps            317859037                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                56506847                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts          10256222                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts       9051847                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                 50890020                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads            62384560                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores           53396526                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          8272508                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         8814741                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                 368973435                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded           10287007                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                371458257                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued           527403                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined       47542551                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     30606523                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved        220793                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples    419306139                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.885888                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.625743                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0          272370865     64.96%     64.96% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1           63755387     15.20%     80.16% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2           26527410      6.33%     86.49% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3           18802792      4.48%     90.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4           14265193      3.40%     94.38% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5            9871415      2.35%     96.73% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6            6899561      1.65%     98.38% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7            4083667      0.97%     99.35% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8            2729849      0.65%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total      419306139                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                1874044     25.07%     25.07% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                 14207      0.19%     25.26% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                   1529      0.02%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.29% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead               3115796     41.69%     66.97% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite              2468334     33.03%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass               19      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu            252023231     67.85%     67.85% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult              873366      0.24%     68.08% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                40952      0.01%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc         37311      0.01%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead            67010678     18.04%     86.14% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite           51472700     13.86%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total             371458257                       # Type of FU issued
system.cpu3.iq.rate                          0.855644                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                    7473910                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.020120                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads        1169596628                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes        426913403                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses    357682131                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads             627338                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes            312499                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses       278370                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses             378596824                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                 335324                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads         2893628                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      9605329                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses        12315                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation       430621                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores      5363996                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads      2422339                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked      5589935                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles               3062237                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles               10687906                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles              7763233                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts          379342357                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts          1032736                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts             62384560                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts            53396526                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts           8880600                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                160790                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents              7539596                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents        430621                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect       1536012                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect      1351234                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts             2887246                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts            367483062                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts             65729081                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts          3395466                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        81915                       # number of nop insts executed
system.cpu3.iew.exec_refs                   116559779                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                68181123                       # Number of branches executed
system.cpu3.iew.exec_stores                  50830698                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.846488                       # Inst execution rate
system.cpu3.iew.wb_sent                     358682036                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                    357960501                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                176824720                       # num instructions producing a value
system.cpu3.iew.wb_consumers                308531947                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      0.824553                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.573116                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts       47576745                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls       10066214                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts          2576993                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples    411229636                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.806649                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.806100                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0    288483917     70.15%     70.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1     61981955     15.07%     85.22% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2     20267968      4.93%     90.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      9217498      2.24%     92.39% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4      6652848      1.62%     94.01% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5      4003479      0.97%     94.99% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6      3757671      0.91%     95.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7      2541712      0.62%     96.52% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8     14322588      3.48%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total    411229636                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts           282128500                       # Number of instructions committed
system.cpu3.commit.committedOps             331717886                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                     100811760                       # Number of memory references committed
system.cpu3.commit.loads                     52779230                       # Number of loads committed
system.cpu3.commit.membars                    2341382                       # Number of memory barriers committed
system.cpu3.commit.branches                  63187183                       # Number of branches committed
system.cpu3.commit.fp_insts                    266447                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                304028105                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             8134067                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu       230158153     69.38%     69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult         685246      0.21%     69.59% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv           30654      0.01%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.60% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc        32073      0.01%     69.61% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.61% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.61% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.61% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead       52779230     15.91%     85.52% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite      48032530     14.48%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total        331717886                       # Class of committed instruction
system.cpu3.commit.bw_lim_events             14322588                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                   773873016                       # The number of ROB reads
system.cpu3.rob.rob_writes                  766677768                       # The number of ROB writes
system.cpu3.timesIdled                        2386400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                       14820766                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                 98598665590                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                  282128500                       # Number of Instructions Simulated
system.cpu3.committedOps                    331717886                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.538756                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.538756                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.649876                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.649876                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads               433777374                       # number of integer regfile reads
system.cpu3.int_regfile_writes              254753352                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                   550692                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                  344140                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                 80727735                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                81413298                       # number of cc regfile writes
system.cpu3.misc_regfile_reads              763399482                       # number of misc regfile reads
system.cpu3.misc_regfile_writes              10252205                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40277                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40277                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136543                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136543                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47710                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122592                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353640                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47730                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155722                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334304                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334304                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492112                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             27944000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                4000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             9762000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy               84000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            18725000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               37000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           256543158                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            57567000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            67102000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115465                       # number of replacements
system.iocache.tags.tagsinuse               10.434887                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13089149976509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.535229                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.899658                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.220952                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.431229                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652180                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039713                       # Number of tag accesses
system.iocache.tags.data_accesses             1039713                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8820                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8857                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8820                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8860                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8820                       # number of overall misses
system.iocache.overall_misses::total             8860                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide    731246845                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    731246845                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   6288189313                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6288189313                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide    731246845                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    731246845                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide    731246845                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    731246845                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8820                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8857                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8820                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8860                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8820                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8860                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 82907.805556                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 82561.459298                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58953.248641                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58953.248641                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 82907.805556                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 82533.503950                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 82907.805556                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 82533.503950                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         14483                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 1449                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.995169                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide         3943                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         3943                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        48464                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        48464                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide         3943                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         3943                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide         3943                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         3943                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide    534096845                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    534096845                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3864989313                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3864989313                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide    534096845                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    534096845                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide    534096845                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    534096845                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.447052                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.445185                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.454361                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.454361                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.447052                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.445034                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.447052                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.445034                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135454.436977                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 135454.436977                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79749.696950                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79749.696950                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135454.436977                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 135454.436977                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135454.436977                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 135454.436977                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1727571                       # number of replacements
system.l2c.tags.tagsinuse                65366.434127                       # Cycle average of tags in use
system.l2c.tags.total_refs                   52377191                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1790828                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    29.247472                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35675.383365                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   150.314968                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   221.842308                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3453.336849                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     8628.573919                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    25.870351                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    46.456847                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      201.612441                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2287.318567                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    59.687727                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker    74.075629                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1384.134493                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3678.892327                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    90.341060                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker   136.749974                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     2263.424269                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     6988.419034                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.544363                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002294                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003385                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052694                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.131662                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000395                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000709                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.003076                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.034902                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000911                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.001130                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.021120                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.056135                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001378                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker     0.002087                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.034537                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.106635                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997413                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62986                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          271                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          557                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2824                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5088                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54403                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.961090                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                469232047                       # Number of tag accesses
system.l2c.tags.data_accesses               469232047                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       235826                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       121184                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        81459                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        45184                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       191869                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        62064                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker       348446                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker       115721                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1201753                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         8924778                       # number of Writeback hits
system.l2c.Writeback_hits::total              8924778                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            4561                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1493                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            2040                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data            3109                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               11203                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data             1                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           686392                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           217346                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           284271                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data           485127                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1673136                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       5986561                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       1802233                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst       4138498                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst       4701144                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          16628436                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3068738                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       952648                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data      1326974                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data      2219552                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          7567912                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       272293                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data        86845                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data       121922                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data       214200                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           695260                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        235826                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        121184                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             5986561                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3755130                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         81459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         45184                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1802233                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             1169994                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        191869                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         62064                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             4138498                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             1611245                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker        348446                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker        115721                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst             4701144                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data             2704679                       # number of demand (read+write) hits
system.l2c.demand_hits::total                27071237                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       235826                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       121184                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            5986561                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3755130                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        81459                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        45184                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1802233                       # number of overall hits
system.l2c.overall_hits::cpu1.data            1169994                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       191869                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        62064                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            4138498                       # number of overall hits
system.l2c.overall_hits::cpu2.data            1611245                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker       348446                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker       115721                       # number of overall hits
system.l2c.overall_hits::cpu3.inst            4701144                       # number of overall hits
system.l2c.overall_hits::cpu3.data            2704679                       # number of overall hits
system.l2c.overall_hits::total               27071237                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2935                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2779                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          724                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker          700                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker         1192                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker          941                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker         1791                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker         1697                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                12759                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         16043                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          5251                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          6949                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data         11616                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             39859                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         366292                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          91622                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data         117894                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data         230007                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             805815                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        41869                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         6490                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst        27299                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst        31020                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total          106678                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       153106                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        34842                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        56209                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data       101610                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         345767                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       424081                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        25091                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data        36365                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data        65672                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         551209                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2935                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2779                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             41869                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            519398                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          724                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          700                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              6490                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            126464                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker         1192                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker          941                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             27299                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data            174103                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker         1791                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker         1697                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst             31020                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data            331617                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1271019                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2935                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2779                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            41869                       # number of overall misses
system.l2c.overall_misses::cpu0.data           519398                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          724                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          700                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             6490                       # number of overall misses
system.l2c.overall_misses::cpu1.data           126464                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker         1192                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker          941                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            27299                       # number of overall misses
system.l2c.overall_misses::cpu2.data           174103                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker         1791                       # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker         1697                       # number of overall misses
system.l2c.overall_misses::cpu3.inst            31020                       # number of overall misses
system.l2c.overall_misses::cpu3.data           331617                       # number of overall misses
system.l2c.overall_misses::total              1271019                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     97227500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker     96353000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker    165331500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker    128011000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    247954000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker    236571000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      971448000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    199570000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data    267940000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data    453413000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    920923000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  12038938500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data  15663963000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data  35455675000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  63158576500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    853135000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst   3650715000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst   4222794500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   8726644500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   4662398000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   7598847500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data  14323981000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  26585226500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data   3295489000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data   5124829000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data  10352584000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  18772902000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     97227500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     96353000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    853135000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  16701336500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker    165331500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker    128011000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   3650715000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data  23262810500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker    247954000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker    236571000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst   4222794500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data  49779656000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     99441895500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     97227500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     96353000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    853135000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  16701336500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker    165331500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker    128011000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   3650715000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data  23262810500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker    247954000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker    236571000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst   4222794500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data  49779656000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    99441895500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       238761                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       123963                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        82183                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        45884                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       193061                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        63005                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker       350237                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker       117418                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1214512                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      8924778                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          8924778                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        20604                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         6744                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         8989                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data        14725                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           51062                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1052684                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       308968                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       402165                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data       715134                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2478951                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6028430                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1808723                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst      4165797                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst      4732164                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      16735114                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3221844                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       987490                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data      1383183                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data      2321162                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7913679                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       696374                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       111936                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data       158287                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data       279872                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1246469                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       238761                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       123963                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6028430                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4274528                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        82183                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        45884                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1808723                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1296458                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       193061                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        63005                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         4165797                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         1785348                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker       350237                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker       117418                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst         4732164                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data         3036296                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            28342256                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       238761                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       123963                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6028430                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4274528                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        82183                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        45884                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1808723                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1296458                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       193061                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        63005                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        4165797                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        1785348                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker       350237                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker       117418                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst        4732164                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data        3036296                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           28342256                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.012293                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.022418                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008810                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.015256                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.006174                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.014935                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.005114                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.014453                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.010505                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.778635                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.778618                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.773056                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.788862                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.780600                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.750000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.347960                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.296542                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.293148                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.321628                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.325063                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006945                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.003588                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006553                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.006555                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.006375                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.047521                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.035283                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.040637                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.043775                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.043692                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.608985                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.224155                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data     0.229741                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data     0.234650                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.442216                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.012293                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.022418                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006945                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.121510                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008810                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.015256                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.003588                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.097546                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.006174                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.014935                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.006553                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.097518                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.005114                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker     0.014453                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.006555                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.109218                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.044845                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.012293                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.022418                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006945                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.121510                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008810                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.015256                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.003588                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.097546                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.006174                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.014935                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.006553                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.097518                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.005114                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker     0.014453                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.006555                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.109218                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.044845                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 76138.255349                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38006.094077                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38558.065909                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 39033.488292                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 23104.518427                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131397.901159                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132864.802280                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 154150.417161                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 78378.506853                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131453.775039                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133730.722737                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136131.350741                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81803.600555                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133815.452615                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135189.160099                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 140970.189942                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 76887.691711                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 131341.477024                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 140927.512718                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 157640.760141                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 34057.684109                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131453.775039                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 132063.958913                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 133730.722737                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 133615.219152                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 136131.350741                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 150111.894143                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 78237.929960                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134292.127072                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137647.142857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131453.775039                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 132063.958913                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 138700.922819                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 136037.194474                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 133730.722737                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 133615.219152                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138444.444444                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 139405.421332                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 136131.350741                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 150111.894143                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 78237.929960                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1483665                       # number of writebacks
system.l2c.writebacks::total                  1483665                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker           12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           27                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                39                       # number of ReadReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            6                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker           12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker           27                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 45                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker           12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker           27                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                45                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          724                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          700                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker         1192                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          941                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1779                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker         1670                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7006                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks          338                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total          338                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         5251                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         6949                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data        11616                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        23816                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        91622                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data       117894                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data       230007                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        439523                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         6490                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        27299                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        31020                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        64809                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        34842                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        56207                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data       101606                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       192655                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        25091                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data        36365                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data        65672                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       127128                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          724                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          700                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         6490                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       126464                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker         1192                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker          941                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        27299                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data       174101                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker         1779                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker         1670                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst        31020                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data       331613                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           703993                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          724                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          700                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         6490                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       126464                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker         1192                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker          941                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        27299                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data       174101                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker         1779                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker         1670                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst        31020                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data       331613                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          703993                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         7202                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6366                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         6575                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        20143                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6701                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         5973                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6301                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        18975                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13903                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data        12339                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        12876                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        39118                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    896511500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    370929500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    491743500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    821824000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1684497000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        72000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        72000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  11122718500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  14485023000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  33155605000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  58763346500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    788235000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   3377725000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3912594500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   8078554500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   4313978000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   7036589000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  13307454500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  24658021500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   3044579000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   4761179000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   9695864000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  17501622000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    788235000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  15436696500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   3377725000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data  21521612000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst   3912594500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data  46463059500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  92396434000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     89987500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     89353000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    788235000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  15436696500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker    153411500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    118601000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   3377725000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data  21521612000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    228621000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    216537500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst   3912594500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data  46463059500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  92396434000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1257349000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1099961500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1114322500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3471633000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1204367500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1063346000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1092408000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   3360121500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2461716500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2163307500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2206730500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6831754500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005769                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.778618                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.773056                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.788862                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.466413                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.296542                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.293148                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.321628                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.177302                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003873                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.035283                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.040636                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.043774                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.024345                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.224155                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.229741                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.234650                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.101991                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.097546                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.097517                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.109216                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.024839                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008810                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.015256                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.003588                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.097546                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.006174                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.014935                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006553                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.097517                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.005079                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.014223                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.006555                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.109216                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.024839                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127963.388524                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70639.782898                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70764.642395                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70749.311295                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70729.635539                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        72000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121397.901159                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122864.802280                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 144150.417161                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 133698.001015                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124651.738185                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123815.452615                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125190.616827                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130971.148357                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127990.560847                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121341.477024                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 130927.512718                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 147640.760141                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 137669.293940                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122063.958913                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123615.671363                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 140112.298070                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 131246.239664                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121453.775039                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122063.958913                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123730.722737                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123615.671363                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126131.350741                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 140112.298070                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 131246.239664                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174583.310192                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 172786.914860                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169478.707224                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172349.352132                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179729.517982                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178025.447849                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173370.576099                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177081.501976                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177063.691290                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175322.757112                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171383.232370                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 174644.779897                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76751                       # Transaction distribution
system.membus.trans_dist::ReadResp             550767                       # Transaction distribution
system.membus.trans_dist::WriteReq              33656                       # Transaction distribution
system.membus.trans_dist::WriteResp             33656                       # Transaction distribution
system.membus.trans_dist::Writeback           1590295                       # Transaction distribution
system.membus.trans_dist::CleanEvict           250132                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            40589                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           40592                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1356297                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1356297                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        474016                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122592                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6786                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5542839                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5672278                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342541                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6014819                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155722                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    211708448                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    211877938                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7303680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7303680                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               219181618                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1560                       # Total snoops (count)
system.membus.snoop_fanout::samples           3931023                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3931023    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3931023                       # Request fanout histogram
system.membus.reqLayer0.occupancy            67063498                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                2000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1693000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          4875978841                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4492458378                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          103510165                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     57525316                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     29151092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3060                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2399                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2399                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            1748199                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          26397420                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33656                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33656                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          9662082                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict        19582233                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           51062                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          51066                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2478951                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2478951                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      16735129                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7917622                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1294933                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1246469                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     50288517                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35153401                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       878892                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2158697                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              88479507                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1071219732                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1236530654                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3178896                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      7750232                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2318679514                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2264699                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         60538896                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.012147                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.109543                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               59803521     98.79%     98.79% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 735375      1.21%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           60538896                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        23067770487                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           767706                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       16065319902                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        9498707196                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         310622695                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         847575032                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------