path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.276915                       # Number of seconds simulated
sim_ticks                                51276914665000                       # Number of ticks simulated
final_tick                               51276914665000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 268578                       # Simulator instruction rate (inst/s)
host_op_rate                                   315601                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            16108564651                       # Simulator tick rate (ticks/s)
host_mem_usage                                 678484                       # Number of bytes of host memory used
host_seconds                                  3183.21                       # Real time elapsed on the host
sim_insts                                   854941205                       # Number of instructions simulated
sim_ops                                    1004625181                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        83328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        90048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2407092                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         43660040                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        20288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        19392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           699200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          6175552                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker        32448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker        28928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          1537920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          8615616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker        64768                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker        60352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst          1793920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data         16163456                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        420032                       # Number of bytes read from this memory
system.physmem.bytes_read::total             81872380                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2407092                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       699200                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      1537920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst      1793920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6438132                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     69681088                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          69701668                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1302                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1407                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             78018                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            682201                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          317                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          303                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10925                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             96493                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker          507                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker          452                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             24030                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            134619                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker         1012                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker          943                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst             28030                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data            252554                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6563                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1319676                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1088767                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1091340                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1625                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1756                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               46943                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              851456                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           396                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker           378                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               13636                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              120435                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           633                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker           564                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               29992                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              168021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1263                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker          1177                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst               34985                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data              315219                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8191                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1596671                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          46943                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          13636                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          29992                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst          34985                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             125556                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1358917                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1359319                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1358917                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1756                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              46943                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             851857                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          396                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker          378                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              13636                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             120435                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          633                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker          564                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              29992                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             168021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1263                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker         1177                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst              34985                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data             315219                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8191                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2955990                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        550245                       # Number of read requests accepted
system.physmem.writeReqs                       481237                       # Number of write requests accepted
system.physmem.readBursts                      550245                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     481237                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 35190464                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     25216                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  30797568                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  35215680                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               30799168                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      394                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          68304                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               35436                       # Per bank write bursts
system.physmem.perBankRdBursts::1               39868                       # Per bank write bursts
system.physmem.perBankRdBursts::2               34215                       # Per bank write bursts
system.physmem.perBankRdBursts::3               34743                       # Per bank write bursts
system.physmem.perBankRdBursts::4               34056                       # Per bank write bursts
system.physmem.perBankRdBursts::5               38097                       # Per bank write bursts
system.physmem.perBankRdBursts::6               32100                       # Per bank write bursts
system.physmem.perBankRdBursts::7               33790                       # Per bank write bursts
system.physmem.perBankRdBursts::8               31750                       # Per bank write bursts
system.physmem.perBankRdBursts::9               37588                       # Per bank write bursts
system.physmem.perBankRdBursts::10              34493                       # Per bank write bursts
system.physmem.perBankRdBursts::11              35548                       # Per bank write bursts
system.physmem.perBankRdBursts::12              32409                       # Per bank write bursts
system.physmem.perBankRdBursts::13              32208                       # Per bank write bursts
system.physmem.perBankRdBursts::14              31335                       # Per bank write bursts
system.physmem.perBankRdBursts::15              32215                       # Per bank write bursts
system.physmem.perBankWrBursts::0               29077                       # Per bank write bursts
system.physmem.perBankWrBursts::1               32864                       # Per bank write bursts
system.physmem.perBankWrBursts::2               29906                       # Per bank write bursts
system.physmem.perBankWrBursts::3               31279                       # Per bank write bursts
system.physmem.perBankWrBursts::4               30178                       # Per bank write bursts
system.physmem.perBankWrBursts::5               33497                       # Per bank write bursts
system.physmem.perBankWrBursts::6               28885                       # Per bank write bursts
system.physmem.perBankWrBursts::7               30667                       # Per bank write bursts
system.physmem.perBankWrBursts::8               29490                       # Per bank write bursts
system.physmem.perBankWrBursts::9               32863                       # Per bank write bursts
system.physmem.perBankWrBursts::10              29440                       # Per bank write bursts
system.physmem.perBankWrBursts::11              30986                       # Per bank write bursts
system.physmem.perBankWrBursts::12              28208                       # Per bank write bursts
system.physmem.perBankWrBursts::13              28238                       # Per bank write bursts
system.physmem.perBankWrBursts::14              27304                       # Per bank write bursts
system.physmem.perBankWrBursts::15              28330                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
system.physmem.totGap                    51275914443000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  550245                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 481237                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    388368                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    101483                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     36821                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     22989                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        19                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7785                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     8646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    19148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    23177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    26333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    27904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    27768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    28936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    29500                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    30869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    30606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    30707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    29539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    30452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    32548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    28468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    28582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    27212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      466                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       35                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       273820                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      240.988445                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     145.225402                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     282.507263                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         125281     45.75%     45.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        68336     24.96%     70.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        24972      9.12%     79.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        12598      4.60%     84.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         9315      3.40%     87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         5687      2.08%     89.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4750      1.73%     91.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3875      1.42%     93.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19006      6.94%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         273820                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         27019                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.349051                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       10.037322                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-15             3255     12.05%     12.05% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16-31           21302     78.84%     90.89% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-47            1883      6.97%     97.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::48-63             429      1.59%     99.44% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-79              82      0.30%     99.75% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::80-95              50      0.19%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-111              5      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::112-127             5      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-143             2      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::144-159             2      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-175             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::208-223             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::240-255             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::336-351             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           27019                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         27019                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.810134                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.198144                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.395128                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                20      0.07%      0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                13      0.05%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                7      0.03%      0.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              44      0.16%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           25225     93.36%     93.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             422      1.56%     95.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             332      1.23%     96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             185      0.68%     97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             112      0.41%     97.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             204      0.76%     98.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              76      0.28%     98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              16      0.06%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              19      0.07%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.07%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              23      0.09%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.05%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             191      0.71%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              20      0.07%     99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              23      0.09%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              16      0.06%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               2      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.05%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             5      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           27019                       # Writes before turning the bus around for reads
system.physmem.totQLat                    11443674557                       # Total ticks spent queuing
system.physmem.totMemAccLat               21753380807                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2749255000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20812.32                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39562.32                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.69                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.60                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.69                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.60                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.72                       # Average write queue length when enqueuing
system.physmem.readRowHits                     421327                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    335914                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.80                       # Row buffer hit rate for writes
system.physmem.avgGap                     49710915.40                       # Average gap between requests
system.physmem.pageHitRate                      73.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1064213640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  579096375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                2201979000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               1596367440                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3310527770160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1178433187650                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           30013431943500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34507834557765                       # Total energy per rank (pJ)
system.physmem_0.averagePower              666.879372                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   48871742574250                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1692498860000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    121731845500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1005865560                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  547383375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                2086788600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               1521886320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3310527770160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1173650278320                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29856307058250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34345647030585                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.211846                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   48878835578992                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1692498860000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    114595771758                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    90556                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong                90556                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples        90556                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          90556    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        90556                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 391820965788                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.505629                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -198115997962    -50.56%    -50.56% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1   589936963750    150.56%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 391820965788                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        66622     84.81%     84.81% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11928     15.19%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        78550                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90556                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90556                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78550                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78550                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       169106                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    64673225                       # DTB read hits
system.cpu0.dtb.read_misses                     68448                       # DTB read misses
system.cpu0.dtb.write_hits                   58639149                       # DTB write hits
system.cpu0.dtb.write_misses                    22108                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1188                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              15858                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    413                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   41832                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2761                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     7632                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                64741673                       # DTB read accesses
system.cpu0.dtb.write_accesses               58661257                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        123312374                       # DTB hits
system.cpu0.dtb.misses                          90556                       # DTB misses
system.cpu0.dtb.accesses                    123402930                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    54313                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                54313                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        54313                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          54313    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        54313                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 391820965788                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.505731                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -198155892462    -50.57%    -50.57% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   589976858250    150.57%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 391820965788                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        47491     95.01%     95.01% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2494      4.99%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        49985                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        54313                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        54313                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49985                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49985                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       104298                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   343634485                       # ITB inst hits
system.cpu0.itb.inst_misses                     54313                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1188                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              15858                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    413                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   29675                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               343688798                       # ITB inst accesses
system.cpu0.itb.hits                        343634485                       # DTB hits
system.cpu0.itb.misses                          54313                       # DTB misses
system.cpu0.itb.accesses                    343688798                       # DTB accesses
system.cpu0.numCycles                       414612673                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  343491459                       # Number of instructions committed
system.cpu0.committedOps                    404038438                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            371064332                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                366662                       # Number of float alu accesses
system.cpu0.num_func_calls                   20606328                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     52246055                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   371064332                       # number of integer instructions
system.cpu0.num_fp_insts                       366662                       # number of float instructions
system.cpu0.num_int_register_reads          542308147                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         294610052                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              579925                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             335816                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            90131130                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           89914881                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    123386712                       # number of memory refs
system.cpu0.num_load_insts                   64730993                       # Number of load instructions
system.cpu0.num_store_insts                  58655719                       # Number of store instructions
system.cpu0.num_idle_cycles              404807579.503922                       # Number of idle cycles
system.cpu0.num_busy_cycles              9805093.496078                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.023649                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.976351                       # Percentage of idle cycles
system.cpu0.Branches                         76646162                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                279922003     69.24%     69.24% # Class of executed instruction
system.cpu0.op_class::IntMult                  872785      0.22%     69.46% # Class of executed instruction
system.cpu0.op_class::IntDiv                    43154      0.01%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             49919      0.01%     69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.48% # Class of executed instruction
system.cpu0.op_class::MemRead                64730993     16.01%     85.49% # Class of executed instruction
system.cpu0.op_class::MemWrite               58655719     14.51%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 404274574                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16555                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          9760623                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999693                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          295406617                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9761135                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.263552                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   495.408382                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.358891                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     7.391492                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data     3.840928                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.967594                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010467                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.014437                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.007502                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1251530357                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1251530357                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     60440714                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     19079891                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     26457743                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data     46030584                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      152008932                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     55470897                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     17632949                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     23585193                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data     38751939                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     135440978                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       163149                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        46374                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        80888                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112448                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       402859                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       132862                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data        44988                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data        52244                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data        99564                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       329658                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1435046                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       431760                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       583467                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       975735                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3426008                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1528481                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       469205                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       629772                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1126896                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3754354                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    115911611                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     36712840                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     50042936                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     84782523                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       287449910                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    116074760                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     36759214                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     50123824                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     84894971                       # number of overall hits
system.cpu0.dcache.overall_hits::total      287852769                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2074038                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       622706                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       950512                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data      3520436                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7167692                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       834575                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       257970                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       650618                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      3386065                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      5129228                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       508589                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       146296                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       212076                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data       322320                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1189281                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       666999                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       114735                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data       152937                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data       292722                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1227393                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        94072                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37658                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        46539                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       187643                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       365912                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2908613                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       880676                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1601130                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      6906501                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      12296920                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3417202                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1026972                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1813206                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      7228821                       # number of overall misses
system.cpu0.dcache.overall_misses::total     13486201                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9559498000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14919986000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  53204647500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  77684131500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6931134000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17483945500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  95592660029                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 120007739529                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   2732317500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   4244347000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  10498361311                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  17475025811                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    520498500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    650995000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2326488500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3497982000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       142500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       142500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  16490632000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  32403931500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 148797307529                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 197691871029                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  16490632000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  32403931500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 148797307529                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 197691871029                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     62514752                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     19702597                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     27408255                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data     49551020                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    159176624                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     56305472                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     17890919                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     24235811                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data     42138004                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    140570206                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       671738                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       192670                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       292964                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       434768                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1592140                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       799861                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       159723                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       205181                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       392286                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1557051                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1529118                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       469418                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       630006                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1163378                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3791920                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1528481                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       469205                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       629772                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1126900                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3754358                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    118820224                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     37593516                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     51644066                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     91689024                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    299746830                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    119491962                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     37786186                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     51937030                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     92123792                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    301338970                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033177                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031605                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.034680                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071047                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.045030                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014822                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014419                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.026845                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.080357                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.036489                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.757124                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.759309                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.723898                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.741361                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.746970                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.833894                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.718337                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.745376                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.746195                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788281                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.061520                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080223                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.073871                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.161292                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.096498                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024479                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023426                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.031003                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.075325                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.041024                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028598                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027179                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034912                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.078469                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.044754                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15351.543104                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15696.788678                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15113.084715                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10838.095652                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26867.984649                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26872.827834                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 28231.194625                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23396.842474                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23814.158714                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27752.257465                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35864.613220                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14237.514644                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13821.724468                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.160468                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12398.482757                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9559.626358                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        35625                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        35625                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18724.970364                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20238.163984                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21544.528485                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16076.535509                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16057.528345                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17871.070082                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20583.897088                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14658.825790                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     12159694                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        10325                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           863086                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            292                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.088624                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    35.359589                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7548701                       # number of writebacks
system.cpu0.dcache.writebacks::total          7548701                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3073                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       106555                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1929145                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2038773                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         2189                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       286613                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2805614                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3094416                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           22                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2153                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         2175                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8609                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10642                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       114897                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       134148                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         5262                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       393168                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      4734759                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      5133189                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         5262                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       393168                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      4734759                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      5133189                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       619633                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       843957                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1591291                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3054881                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       255781                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       364005                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       580451                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1200237                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       146073                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       211968                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       317579                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       675620                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       114735                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       152915                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       290569                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       558219                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29049                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        35897                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        72746                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137692                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       875414                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      1207962                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data      2171742                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4255118                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1021487                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      1419930                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data      2489321                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4930738                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6070                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4638                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         5330                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16038                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         5514                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4225                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         5069                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        14808                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        11584                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8863                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        10399                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        30846                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   8870276000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12358412500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  24290690000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45519378500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6598387000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9284220500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17173491540                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33056099040                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2440625000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3114719000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   4962911000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10518255000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   2617582500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   4091120500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10122943811                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  16831646811                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    372258500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    460319500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    958480000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1791058000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       138500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       138500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  15468663000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  21642633000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  41464181540                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  78575477540                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  17909288000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  24757352000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  46427092540                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  89093732540                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1079003500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    788343500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    908401000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2775748000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    999912000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    723848500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data    894544000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2618304500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2078915500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   1512192000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   1802945000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5394052500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031449                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030792                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.032114                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019192                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014297                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.015019                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.013775                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008538                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.758151                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.723529                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.730456                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.424347                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.718337                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.745269                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.740707                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.358510                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061883                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.056979                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.062530                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036312                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023286                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023390                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023686                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.014196                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027033                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027339                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027021                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.016363                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14315.370550                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14643.414890                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15264.769297                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14900.540643                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25797.017761                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25505.749921                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29586.462148                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27541.309791                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16708.255461                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14694.288761                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15627.327374                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15568.300228                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22814.158714                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26754.213125                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34838.347556                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30152.407587                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12814.847327                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12823.341783                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13175.707255                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13007.712866                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        34625                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        34625                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17670.111513                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17916.650524                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19092.590897                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18466.110115                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17532.565760                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17435.614432                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18650.504511                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18069.046163                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177760.049423                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 169974.881414                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 170431.707317                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173073.201147                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181340.587595                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171325.088757                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 176473.466167                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 176816.889519                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 179464.390539                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170618.526458                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 173376.766997                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174870.404591                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         15782789                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.974752                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          561471069                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15783301                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.573741                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10320549500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.461580                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     3.134097                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    25.765697                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst    11.613377                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.920823                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.006121                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.050324                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.022682                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        593396461                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       593396461                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    338161196                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    107417239                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     66543293                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst     49349341                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      561471069                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    338161196                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    107417239                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     66543293                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst     49349341                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       561471069                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    338161196                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    107417239                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     66543293                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst     49349341                       # number of overall hits
system.cpu0.icache.overall_hits::total      561471069                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5523274                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1705507                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      3878392                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst      5034836                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     16142009                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5523274                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1705507                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      3878392                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst      5034836                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      16142009                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5523274                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1705507                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      3878392                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst      5034836                       # number of overall misses
system.cpu0.icache.overall_misses::total     16142009                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22950704500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52180116500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  65837786856                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 140968607856                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  22950704500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  52180116500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst  65837786856                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 140968607856                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  22950704500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  52180116500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst  65837786856                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 140968607856                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    343684470                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    109122746                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     70421685                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst     54384177                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    577613078                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    343684470                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    109122746                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     70421685                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst     54384177                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    577613078                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    343684470                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    109122746                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     70421685                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst     54384177                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    577613078                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016071                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015629                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055074                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.092579                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027946                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016071                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015629                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055074                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.092579                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027946                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016071                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015629                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055074                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.092579                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027946                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13456.822224                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13454.059440                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13076.451121                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8733.027460                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13456.822224                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13454.059440                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13076.451121                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8733.027460                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13456.822224                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13454.059440                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13076.451121                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8733.027460                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        36241                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             2942                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.318491                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358626                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       358626                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst       358626                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       358626                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst       358626                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       358626                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1705507                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3878392                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4676210                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10260109                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1705507                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      3878392                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst      4676210                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10260109                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1705507                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      3878392                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst      4676210                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10260109                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21245197500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48301724500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58313017880                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 127859939880                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21245197500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48301724500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58313017880                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 127859939880                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21245197500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48301724500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58313017880                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 127859939880                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015629                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055074                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.085985                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017763                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015629                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055074                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.085985                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.017763                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015629                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055074                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.085985                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.017763                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12456.822224                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12454.059440                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.145242                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12461.850052                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12456.822224                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12454.059440                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.145242                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12461.850052                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12456.822224                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12454.059440                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.145242                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12461.850052                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    31718                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                31718                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4562                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23271                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        31713                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          31713    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        31713                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        27838                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23890.419570                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 20799.818642                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 12686.242290                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        18271     65.63%     65.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9416     33.82%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303           93      0.33%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071           40      0.14%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607            7      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        27838                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1656807784                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.386410                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.486926                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1016600500     61.36%     61.36% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1      640207284     38.64%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1656807784                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        23271     83.61%     83.61% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         4562     16.39%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        27833                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31718                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31718                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27833                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27833                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        59551                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    20370755                       # DTB read hits
system.cpu1.dtb.read_misses                     24112                       # DTB read misses
system.cpu1.dtb.write_hits                   18527997                       # DTB write hits
system.cpu1.dtb.write_misses                     7606                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1180                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               5411                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    128                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   17894                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   972                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2622                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                20394867                       # DTB read accesses
system.cpu1.dtb.write_accesses               18535603                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         38898752                       # DTB hits
system.cpu1.dtb.misses                          31718                       # DTB misses
system.cpu1.dtb.accesses                     38930470                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    20303                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                20303                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          913                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        18082                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        20303                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          20303    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        20303                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        18995                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26989.076073                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24368.047797                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 13392.289816                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        10117     53.26%     53.26% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         8707     45.84%     99.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303           60      0.32%     99.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071           90      0.47%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839            2      0.01%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607            6      0.03%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375            3      0.02%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143            6      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        18995                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000001500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000001500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000001500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        18082     95.19%     95.19% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          913      4.81%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        18995                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20303                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20303                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18995                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18995                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        39298                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   109122746                       # ITB inst hits
system.cpu1.itb.inst_misses                     20303                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1180                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               5411                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    128                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   13373                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               109143049                       # ITB inst accesses
system.cpu1.itb.hits                        109122746                       # DTB hits
system.cpu1.itb.misses                          20303                       # DTB misses
system.cpu1.itb.accesses                    109143049                       # DTB accesses
system.cpu1.numCycles                      1180099858                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  109047622                       # Number of instructions committed
system.cpu1.committedOps                    127894194                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            117464270                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                113646                       # Number of float alu accesses
system.cpu1.num_func_calls                    6418056                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     16543747                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   117464270                       # number of integer instructions
system.cpu1.num_fp_insts                       113646                       # number of float instructions
system.cpu1.num_int_register_reads          169880190                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          93121428                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              186254                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              89372                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            28297680                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           28206937                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     38895648                       # number of memory refs
system.cpu1.num_load_insts                   20369525                       # Number of load instructions
system.cpu1.num_store_insts                  18526123                       # Number of store instructions
system.cpu1.num_idle_cycles              1154177022.629432                       # Number of idle cycles
system.cpu1.num_busy_cycles              25922835.370568                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.021967                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.978033                       # Percentage of idle cycles
system.cpu1.Branches                         24335155                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 88791781     69.39%     69.39% # Class of executed instruction
system.cpu1.op_class::IntMult                  259621      0.20%     69.59% # Class of executed instruction
system.cpu1.op_class::IntDiv                    10323      0.01%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             11904      0.01%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.61% # Class of executed instruction
system.cpu1.op_class::MemRead                20369525     15.92%     85.52% # Class of executed instruction
system.cpu1.op_class::MemWrite               18526123     14.48%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 127969318                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               40525945                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         28226804                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          1998617                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            29685490                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               21101641                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            71.084025                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                4984455                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            337609                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    94850                       # Table walker walks requested
system.cpu2.dtb.walker.walksLong                94850                       # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7112                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        30265                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        94850                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          94850    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        94850                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples        37377                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 24334.778072                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 21415.303868                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 12070.350338                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767        24490     65.52%     65.52% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535        12692     33.96%     99.48% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-98303          111      0.30%     99.78% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::98304-131071           62      0.17%     99.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839            2      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607            6      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::294912-327679            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total        37377                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000229500                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000229500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000229500                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K        30265     80.97%     80.97% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M         7112     19.03%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total        37377                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        94850                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        94850                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        37377                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        37377                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total       132227                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    28616458                       # DTB read hits
system.cpu2.dtb.read_misses                     79197                       # DTB read misses
system.cpu2.dtb.write_hits                   25171351                       # DTB write hits
system.cpu2.dtb.write_misses                    15653                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1181                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid               6998                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    187                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   22525                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                       82                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  2323                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                     3900                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                28695655                       # DTB read accesses
system.cpu2.dtb.write_accesses               25187004                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         53787809                       # DTB hits
system.cpu2.dtb.misses                          94850                       # DTB misses
system.cpu2.dtb.accesses                     53882659                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                    27487                       # Table walker walks requested
system.cpu2.itb.walker.walksLong                27487                       # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1835                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22882                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples        27487                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0          27487    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total        27487                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples        24717                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 27209.107092                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 24621.462305                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 12743.919659                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767        12896     52.17%     52.17% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535        11567     46.80%     98.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303           97      0.39%     99.36% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071          138      0.56%     99.92% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839            3      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607            7      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total        24717                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000203500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000203500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000203500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K        22882     92.58%     92.58% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M         1835      7.42%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total        24717                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27487                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27487                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24717                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24717                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total        52204                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    70482542                       # ITB inst hits
system.cpu2.itb.inst_misses                     27487                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1181                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid               6998                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    187                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   17121                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                    57866                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                70510029                       # ITB inst accesses
system.cpu2.itb.hits                         70482542                       # DTB hits
system.cpu2.itb.misses                          27487                       # DTB misses
system.cpu2.itb.accesses                     70510029                       # DTB accesses
system.cpu2.numCycles                      6664328122                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                  147830191                       # Number of instructions committed
system.cpu2.committedOps                    173473680                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                     14792725                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                     1537                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                 95888456497                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             45.080968                       # CPI: cycles per instruction
system.cpu2.ipc                              0.022182                       # IPC: instructions per cycle
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                      277268742                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     6387059380                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               75157877                       # Number of BP lookups
system.cpu3.branchPred.condPredicted         50856390                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect          3416721                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups            51465907                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits               36468064                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            70.858683                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                9896161                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect            105828                       # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                   516175                       # Table walker walks requested
system.cpu3.dtb.walker.walksLong               516175                       # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8289                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49802                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore       319657                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples       196518                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean  2097.090343                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 12006.037085                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535       195408     99.44%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071          810      0.41%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607          191      0.10%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143           57      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679           27      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215           12      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751           11      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total       196518                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples       233052                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 21512.128195                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 17601.941392                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 14913.346295                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535       228911     98.22%     98.22% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3858      1.66%     99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607          119      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143          117      0.05%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215           13      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total       233052                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -26470108720                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean     0.558973                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -27011428720    102.05%    102.05% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7    297974000     -1.13%    100.92% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11    102453500     -0.39%    100.53% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15     64308500     -0.24%    100.29% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19     26659500     -0.10%    100.19% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23     13977000     -0.05%    100.14% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27     12432000     -0.05%    100.09% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31     20278500     -0.08%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35      3004000     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39       171500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43        49500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47        10000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51         2000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -26470108720                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K        49802     85.73%     85.73% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M         8289     14.27%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total        58091                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       516175                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       516175                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        58091                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        58091                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total       574266                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                    59190068                       # DTB read hits
system.cpu3.dtb.read_misses                    354265                       # DTB read misses
system.cpu3.dtb.write_hits                   46339519                       # DTB write hits
system.cpu3.dtb.write_misses                   161910                       # DTB write misses
system.cpu3.dtb.flush_tlb                        1179                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid              11674                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                    299                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                   28883                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                       57                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                  5029                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                    29040                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                59544333                       # DTB read accesses
system.cpu3.dtb.write_accesses               46501429                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                        105529587                       # DTB hits
system.cpu3.dtb.misses                         516175                       # DTB misses
system.cpu3.dtb.accesses                    106045762                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                    59515                       # Table walker walks requested
system.cpu3.itb.walker.walksLong                59515                       # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1820                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40428                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore         8158                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples        51357                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1446.696653                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev  8669.763957                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767        50895     99.10%     99.10% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535          295      0.57%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303           94      0.18%     99.86% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071           42      0.08%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839           10      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607            7      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375            4      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::294912-327679            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total        51357                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples        50406                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 27093.679324                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 23240.458219                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 16758.841159                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-32767        28504     56.55%     56.55% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-65535        21034     41.73%     98.28% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-98303          420      0.83%     99.11% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::98304-131071          332      0.66%     99.77% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-163839           37      0.07%     99.84% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::163840-196607           32      0.06%     99.91% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-229375           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-294911            9      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total        50406                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -26472605720                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     1.148605                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0     3969304628    -14.99%    -14.99% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1   -30473405348    115.11%    100.12% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2       28081500     -0.11%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3        3146000     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4         137000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5         114000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6           8000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::7           8500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -26472605720                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K        40428     95.69%     95.69% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M         1820      4.31%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total        42248                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        59515                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total        59515                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42248                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42248                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total       101763                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                    54520119                       # ITB inst hits
system.cpu3.itb.inst_misses                     59515                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                        1179                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid              11674                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                    299                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                   21966                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                   118601                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                54579634                       # ITB inst accesses
system.cpu3.itb.hits                         54520119                       # DTB hits
system.cpu3.itb.misses                          59515                       # DTB misses
system.cpu3.itb.accesses                     54579634                       # DTB accesses
system.cpu3.numCycles                       361365292                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles         141188803                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                     334212277                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   75157877                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches          46364225                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                    199187397                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                7734395                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                   1397358                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                6420                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles             2372                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles      3033071                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        90584                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles         3440                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                 54384224                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes              2106741                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                  23723                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples         348776447                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.121764                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.363245                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0               266236191     76.33%     76.33% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                10517145      3.02%     79.35% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                10460372      3.00%     82.35% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 7763584      2.23%     84.57% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                15658447      4.49%     89.06% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                 5090746      1.46%     90.52% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 5553519      1.59%     92.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                 4863826      1.39%     93.51% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                22632617      6.49%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total           348776447                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.207983                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.924860                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles               115165884                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles            162148875                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                 61184358                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles              7206821                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles               3068716                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved            11212761                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred               810030                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts             365054891                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts              2491895                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles               3068716                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles               119377384                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles               12649358                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles     130577518                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                 64081160                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles             19020412                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts             356185546                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                41963                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents               1038308                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                801382                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents               8908900                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents            2068                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands          339701413                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            543048215                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups       420838737                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups           489590                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps            283499579                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                56201829                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts           7935014                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts       6800551                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                 39752644                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads            57621684                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores           48771091                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          7646320                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         8098105                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                 338209447                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded            7991300                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                336799958                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued           493625                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined       46981873                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     30279381                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved        194982                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples    348776447                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.965661                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.679402                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0          218198931     62.56%     62.56% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1           53432546     15.32%     77.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2           24862182      7.13%     85.01% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3           17747115      5.09%     90.10% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4           13068769      3.75%     93.85% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5            9162782      2.63%     96.47% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6            6242831      1.79%     98.26% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7            3634597      1.04%     99.30% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8            2426694      0.70%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total      348776447                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                1722255     26.20%     26.20% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                 16072      0.24%     26.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                   1128      0.02%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               1      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead               2609788     39.70%     66.16% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite              2224178     33.84%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                1      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu            228441301     67.83%     67.83% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult              866625      0.26%     68.08% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                39602      0.01%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.10% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc         39134      0.01%     68.11% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.11% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.11% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.11% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead            60438362     17.94%     86.05% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite           46974933     13.95%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total             336799958                       # Type of FU issued
system.cpu3.iq.rate                          0.932021                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                    6573422                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.019517                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads        1028800637                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes        393256983                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses    324790914                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads             642773                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes            320221                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses       286838                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses             343029301                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                 344078                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads         2684495                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      9539540                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses        13050                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation       400702                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores      5115949                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads      2114056                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked      3866933                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles               3068716                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                8569768                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles              3216654                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts          346278716                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts          1046515                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts             57621684                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts            48771091                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts           6645619                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                129030                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents              3038668                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents        400702                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect       1583590                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect      1353598                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts             2937188                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts            332817802                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts             59181929                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts          3473252                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        77969                       # number of nop insts executed
system.cpu3.iew.exec_refs                   105520536                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                61786884                       # Number of branches executed
system.cpu3.iew.exec_stores                  46338607                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.921001                       # Inst execution rate
system.cpu3.iew.wb_sent                     325791778                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                    325077752                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                160558315                       # num instructions producing a value
system.cpu3.iew.wb_consumers                278246243                       # num instructions consuming a value
system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate                      0.899582                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.577037                       # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts       47005398                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls        7796318                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts          2618044                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples    340807461                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.877970                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.872285                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0    232401746     68.19%     68.19% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1     52180181     15.31%     83.50% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2     19062195      5.59%     89.10% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      8578726      2.52%     91.61% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4      6304961      1.85%     93.46% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5      3698650      1.09%     94.55% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6      3483571      1.02%     95.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7      2215848      0.65%     96.22% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8     12881583      3.78%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total    340807461                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts           254571933                       # Number of instructions committed
system.cpu3.commit.committedOps             299218869                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      91737285                       # Number of memory references committed
system.cpu3.commit.loads                     48082143                       # Number of loads committed
system.cpu3.commit.membars                    2101761                       # Number of memory barriers committed
system.cpu3.commit.branches                  56830426                       # Number of branches committed
system.cpu3.commit.fp_insts                    274837                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                275203911                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             7606631                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu       206755279     69.10%     69.10% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult         663617      0.22%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv           29152      0.01%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc        33536      0.01%     69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead       48082143     16.07%     85.41% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite      43655142     14.59%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total        299218869                       # Class of committed instruction
system.cpu3.commit.bw_lim_events             12881583                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                   672002413                       # The number of ROB reads
system.cpu3.rob.rob_writes                  700430084                       # The number of ROB writes
system.cpu3.timesIdled                        2364277                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                       12588845                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                 98652153144                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                  254571933                       # Number of Instructions Simulated
system.cpu3.committedOps                    299218869                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.419502                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.419502                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.704473                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.704473                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads               392353216                       # number of integer regfile reads
system.cpu3.int_regfile_writes              232744708                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                   564242                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                  330472                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                 70058550                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                70773135                       # number of cc regfile writes
system.cpu3.misc_regfile_reads              654632577                       # number of misc regfile reads
system.cpu3.misc_regfile_writes               7821457                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40271                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40271                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230964                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230964                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353620                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334288                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334288                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492080                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             14862000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 5000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                4000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            10428000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy               45000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            18725000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           246351678                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            45146000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            48770000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115464                       # number of replacements
system.iocache.tags.tagsinuse               10.421022                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115480                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13087689851509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.547375                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.873647                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221711                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429603                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651314                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039695                       # Number of tag accesses
system.iocache.tags.data_accesses             1039695                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8818                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8855                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8818                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8858                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8818                       # number of overall misses
system.iocache.overall_misses::total             8858                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     66023672                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     66023672                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   5601261006                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5601261006                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     66023672                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     66023672                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     66023672                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     66023672                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8818                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8855                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8818                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8858                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8818                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8858                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide  7487.374915                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total  7456.089441                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52513.134760                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 52513.134760                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide  7487.374915                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total  7453.564236                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide  7487.374915                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total  7453.564236                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           432                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   47                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.191489                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          493                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          493                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        47400                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        47400                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          493                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          493                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          493                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          493                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     41373672                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     41373672                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3231261006                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3231261006                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide     41373672                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     41373672                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide     41373672                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     41373672                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.055908                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.055675                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.444386                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.444386                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.055908                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.055656                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.055908                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.055656                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83922.255578                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 83922.255578                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68170.063418                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68170.063418                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 83922.255578                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 83922.255578                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 83922.255578                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 83922.255578                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1178201                       # number of replacements
system.l2c.tags.tagsinuse                65342.536635                       # Cycle average of tags in use
system.l2c.tags.total_refs                   47533778                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1240935                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    38.304809                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36457.259516                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   134.391742                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   206.626869                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3141.459987                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    10234.454405                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    42.556098                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    61.614862                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      851.307108                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2279.755035                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    36.540857                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker    56.575168                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1930.782572                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     2582.079000                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    98.957647                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker   152.820118                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     2413.377960                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     4661.977691                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.556294                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002051                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003153                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.047935                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.156165                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000649                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000940                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.012990                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.034786                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000558                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000863                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.029461                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.039399                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001510                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker     0.002332                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.036825                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.071136                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997048                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          348                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62386                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          346                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          559                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2832                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5180                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53698                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005310                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.951935                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                421030068                       # Number of tag accesses
system.l2c.tags.data_accesses               421030068                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       160105                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       111071                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        55142                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        41666                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       153356                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        57206                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker       292962                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker       104864                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 976372                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         7548701                       # number of Writeback hits
system.l2c.Writeback_hits::total              7548701                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            3766                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1252                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            1641                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data            2803                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9462                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           634186                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           200968                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           288741                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data           458130                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1582025                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       5488344                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       1694582                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst       3854361                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst       4648089                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15685376                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      2558848                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       765070                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data      1053468                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data      1902951                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6280337                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       284863                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data        96754                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data       124346                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data       225674                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           731637                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        160105                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        111071                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             5488344                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3193034                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         55142                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         41666                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1694582                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              966038                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        153356                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         57206                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             3854361                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             1342209                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker        292962                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker        104864                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst             4648089                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data             2361081                       # number of demand (read+write) hits
system.l2c.demand_hits::total                24524110                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       160105                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       111071                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            5488344                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3193034                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        55142                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        41666                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1694582                       # number of overall hits
system.l2c.overall_hits::cpu1.data             966038                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       153356                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        57206                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            3854361                       # number of overall hits
system.l2c.overall_hits::cpu2.data            1342209                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker       292962                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker       104864                       # number of overall hits
system.l2c.overall_hits::cpu3.inst            4648089                       # number of overall hits
system.l2c.overall_hits::cpu3.data            2361081                       # number of overall hits
system.l2c.overall_hits::total               24524110                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1302                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1407                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          317                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker          303                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker          507                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker          452                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker         1016                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker          958                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6262                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         13735                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4483                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          5785                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data         10296                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             34299                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         182889                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          49078                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          67882                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data         112079                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             411928                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        34930                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10925                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst        24031                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst        28031                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           97917                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       117851                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        29685                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        38310                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data        75808                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         261654                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       382135                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        17981                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data        28569                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data        64895                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         493580                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1302                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1407                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             34930                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            300740                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          317                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          303                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10925                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             78763                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker          507                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker          452                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             24031                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data            106192                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker         1016                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker          958                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst             28031                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data            187887                       # number of demand (read+write) misses
system.l2c.demand_misses::total                777761                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1302                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1407                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            34930                       # number of overall misses
system.l2c.overall_misses::cpu0.data           300740                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          317                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          303                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10925                       # number of overall misses
system.l2c.overall_misses::cpu1.data            78763                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker          507                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker          452                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            24031                       # number of overall misses
system.l2c.overall_misses::cpu2.data           106192                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker         1016                       # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker          958                       # number of overall misses
system.l2c.overall_misses::cpu3.inst            28031                       # number of overall misses
system.l2c.overall_misses::cpu3.data           187887                       # number of overall misses
system.l2c.overall_misses::total               777761                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     27522500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker     26481000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     43212000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker     38388000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker     88884500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker     86213000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      310701000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     68441500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data     90805000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data    164582000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    323828500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        81000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   3953928500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   5507688000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data  10998115500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  20459732000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    888341500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst   1996189000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2389519000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   5274049500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   2457700500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   3192549500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data   6788552500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  12438802500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data   1429563000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data   2523386500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data   6994477500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  10947427000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     27522500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     26481000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    888341500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6411629000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker     43212000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker     38388000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   1996189000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   8700237500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker     88884500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker     86213000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst   2389519000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data  17786668000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     38483285000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     27522500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     26481000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    888341500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6411629000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker     43212000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker     38388000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   1996189000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   8700237500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker     88884500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker     86213000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst   2389519000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data  17786668000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    38483285000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       161407                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       112478                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        55459                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        41969                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       153863                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        57658                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker       293978                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker       105822                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             982634                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      7548701                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          7548701                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        17501                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5735                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         7426                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data        13099                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           43761                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       817075                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       250046                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       356623                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data       570209                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1993953                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      5523274                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1705507                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst      3878392                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst      4676120                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15783293                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      2676699                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       794755                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data      1091778                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data      1978759                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6541991                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       666998                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       114735                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data       152915                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data       290569                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1225217                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       161407                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       112478                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         5523274                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         3493774                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        55459                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        41969                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1705507                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1044801                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       153863                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        57658                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         3878392                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         1448401                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker       293978                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker       105822                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst         4676120                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data         2548968                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            25301871                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       161407                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       112478                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        5523274                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        3493774                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        55459                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        41969                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1705507                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1044801                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       153863                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        57658                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        3878392                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        1448401                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker       293978                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker       105822                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst        4676120                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data        2548968                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           25301871                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008067                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012509                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005716                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007220                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003295                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.007839                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003456                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.009053                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006373                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784812                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781691                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.779020                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.786014                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.783780                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.223834                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.196276                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.190347                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.196558                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.206589                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006324                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006406                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006196                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005994                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.006204                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.044028                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.037351                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035090                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.038311                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.039996                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.572918                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.156718                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data     0.186829                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data     0.223338                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.402851                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008067                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012509                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006324                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.086079                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005716                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.007220                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.006406                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.075386                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003295                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.007839                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.006196                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.073317                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003456                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker     0.009053                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.005994                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.073711                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.030739                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008067                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012509                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006324                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.086079                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005716                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.007220                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.006406                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.075386                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003295                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.007839                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.006196                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.073317                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003456                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker     0.009053                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.005994                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.073711                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.030739                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86821.766562                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87396.039604                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85230.769231                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 84929.203540                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87484.744094                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 89992.693111                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 49616.895561                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15266.897167                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15696.629213                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15985.042735                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  9441.339398                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        40500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        40500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80564.173357                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81136.206947                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98128.244363                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 49668.223573                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81312.723112                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83067.246473                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85245.585245                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 53862.449830                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82792.673067                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83334.625424                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 89549.288993                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 47539.126098                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79504.087648                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88326.035213                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107781.454658                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 22179.640585                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86821.766562                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87396.039604                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81312.723112                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81404.072978                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85230.769231                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 84929.203540                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 83067.246473                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 81929.312001                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87484.744094                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 89992.693111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 85245.585245                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 94666.836982                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 49479.576631                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86821.766562                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87396.039604                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81312.723112                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81404.072978                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85230.769231                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 84929.203540                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 83067.246473                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 81929.312001                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87484.744094                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 89992.693111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 85245.585245                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 94666.836982                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 49479.576631                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              982136                       # number of writebacks
system.l2c.writebacks::total                   982136                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           15                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker            4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker           15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 25                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker            4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker           15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                25                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          317                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          303                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          507                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          452                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1012                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          943                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            3534                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks          457                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total          457                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4483                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         5785                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data        10296                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        20564                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        49078                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        67882                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data       112079                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        229039                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10925                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        24031                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        28030                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        62986                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        29685                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        38307                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data        75806                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       143798                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        17981                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data        28569                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data        64895                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       111445                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          317                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          303                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10925                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        78763                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker          507                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker          452                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        24031                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data       106189                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker         1012                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker          943                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst        28030                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data       187885                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           439357                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          317                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          303                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10925                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        78763                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker          507                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker          452                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        24031                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data       106189                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker         1012                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker          943                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst        28030                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data       187885                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          439357                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6070                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         4638                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         5330                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        16038                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         5514                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4225                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         5069                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        14808                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        11584                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data         8863                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        10399                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        30846                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     24352500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     23451000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     38142000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     33868000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker     78456500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker     75654000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    273924000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     92604000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    120054000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    213635500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    426293500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        91500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        91500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3463148500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4828868000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data   9877325500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  18169342000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    779091500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   1755879000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   2109208500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   4644179000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2160850500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   2809328500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data   6030368000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  11000547000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   1249753000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   2237696500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   6345527500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total   9832977000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     24352500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     23451000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    779091500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5623999000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     38142000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     33868000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   1755879000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   7638196500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     78456500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     75654000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst   2109208500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data  15907693500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  34087992000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     24352500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     23451000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    779091500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5623999000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     38142000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     33868000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   1755879000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   7638196500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     78456500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     75654000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst   2109208500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data  15907693500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  34087992000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1003128500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    730361500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    841776000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   2575266000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    936501000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    675184500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data    836243500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2447929000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1939629500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   1405546000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   1678019500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5023195000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.005716                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007220                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003295                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.007839                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003442                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008911                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.003596                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781691                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.779020                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.786014                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.469916                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.196276                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.190347                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.196558                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.114867                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006406                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006196                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005994                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003991                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.037351                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035087                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.038310                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021981                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.156718                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.186829                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.223338                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.090959                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005716                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007220                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006406                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.075386                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003295                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.007839                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006196                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.073315                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003442                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008911                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005994                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.073710                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.017365                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005716                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007220                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006406                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.075386                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003295                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.007839                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006196                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.073315                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003442                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008911                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005994                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.073710                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.017365                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77511.035654                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20656.703101                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20752.636128                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.368687                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20730.086559                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        45750                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        45750                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70564.173357                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71136.206947                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88128.244363                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 79328.594693                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71312.723112                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73067.246473                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75248.251873                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73733.512209                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72792.673067                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73337.209909                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79550.009234                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total        76500                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69504.087648                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78326.035213                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97781.454658                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88231.656871                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71312.723112                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71404.072978                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73067.246473                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71930.204635                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75248.251873                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84667.182053                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 77586.090582                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71312.723112                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71404.072978                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73067.246473                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71930.204635                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75248.251873                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84667.182053                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 77586.090582                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165260.049423                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157473.372143                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 157931.707317                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160572.764684                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169840.587595                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159806.982249                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 164972.085224                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165311.250675                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 167440.391920                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158585.806160                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 161363.544572                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 162847.532905                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76737                       # Transaction distribution
system.membus.trans_dist::ReadResp             451400                       # Transaction distribution
system.membus.trans_dist::WriteReq              33647                       # Transaction distribution
system.membus.trans_dist::WriteResp             33647                       # Transaction distribution
system.membus.trans_dist::Writeback           1088767                       # Transaction distribution
system.membus.trans_dist::CleanEvict           205338                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34966                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           34968                       # Transaction distribution
system.membus.trans_dist::ReadExReq            904844                       # Transaction distribution
system.membus.trans_dist::ReadExResp           904844                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        374663                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           62                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6756                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3881435                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4010829                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       345611                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       345611                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4356440                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    144353760                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    144523174                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7363392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7363392                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               151886566                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              711                       # Total snoops (count)
system.membus.snoop_fanout::samples           2826104                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2826104    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2826104                       # Request fanout histogram
system.membus.reqLayer0.occupancy            51928000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                2000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1759000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          3236688724                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2999492092                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           84543932                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            1501925                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          23827607                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33647                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33647                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          8029950                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict        18099474                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           43761                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          43765                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1993953                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1993953                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15783383                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6542484                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1272617                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1225217                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47433804                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29504905                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       816519                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1737039                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              79492267                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1010303252                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1029626962                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2926248                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6100712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2048957174                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1001590                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         53371149                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.039891                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.195703                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               51242120     96.01%     96.01% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                2129029      3.99%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           53371149                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        20695529987                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           462000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       15394171442                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        7879772837                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         290523250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         715846054                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------