path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.316276                       # Number of seconds simulated
sim_ticks                                51316275690000                       # Number of ticks simulated
final_tick                               51316275690000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 326587                       # Simulator instruction rate (inst/s)
host_op_rate                                   383768                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            19561029283                       # Simulator tick rate (ticks/s)
host_mem_usage                                 692584                       # Number of bytes of host memory used
host_seconds                                  2623.39                       # Real time elapsed on the host
sim_insts                                   856765339                       # Number of instructions simulated
sim_ops                                    1006773904                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker        86272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        86656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2383476                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         19569480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        22528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        19008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           645440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5197376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker        31936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker        29376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          1640192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          6901376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker        81152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker        66816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst          1624448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data         11589312                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        437504                       # Number of bytes read from this memory
system.physmem.bytes_read::total             50412348                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2383476                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       645440                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      1640192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst      1624448                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6293556                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     70023744                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          70044324                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1348                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1354                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             77649                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            305786                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          352                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             10085                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             81209                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker          499                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker          459                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             25628                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            107834                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker         1268                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker         1044                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst             25382                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data            181083                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6836                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                828113                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1094121                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1096694                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1681                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1689                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               46447                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              381350                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker           370                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               12578                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              101281                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           622                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker           572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               31962                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              134487                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1581                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker          1302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst               31656                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data              225841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8526                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  982385                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          46447                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          12578                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          31962                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst          31656                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             122642                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1364552                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1364953                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1364552                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1681                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1689                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              46447                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             381751                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker          370                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              12578                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             101281                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          622                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker          572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              31962                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             134487                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1581                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker         1302                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst              31656                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data             225841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8526                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2347339                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        435200                       # Number of read requests accepted
system.physmem.writeReqs                       483804                       # Number of write requests accepted
system.physmem.readBursts                      435200                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     483804                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 27836736                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     16064                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  30961600                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  27852800                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               30963456                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      251                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               27905                       # Per bank write bursts
system.physmem.perBankRdBursts::1               28763                       # Per bank write bursts
system.physmem.perBankRdBursts::2               27094                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24985                       # Per bank write bursts
system.physmem.perBankRdBursts::4               26681                       # Per bank write bursts
system.physmem.perBankRdBursts::5               30728                       # Per bank write bursts
system.physmem.perBankRdBursts::6               26238                       # Per bank write bursts
system.physmem.perBankRdBursts::7               28208                       # Per bank write bursts
system.physmem.perBankRdBursts::8               24817                       # Per bank write bursts
system.physmem.perBankRdBursts::9               29447                       # Per bank write bursts
system.physmem.perBankRdBursts::10              28003                       # Per bank write bursts
system.physmem.perBankRdBursts::11              29718                       # Per bank write bursts
system.physmem.perBankRdBursts::12              26417                       # Per bank write bursts
system.physmem.perBankRdBursts::13              26875                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23221                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25849                       # Per bank write bursts
system.physmem.perBankWrBursts::0               29439                       # Per bank write bursts
system.physmem.perBankWrBursts::1               30169                       # Per bank write bursts
system.physmem.perBankWrBursts::2               29222                       # Per bank write bursts
system.physmem.perBankWrBursts::3               30308                       # Per bank write bursts
system.physmem.perBankWrBursts::4               30582                       # Per bank write bursts
system.physmem.perBankWrBursts::5               32929                       # Per bank write bursts
system.physmem.perBankWrBursts::6               29622                       # Per bank write bursts
system.physmem.perBankWrBursts::7               32397                       # Per bank write bursts
system.physmem.perBankWrBursts::8               29255                       # Per bank write bursts
system.physmem.perBankWrBursts::9               32999                       # Per bank write bursts
system.physmem.perBankWrBursts::10              30308                       # Per bank write bursts
system.physmem.perBankWrBursts::11              31541                       # Per bank write bursts
system.physmem.perBankWrBursts::12              29215                       # Per bank write bursts
system.physmem.perBankWrBursts::13              29346                       # Per bank write bursts
system.physmem.perBankWrBursts::14              27349                       # Per bank write bursts
system.physmem.perBankWrBursts::15              29094                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
system.physmem.totGap                    51315275469000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  435200                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 483804                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    339047                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     67972                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     19489                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8325                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       556                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       555                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    10688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    12645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    21314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    23642                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    26112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    26953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    27836                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    28305                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    29478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    29464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    30830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    31587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    29857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    29451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    30076                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    27393                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    27014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    26345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       59                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       275230                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      213.631363                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     134.345796                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     252.466079                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         131747     47.87%     47.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        72284     26.26%     74.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        24873      9.04%     83.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        12745      4.63%     87.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         8355      3.04%     90.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         4904      1.78%     92.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4003      1.45%     94.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2900      1.05%     95.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        13419      4.88%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         275230                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         25971                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        16.744908                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       10.064212                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-7              4094     15.76%     15.76% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8-15             5177     19.93%     35.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16-23           12484     48.07%     83.77% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24-31            2573      9.91%     93.67% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-39             911      3.51%     97.18% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40-47             410      1.58%     98.76% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::48-55             151      0.58%     99.34% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::56-63              87      0.33%     99.68% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-71              41      0.16%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::72-79              17      0.07%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::80-87              14      0.05%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::88-95               7      0.03%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-103              1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::136-143             2      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::144-151             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::208-215             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           25971                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         25971                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.627508                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.774611                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        9.820731                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7                27      0.10%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15               58      0.22%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           24184     93.12%     93.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31             657      2.53%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             512      1.97%     97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             109      0.42%     98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55              61      0.23%     98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63              50      0.19%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             187      0.72%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79              29      0.11%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87              13      0.05%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               6      0.02%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              4      0.02%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            13      0.05%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             7      0.03%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             7      0.03%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            17      0.07%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             7      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151             5      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             4      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             2      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             3      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::312-319             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           25971                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8284996307                       # Total ticks spent queuing
system.physmem.totMemAccLat               16440290057                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2174745000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19048.20                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37798.20                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.54                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.60                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.54                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.60                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.48                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317706                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    325786                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.04                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  67.34                       # Row buffer hit rate for writes
system.physmem.avgGap                     55837923.96                       # Average gap between requests
system.physmem.pageHitRate                      70.04                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1063034280                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  578527125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1720625400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               1585448640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1176100438995                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29681595659250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34175675653290                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.640087                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   48913549174000                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1693779100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    116961174250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1017704520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  553591500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1671906600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               1549413360                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1173827506995                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29683698941250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34175350983825                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.631365                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   48916914851742                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1693779100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    113597968758                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                    90923                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong                90923                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples        90923                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          90923    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        90923                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.489265                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -194140819580    -48.93%    -48.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1   590942018000    148.93%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        66800     85.03%     85.03% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11762     14.97%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        78562                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90923                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90923                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78562                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78562                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       169485                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    64271568                       # DTB read hits
system.cpu0.dtb.read_misses                     68949                       # DTB read misses
system.cpu0.dtb.write_hits                   58335276                       # DTB write hits
system.cpu0.dtb.write_misses                    21974                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1189                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   41721                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2805                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     7542                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                64340517                       # DTB read accesses
system.cpu0.dtb.write_accesses               58357250                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        122606844                       # DTB hits
system.cpu0.dtb.misses                          90923                       # DTB misses
system.cpu0.dtb.accesses                    122697767                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    54169                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                54169                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        54169                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          54169    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        54169                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.489353                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -194175666580    -48.94%    -48.94% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   590976865000    148.94%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        47334     95.01%     95.01% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2486      4.99%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        49820                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        54169                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        54169                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49820                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49820                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       103989                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   341484641                       # ITB inst hits
system.cpu0.itb.inst_misses                     54169                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1189                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   29832                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               341538810                       # ITB inst accesses
system.cpu0.itb.hits                        341484641                       # DTB hits
system.cpu0.itb.misses                          54169                       # DTB misses
system.cpu0.itb.accesses                    341538810                       # DTB accesses
system.cpu0.numPwrStateTransitions              12198                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         6099                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    8210231821.367437                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   209893503926.618408                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         2601     42.65%     42.65% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         3474     56.96%     99.61% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            5      0.08%     99.69% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            4      0.07%     99.77% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.03%     99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.02%     99.82% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11            1      0.02%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows            9      0.15%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7947193321500                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           6099                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   1242071811480                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074203878520                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       412415124                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16566                       # number of quiesce instructions executed
system.cpu0.committedInsts                  341336485                       # Number of instructions committed
system.cpu0.committedOps                    401580232                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            368861574                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                359512                       # Number of float alu accesses
system.cpu0.num_func_calls                   20525784                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     51873404                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   368861574                       # number of integer instructions
system.cpu0.num_fp_insts                       359512                       # number of float instructions
system.cpu0.num_int_register_reads          539079221                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         292860354                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              571011                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             323488                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            89499549                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           89284497                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    122681510                       # number of memory refs
system.cpu0.num_load_insts                   64329809                       # Number of load instructions
system.cpu0.num_store_insts                  58351701                       # Number of store instructions
system.cpu0.num_idle_cycles              402393876.753300                       # Number of idle cycles
system.cpu0.num_busy_cycles              10021247.246700                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.024299                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.975701                       # Percentage of idle cycles
system.cpu0.Branches                         76154036                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                278201506     69.24%     69.24% # Class of executed instruction
system.cpu0.op_class::IntMult                  848038      0.21%     69.45% # Class of executed instruction
system.cpu0.op_class::IntDiv                    41846      0.01%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             48432      0.01%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
system.cpu0.op_class::MemRead                64329809     16.01%     85.48% # Class of executed instruction
system.cpu0.op_class::MemWrite               58351701     14.52%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 401821333                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          9787095                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999716                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          296232659                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9787607                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.266097                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.142011                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.386995                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.164772                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data     6.305937                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969027                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.008568                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010087                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.012316                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1255111411                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1255111411                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     60046999                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     19454301                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     26463320                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data     46623681                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      152588301                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     55195720                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     17791665                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     23636838                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data     39052226                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     135676449                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       163106                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47592                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        79678                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112887                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       403263                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       128728                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data        43000                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data        56036                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data       102004                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       329768                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1435392                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       439802                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       587328                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       976810                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3439332                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1527210                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       478716                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       634274                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1126445                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3766645                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    115371447                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     37288966                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     50156194                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     85777911                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       288594518                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    115534553                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     37336558                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     50235872                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     85890798                       # number of overall hits
system.cpu0.dcache.overall_hits::total      288997781                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2061230                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       642663                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       875897                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data      3581810                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7161600                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       820986                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       258023                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       651148                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      3449880                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      5180037                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       513166                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       142485                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       214232                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data       325164                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1195047                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       655346                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       113890                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data       151535                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data       307504                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1228275                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        92447                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        39128                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        47209                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       183438                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       362222                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3537562                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1014576                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1678580                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      7339194                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      13569912                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4050728                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1157061                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1892812                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      7664358                       # number of overall misses
system.cpu0.dcache.overall_misses::total     14764959                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9992794500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13884394000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  52878438500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  76755627000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6954335000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17889776000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96530515223                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 121374626223                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   1854766500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   2567644000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   5803246814                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  10225657314                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    554773000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    665492500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2279898500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3500164000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       188500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       188500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  18801896000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  34341814000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 155212200537                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 208355910537                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  18801896000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  34341814000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 155212200537                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 208355910537                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     62108229                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     20096964                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     27339217                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data     50205491                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    159749901                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     56016706                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     18049688                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     24287986                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data     42502106                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    140856486                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       676272                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       190077                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       293910                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       438051                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1598310                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       784074                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       156890                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       207571                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       409508                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1558043                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1527839                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       478930                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       634537                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1160248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3801554                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1527210                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       478716                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       634274                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1126452                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3766652                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    118909009                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     38303542                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     51834774                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     93117105                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    302164430                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    119585281                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     38493619                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     52128684                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     93555156                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    303762740                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033188                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031978                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.032038                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071343                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.044830                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014656                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014295                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.026809                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.081170                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.036775                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758816                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.749617                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.728903                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.742297                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747694                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.835822                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.725923                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.730039                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.750911                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788345                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060508                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081699                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.074399                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.158102                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095283                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000006                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029750                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026488                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.032383                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.078817                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.044909                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.033873                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.030059                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.036310                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.081923                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.048607                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15549.042811                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15851.628673                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14763.049548                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10717.664628                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26952.384090                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27474.208628                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27980.832731                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23431.227658                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16285.595750                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16944.230706                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18872.101872                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total  8325.218143                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14178.414435                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14096.729437                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12428.714334                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9663.035376                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 26928.571429                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26928.571429                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18531.776821                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20458.848551                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21148.398658                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15354.256574                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16249.701615                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18143.277832                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20251.167878                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14111.512977                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      9947101                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets         9301                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           883316                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            261                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    11.261090                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    35.636015                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      7580739                       # number of writebacks
system.cpu0.dcache.writebacks::total          7580739                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2342                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        38832                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1981448                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2022622                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data           31                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       288487                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2860546                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3149064                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           16                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2230                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         2246                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8708                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10679                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       112790                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       132177                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         2373                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       327335                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      4844224                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      5173932                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         2373                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       327335                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      4844224                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      5173932                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       640321                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       837065                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1600362                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3077748                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       257992                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       362661                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       589334                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1209987                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       142485                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       214116                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       320624                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       677225                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       113890                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       151519                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       305274                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       570683                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30420                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        36530                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        70648                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137598                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      1012203                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      1351245                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data      2494970                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4858418                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1154688                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      1565361                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data      2815594                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      5535643                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5039                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4577                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4597                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14213                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4567                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4089                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4315                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        12971                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         9606                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8666                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         8912                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        27184                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9316912500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12310511500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  24145682500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45773106500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6694367500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9409306500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17283283287                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33386957287                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2351295000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3106665500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   4848120000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10306080500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   1740876500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   2415825500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   5418758314                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total   9575460314                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    393499000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    471106000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    934011000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1798616000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       181500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       181500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  17752156500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  24135643500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  46847724101                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  88735524101                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  20103451500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  27242309000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  51695844101                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  99041604601                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    916274500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    823963000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    848646500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2588884000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    916274500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    823963000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data    848646500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2588884000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031862                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030618                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031876                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019266                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014293                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014932                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.013866                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008590                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.749617                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.728509                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.731933                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.423713                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725923                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.729962                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.745465                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.366282                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063517                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.057570                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060890                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036195                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000006                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026426                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.026068                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.026794                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.016079                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029997                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030029                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.030096                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.018224                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14550.377857                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14706.756942                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15087.637984                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14872.272356                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25947.965441                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25945.184346                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29326.804982                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27592.823135                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16502.052848                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14509.263670                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15120.889266                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.104027                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15285.595750                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15944.043321                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17750.474374                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16778.947882                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12935.535832                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12896.413906                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13220.629034                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13071.527202                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 25928.571429                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25928.571429                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17538.138595                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17861.781912                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18776.868700                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18264.283580                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17410.288753                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17403.211783                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18360.546336                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17891.617035                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181836.574717                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180022.503823                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184608.766587                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182149.018504                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95385.644389                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 95079.967690                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95225.145871                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95235.579753                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements         15900081                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.975051                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          560800301                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15900593                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.269144                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       9932119500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.881688                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     2.899404                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    30.014484                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.179475                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.921644                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.005663                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.058622                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.014022                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        592967136                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       592967136                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    336023230                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    108879045                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     66719955                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst     49178071                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      560800301                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    336023230                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    108879045                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     66719955                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst     49178071                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       560800301                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    336023230                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    108879045                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     66719955                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst     49178071                       # number of overall hits
system.cpu0.icache.overall_hits::total      560800301                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5511231                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1701578                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      3909511                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst      5143815                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     16266135                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5511231                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1701578                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      3909511                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst      5143815                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      16266135                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5511231                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1701578                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      3909511                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst      5143815                       # number of overall misses
system.cpu0.icache.overall_misses::total     16266135                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22882569500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52754697500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  67452926346                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 143090193346                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  22882569500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  52754697500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst  67452926346                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 143090193346                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  22882569500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  52754697500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst  67452926346                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 143090193346                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    341534461                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    110580623                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     70629466                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst     54321886                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    577066436                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    341534461                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    110580623                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     70629466                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst     54321886                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    577066436                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    341534461                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    110580623                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     70629466                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst     54321886                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    577066436                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016137                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015388                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055352                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.094691                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.028188                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016137                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015388                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055352                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.094691                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.028188                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016137                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015388                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055352                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.094691                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.028188                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13447.852229                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.937605                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13113.404418                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8796.815798                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8796.815798                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8796.815798                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        37904                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             3068                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.354628                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     15900081                       # number of writebacks
system.cpu0.icache.writebacks::total         15900081                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       365435                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       365435                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst       365435                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       365435                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst       365435                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       365435                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1701578                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3909511                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4778380                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10389469                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1701578                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      3909511                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst      4778380                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10389469                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1701578                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      3909511                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst      4778380                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10389469                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21180991500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48845186500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59808862373                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 129835040373                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21180991500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48845186500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59808862373                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 129835040373                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21180991500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48845186500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59808862373                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 129835040373                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.018004                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.018004                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.018004                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12496.792702                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                    31190                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                31190                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4602                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        22894                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        31188                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0          31188    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        31188                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        27498                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23439.468325                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 20168.956165                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13617.892423                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        27307     99.31%     99.31% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          167      0.61%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           10      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143            9      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        27498                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   2364440120                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.573010                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.494641                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1009591500     42.70%     42.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1354848620     57.30%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   2364440120                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        22894     83.26%     83.26% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         4602     16.74%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        27496                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31190                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31190                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27496                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27496                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        58686                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    20771010                       # DTB read hits
system.cpu1.dtb.read_misses                     23692                       # DTB read misses
system.cpu1.dtb.write_hits                   18692480                       # DTB write hits
system.cpu1.dtb.write_misses                     7498                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   17937                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1005                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2603                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                20794702                       # DTB read accesses
system.cpu1.dtb.write_accesses               18699978                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         39463490                       # DTB hits
system.cpu1.dtb.misses                          31190                       # DTB misses
system.cpu1.dtb.accesses                     39494680                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    19592                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                19592                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          942                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17338                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        19592                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          19592    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        19592                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        18280                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 26364.633479                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23452.518551                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 14371.838603                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        10663     58.33%     58.33% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535         7451     40.76%     99.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303           65      0.36%     99.45% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071           75      0.41%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839            1      0.01%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           10      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375            1      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143            7      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        18280                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        17338     94.85%     94.85% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          942      5.15%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        18280                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        19592                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        19592                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18280                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18280                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        37872                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   110580623                       # ITB inst hits
system.cpu1.itb.inst_misses                     19592                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   13235                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               110600215                       # ITB inst accesses
system.cpu1.itb.hits                        110580623                       # DTB hits
system.cpu1.itb.misses                          19592                       # DTB misses
system.cpu1.itb.accesses                    110600215                       # DTB accesses
system.cpu1.numPwrStateTransitions               6016                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         3008                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    4046290699.440825                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   205659188461.921204                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows          915     30.42%     30.42% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         2090     69.48%     99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.03%     99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.97% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows            1      0.03%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11261531014001                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           3008                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   39145033266082                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171242423918                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                      1182100228                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  110507936                       # Number of instructions committed
system.cpu1.committedOps                    129543713                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            119008832                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                107333                       # Number of float alu accesses
system.cpu1.num_func_calls                    6516685                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     16787846                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   119008832                       # number of integer instructions
system.cpu1.num_fp_insts                       107333                       # number of float instructions
system.cpu1.num_int_register_reads          172055074                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          94356642                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              176403                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              83340                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            28608279                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           28519816                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     39460487                       # number of memory refs
system.cpu1.num_load_insts                   20769710                       # Number of load instructions
system.cpu1.num_store_insts                  18690777                       # Number of store instructions
system.cpu1.num_idle_cycles              1155308161.927193                       # Number of idle cycles
system.cpu1.num_busy_cycles              26792066.072807                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.022665                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.977335                       # Percentage of idle cycles
system.cpu1.Branches                         24662743                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 89857347     69.33%     69.33% # Class of executed instruction
system.cpu1.op_class::IntMult                  277190      0.21%     69.54% # Class of executed instruction
system.cpu1.op_class::IntDiv                    11015      0.01%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             10320      0.01%     69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
system.cpu1.op_class::MemRead                20769710     16.02%     85.58% # Class of executed instruction
system.cpu1.op_class::MemWrite               18690777     14.42%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 129616400                       # Class of executed instruction
system.cpu2.branchPred.lookups               40854703                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         28349635                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          2013069                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            29873482                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               20268490                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            67.847765                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                4987413                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            331344                       # Number of incorrect RAS predictions.
system.cpu2.branchPred.indirectLookups        1163100                       # Number of indirect predictor lookups.
system.cpu2.branchPred.indirectHits            806401                       # Number of indirect target hits.
system.cpu2.branchPred.indirectMisses          356699                       # Number of indirect misses.
system.cpu2.branchPredindirectMispredicted       146740                       # Number of mispredicted indirect branches.
system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu2.dtb.walker.walks                    93799                       # Table walker walks requested
system.cpu2.dtb.walker.walksLong                93799                       # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7024                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        30187                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        93799                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          93799    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        93799                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples        37211                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 23608.785037                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 20477.524093                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 12702.189700                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767        25796     69.32%     69.32% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535        11234     30.19%     99.51% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-98303           97      0.26%     99.77% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::98304-131071           57      0.15%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607           11      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::294912-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total        37211                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000359000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000359000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000359000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K        30187     81.12%     81.12% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M         7024     18.88%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total        37211                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93799                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93799                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        37211                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        37211                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total       131010                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    28529245                       # DTB read hits
system.cpu2.dtb.read_misses                     78357                       # DTB read misses
system.cpu2.dtb.write_hits                   25227275                       # DTB write hits
system.cpu2.dtb.write_misses                    15442                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1183                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   22552                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                       83                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  2182                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                     3958                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                28607602                       # DTB read accesses
system.cpu2.dtb.write_accesses               25242717                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         53756520                       # DTB hits
system.cpu2.dtb.misses                          93799                       # DTB misses
system.cpu2.dtb.accesses                     53850319                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu2.itb.walker.walks                    27208                       # Table walker walks requested
system.cpu2.itb.walker.walksLong                27208                       # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1843                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22528                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples        27208                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0          27208    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total        27208                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples        24371                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 26858.233146                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 23932.181675                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 13621.050617                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767        13667     56.08%     56.08% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535        10461     42.92%     99.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303           87      0.36%     99.36% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071          133      0.55%     99.91% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839            3      0.01%     99.92% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607           12      0.05%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total        24371                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000327000                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000327000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000327000                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K        22528     92.44%     92.44% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M         1843      7.56%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total        24371                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27208                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27208                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24371                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24371                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total        51579                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    70683304                       # ITB inst hits
system.cpu2.itb.inst_misses                     27208                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1183                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   16893                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                    51118                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                70710512                       # ITB inst accesses
system.cpu2.itb.hits                         70683304                       # DTB hits
system.cpu2.itb.misses                          27208                       # DTB misses
system.cpu2.itb.accesses                     70710512                       # DTB accesses
system.cpu2.numPwrStateTransitions               7024                       # Number of power state transitions
system.cpu2.pwrStateClkGateDist::samples         3512                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::mean    14368150694.236048                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::stdev   129350965742.418961                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::underflows         1152     32.80%     32.80% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1000-5e+10         2323     66.14%     98.95% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::5e+10-1e+11            6      0.17%     99.12% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11            3      0.09%     99.20% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11            2      0.06%     99.26% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11            2      0.06%     99.32% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11            2      0.06%     99.37% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11            1      0.03%     99.40% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.43% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11            1      0.03%     99.46% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11            1      0.03%     99.49% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::overflows           18      0.51%    100.00% # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::max_value 1988791978000                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateClkGateDist::total           3512                       # Distribution of time spent in the clock gated state
system.cpu2.pwrStateResidencyTicks::ON   855330451843                       # Cumulative time (in ticks) in various power states
system.cpu2.pwrStateResidencyTicks::CLK_GATED 50460945238157                       # Cumulative time (in ticks) in various power states
system.cpu2.numCycles                      1176516719                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                  147979887                       # Number of instructions committed
system.cpu2.committedOps                    173747082                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                     15034502                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                     1577                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                     5675627                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                              7.950518                       # CPI: cycles per instruction
system.cpu2.ipc                              0.125778                       # IPC: instructions per cycle
system.cpu2.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
system.cpu2.op_class_0::IntAlu              120575025     69.40%     69.40% # Class of committed instruction
system.cpu2.op_class_0::IntMult                357276      0.21%     69.60% # Class of committed instruction
system.cpu2.op_class_0::IntDiv                  14709      0.01%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatAdd                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatCmp                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatCvt                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatMult                   0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatDiv                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::FloatSqrt                   0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdAdd                     0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdAlu                     0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdCmp                     0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdCvt                     0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdMisc                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdMult                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdShift                   0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdSqrt                    0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     69.61% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMisc           16361      0.01%     69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMult               0      0.00%     69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     69.62% # Class of committed instruction
system.cpu2.op_class_0::MemRead              27648708     15.91%     85.53% # Class of committed instruction
system.cpu2.op_class_0::MemWrite             25135003     14.47%    100.00% # Class of committed instruction
system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
system.cpu2.op_class_0::total               173747082                       # Class of committed instruction
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                      278731731                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                      897784988                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               76144884                       # Number of BP lookups
system.cpu3.branchPred.condPredicted         50917651                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect          3425676                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups            51078726                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits               34631446                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            67.800137                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                9824308                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect            106925                       # Number of incorrect RAS predictions.
system.cpu3.branchPred.indirectLookups        2992006                       # Number of indirect predictor lookups.
system.cpu3.branchPred.indirectHits           1537953                       # Number of indirect target hits.
system.cpu3.branchPred.indirectMisses         1454053                       # Number of indirect misses.
system.cpu3.branchPredindirectMispredicted       245625                       # Number of mispredicted indirect branches.
system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu3.dtb.walker.walks                   512874                       # Table walker walks requested
system.cpu3.dtb.walker.walksLong               512874                       # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8606                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        51328                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore       316923                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples       195951                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean  2195.235033                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 13338.016362                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535       194716     99.37%     99.37% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071          870      0.44%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607          208      0.11%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143           62      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679           47      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215           18      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751           23      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total       195951                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples       235338                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 21271.290654                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 17097.378529                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 15945.708212                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-32767       189296     80.44%     80.44% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-65535        41383     17.58%     98.02% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-98303         3580      1.52%     99.54% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::98304-131071          595      0.25%     99.79% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-163839          139      0.06%     99.85% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::163840-196607          148      0.06%     99.92% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-229375           80      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::229376-262143           73      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-294911           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-360447            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::360448-393215           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total       235338                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -21468826588                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean     0.564464                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -22023506588    102.58%    102.58% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7    315278500     -1.47%    101.12% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11    105205000     -0.49%    100.63% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15     64047000     -0.30%    100.33% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19     24089000     -0.11%    100.21% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23     11371500     -0.05%    100.16% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27     12408500     -0.06%    100.10% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31     18570000     -0.09%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35      3540000     -0.02%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39       163500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43         7000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -21468826588                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K        51328     85.64%     85.64% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M         8606     14.36%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total        59934                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       512874                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       512874                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59934                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59934                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total       572808                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                    59857088                       # DTB read hits
system.cpu3.dtb.read_misses                    352696                       # DTB read misses
system.cpu3.dtb.write_hits                   46573459                       # DTB write hits
system.cpu3.dtb.write_misses                   160178                       # DTB write misses
system.cpu3.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                   29518                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                       76                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                  5036                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                    30761                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                60209784                       # DTB read accesses
system.cpu3.dtb.write_accesses               46733637                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                        106430547                       # DTB hits
system.cpu3.dtb.misses                         512874                       # DTB misses
system.cpu3.dtb.accesses                    106943421                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.cpu3.itb.walker.walks                    59319                       # Table walker walks requested
system.cpu3.itb.walker.walksLong                59319                       # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2009                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40532                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore         8154                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples        51165                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1195.836998                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev  7646.415303                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767        50755     99.20%     99.20% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535          251      0.49%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303           94      0.18%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071           39      0.08%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839           13      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607            9      0.02%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total        51165                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples        50695                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 26787.010553                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 22469.536393                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 17840.810022                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-32767        30103     59.38%     59.38% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-65535        19510     38.49%     97.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-98303          511      1.01%     98.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::98304-131071          427      0.84%     99.72% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-163839           38      0.07%     99.79% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::163840-196607           57      0.11%     99.90% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-229375           19      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-294911            8      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total        50695                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -25766386884                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     0.899092                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev     0.296211                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0    -2567658104      9.97%      9.97% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1   -23226705280     90.14%    100.11% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2       24531500     -0.10%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3        2936500     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4         267500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5          75500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6         120000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::7          45500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -25766386884                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K        40532     95.28%     95.28% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M         2009      4.72%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total        42541                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        59319                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total        59319                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42541                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42541                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total       101860                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                    54449151                       # ITB inst hits
system.cpu3.itb.inst_misses                     59319                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                   22325                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                   110276                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                54508470                       # ITB inst accesses
system.cpu3.itb.hits                         54449151                       # DTB hits
system.cpu3.itb.misses                          59319                       # DTB misses
system.cpu3.itb.accesses                     54508470                       # DTB accesses
system.cpu3.numPwrStateTransitions               7056                       # Number of power state transitions
system.cpu3.pwrStateClkGateDist::samples         3528                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::mean    48263626.625000                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::stdev   1100096495.861649                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::underflows         2141     60.69%     60.69% # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::1000-5e+10         1387     39.31%    100.00% # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::max_value  36012902604                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateClkGateDist::total           3528                       # Distribution of time spent in the clock gated state
system.cpu3.pwrStateResidencyTicks::ON   51146001615267                       # Cumulative time (in ticks) in various power states
system.cpu3.pwrStateResidencyTicks::CLK_GATED 170274074733                       # Cumulative time (in ticks) in various power states
system.cpu3.numCycles                       360624311                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles         142734409                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                     337961407                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   76144884                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches          45993707                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                    196711593                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                7739189                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                   1372744                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                5006                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles             1830                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles      2692575                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        88196                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles         3852                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                 54321925                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes              2128480                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                  22518                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples         347479672                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.136573                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.381700                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0               264664577     76.17%     76.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                10448751      3.01%     79.17% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                10389657      2.99%     82.16% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 7726776      2.22%     84.39% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                15569597      4.48%     88.87% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                 5085732      1.46%     90.33% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 5566487      1.60%     91.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                 4803146      1.38%     93.32% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                23224949      6.68%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total           347479672                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.211147                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.937156                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles               116319092                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles            159338087                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                 61493208                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles              7257195                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles               3070348                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved            11216097                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred               810528                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts             368877230                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts              2502393                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles               3070348                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles               120537316                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles               11607372                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles     129961960                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                 64445904                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles             17854957                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts             360009684                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                40582                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents                995330                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                792465                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents               7726817                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents            2104                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands          342963420                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            547080576                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups       423978365                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups           517857                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps            286215822                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                56747593                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts           7972839                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts       6835897                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                 39855447                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads            58319848                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores           48888042                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          7618365                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         8042184                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                 341704043                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded            8022599                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                340232336                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued           497337                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined       47823760                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     30164946                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved        192380                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples    347479672                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.979143                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.691890                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0          216057167     62.18%     62.18% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1           53646928     15.44%     77.62% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2           24868918      7.16%     84.77% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3           17968855      5.17%     89.95% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4           13078366      3.76%     93.71% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5            9279622      2.67%     96.38% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6            6367435      1.83%     98.21% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7            3674225      1.06%     99.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8            2538156      0.73%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total      347479672                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                1739394     26.12%     26.12% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                 17216      0.26%     26.38% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                   1075      0.02%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.40% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead               2643113     39.69%     66.09% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite              2258125     33.91%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass                5      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu            230928850     67.87%     67.87% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult              888251      0.26%     68.13% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                40201      0.01%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                204      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc         42408      0.01%     68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.16% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead            61160195     17.98%     86.14% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite           47172222     13.86%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total             340232336                       # Type of FU issued
system.cpu3.iq.rate                          0.943454                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                    6658923                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.019572                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads        1034449548                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes        397601121                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses    327921647                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads             651056                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes            333937                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses       289983                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses             346543457                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                 347797                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads         2684612                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      9848030                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses        12099                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation       390855                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores      4852885                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads      2121686                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked      3886704                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles               3070348                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                8044361                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles              2703635                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts          349811697                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts          1019337                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts             58319848                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts            48888042                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts           6684338                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                123262                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents              2534169                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents        390855                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect       1464138                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect      1603865                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts             3068003                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts            336172243                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts             59848506                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts          3553985                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        85055                       # number of nop insts executed
system.cpu3.iew.exec_refs                   106421072                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                62316621                       # Number of branches executed
system.cpu3.iew.exec_stores                  46572566                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.932195                       # Inst execution rate
system.cpu3.iew.wb_sent                     329026261                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                    328211630                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                162144042                       # num instructions producing a value
system.cpu3.iew.wb_consumers                281134898                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      0.910121                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.576748                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts       47849721                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls        7830219                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts          2626302                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples    339381548                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.889568                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.882377                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0    230141242     67.81%     67.81% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1     52578609     15.49%     83.30% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2     18989562      5.60%     88.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      8770494      2.58%     91.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4      6420925      1.89%     93.38% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5      3757747      1.11%     94.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6      3513397      1.04%     95.52% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7      2195731      0.65%     96.17% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8     13013841      3.83%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total    339381548                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts           256941031                       # Number of instructions committed
system.cpu3.commit.committedOps             301902877                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      92506974                       # Number of memory references committed
system.cpu3.commit.loads                     48471817                       # Number of loads committed
system.cpu3.commit.membars                    2097304                       # Number of memory barriers committed
system.cpu3.commit.branches                  57364518                       # Number of branches committed
system.cpu3.commit.fp_insts                    278173                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                277550130                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             7627094                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu       208647320     69.11%     69.11% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult         682317      0.23%     69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv           29904      0.01%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc        36362      0.01%     69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.36% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead       48471817     16.06%     85.41% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite      44035157     14.59%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total        301902877                       # Class of committed instruction
system.cpu3.commit.bw_lim_events             13013841                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                   673991782                       # The number of ROB reads
system.cpu3.rob.rob_writes                  707616779                       # The number of ROB writes
system.cpu3.timesIdled                        2425895                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                       13144639                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                 98725614751                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                  256941031                       # Number of Instructions Simulated
system.cpu3.committedOps                    301902877                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.403529                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.403529                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.712489                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.712489                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads               395604640                       # number of integer regfile reads
system.cpu3.int_regfile_writes              235195836                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                   565870                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                  351196                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                 70807437                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                71493240                       # number of cc regfile writes
system.cpu3.misc_regfile_reads              657110629                       # number of misc regfile reads
system.cpu3.misc_regfile_writes               7862543                       # number of misc regfile writes
system.iobus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353622                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492088                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             13499000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                17500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                5000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            10442000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            21712500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           227539905                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            39848000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            45034000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115465                       # number of replacements
system.iocache.tags.tagsinuse               10.425444                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13087293844009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.544651                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.880792                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221541                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.430050                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651590                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039704                       # Number of tag accesses
system.iocache.tags.data_accesses             1039704                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8819                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8856                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115483                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115523                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115483                       # number of overall misses
system.iocache.overall_misses::total           115523                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     61770218                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     61770218                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   5167926687                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5167926687                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   5229696905                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   5229696905                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   5229696905                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   5229696905                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8819                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8856                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115483                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115523                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115483                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115523                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide  7004.220206                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total  6974.956865                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48450.523954                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 48450.523954                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 45269.746328                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 45269.746328                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           417                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   40                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.425000                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          453                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          453                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        43744                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        43744                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide        44197                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        44197                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide        44197                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        44197                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide     39120218                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     39120218                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2977819124                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   2977819124                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   3016939342                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3016939342                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   3016939342                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3016939342                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.051366                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.051152                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.410110                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.410110                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.382582                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.382582                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86358.097130                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 86358.097130                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68073.772952                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68073.772952                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1182494                       # number of replacements
system.l2c.tags.tagsinuse                65447.621193                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49776356                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1245426                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    39.967333                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10450.326675                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.502647                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   222.666592                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3323.622390                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    21949.117178                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    56.686764                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    60.274211                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      949.191230                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     6589.162943                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    69.129700                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker    76.155286                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2308.881020                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     7819.148817                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker   140.556158                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker   161.169200                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     1712.244141                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     9365.786241                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.159459                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002953                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003398                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.050714                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.334917                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000865                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000920                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.014484                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.100543                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001055                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.001162                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.035231                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.119311                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.002145                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker     0.002459                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.026127                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.142911                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.998651                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          384                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62548                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          384                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1131                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5605                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        55378                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.954407                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                420660189                       # Number of tag accesses
system.l2c.tags.data_accesses               420660189                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker       148411                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       102905                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        50987                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        37863                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       145669                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        53387                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker       286140                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker        98751                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 924113                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7580739                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7580739                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     15897541                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        15897541                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data           10116                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            3190                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            4337                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data            7288                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               24931                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 5                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           624653                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           203950                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           287508                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data           472182                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1588293                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       5476670                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       1691493                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst       3883882                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst       4752795                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15804840                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      2544942                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       782243                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data      1049975                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data      1919039                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6296199                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       281232                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data        93381                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data       121660                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data       233276                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           729549                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        148411                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        102905                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             5476670                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3169595                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         50987                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         37863                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1691493                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              986193                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        145669                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         53387                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             3883882                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             1337483                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker        286140                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker         98751                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst             4752795                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data             2391221                       # number of demand (read+write) hits
system.l2c.demand_hits::total                24613445                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       148411                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       102905                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            5476670                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3169595                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        50987                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        37863                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1691493                       # number of overall hits
system.l2c.overall_hits::cpu1.data             986193                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       145669                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        53387                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            3883882                       # number of overall hits
system.l2c.overall_hits::cpu2.data            1337483                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker       286140                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker        98751                       # number of overall hits
system.l2c.overall_hits::cpu3.inst            4752795                       # number of overall hits
system.l2c.overall_hits::cpu3.data            2391221                       # number of overall hits
system.l2c.overall_hits::total               24613445                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1348                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1354                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          352                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker          499                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker          459                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker         1269                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker         1055                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6633                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1519                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           482                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data           628                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data          1231                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3860                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         184700                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          50370                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          70224                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data         111495                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             416789                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        34561                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        10085                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst        25629                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst        25382                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           95657                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       121901                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        30983                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        37700                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data        69735                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         260319                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       374112                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        20509                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data        29859                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data        71998                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         496478                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1348                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1354                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             34561                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            306601                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          352                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          297                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             10085                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             81353                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker          499                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker          459                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             25629                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data            107924                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker         1269                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker         1055                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst             25382                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data            181230                       # number of demand (read+write) misses
system.l2c.demand_misses::total                779398                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1348                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1354                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            34561                       # number of overall misses
system.l2c.overall_misses::cpu0.data           306601                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          352                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          297                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            10085                       # number of overall misses
system.l2c.overall_misses::cpu1.data            81353                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker          499                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker          459                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            25629                       # number of overall misses
system.l2c.overall_misses::cpu2.data           107924                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker         1269                       # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker         1055                       # number of overall misses
system.l2c.overall_misses::cpu3.inst            25382                       # number of overall misses
system.l2c.overall_misses::cpu3.data           181230                       # number of overall misses
system.l2c.overall_misses::total               779398                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     29403500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker     26495000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     43837500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker     40434000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    112747500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker     93804500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      346722000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data      9065500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data     11493000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data     21540500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     42099000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data        86000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        86000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   4112169500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   5777401500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data  11171660500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  21061231500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    833482500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst   2164843000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2195026000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   5193351500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   2618754500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   3195444500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data   6292724500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  12106923500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data        57000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data        59000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data       233000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total       349000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     29403500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     26495000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    833482500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   6730924000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker     43837500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker     40434000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   2164843000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   8972846000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker    112747500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker     93804500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst   2195026000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data  17464385000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     38708228500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     29403500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     26495000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    833482500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   6730924000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker     43837500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker     40434000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   2164843000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   8972846000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker    112747500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker     93804500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst   2195026000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data  17464385000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    38708228500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       149759                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       104259                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        51339                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        38160                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       146168                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        53846                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker       287409                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker        99806                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             930746                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7580739                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7580739                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     15897541                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     15897541                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        11635                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3672                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         4965                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data         8519                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           28791                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       809353                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       254320                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       357732                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data       583677                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2005082                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      5511231                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1701578                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst      3909511                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst      4778177                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15900497                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      2666843                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       813226                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data      1087675                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data      1988774                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6556518                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       655344                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       113890                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data       151519                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data       305274                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1226027                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       149759                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       104259                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         5511231                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         3476196                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        51339                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        38160                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1701578                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1067546                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       146168                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        53846                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         3909511                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         1445407                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker       287409                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker        99806                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst         4778177                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data         2572451                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            25392843                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       149759                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       104259                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        5511231                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        3476196                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        51339                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        38160                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1701578                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1067546                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       146168                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        53846                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        3909511                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        1445407                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker       287409                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker        99806                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst        4778177                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data        2572451                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           25392843                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.007127                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.130554                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.131264                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.126485                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.144501                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.134070                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.228207                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.198058                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.196303                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.191022                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.207866                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006271                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005927                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006556                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005312                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.006016                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045710                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.038099                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.034661                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.035064                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.039704                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.570864                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.180077                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data     0.197064                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data     0.235847                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.404949                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006271                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.088200                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005927                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.076206                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.006556                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.074667                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.005312                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.070450                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.030694                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006271                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.088200                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005927                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.076206                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.006556                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.074667                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.005312                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.070450                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.030694                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52272.274989                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18808.091286                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 18300.955414                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 17498.375305                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 10906.476684                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        43000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        43000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81639.259480                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82271.039815                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 100198.757792                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 50532.119370                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82645.761031                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84468.492723                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 86479.631235                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 54291.390071                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84522.302553                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84759.801061                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90237.678354                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 46508.028611                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     2.779268                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data     1.975954                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data     3.236201                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total     0.702952                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 49664.264599                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 49664.264599                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks              987490                       # number of writebacks
system.l2c.writebacks::total                   987490                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker            1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker            1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          352                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          297                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          499                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          459                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1268                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker         1044                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            3919                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          482                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data          628                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data         1231                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2341                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        50370                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        70224                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data       111495                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        232089                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10085                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        25628                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        25382                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        61095                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        30983                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        37698                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data        69732                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       138413                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        20509                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data        29859                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data        71998                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       122366                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          352                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          297                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        10085                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        81353                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker          499                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker          459                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        25628                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data       107922                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker         1268                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker         1044                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst        25382                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data       181227                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           435516                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          352                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          297                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        10085                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        81353                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker          499                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker          459                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        25628                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data       107922                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker         1268                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker         1044                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst        25382                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data       181227                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          435516                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5039                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         4577                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         4597                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        14213                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4567                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4089                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         4315                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        12971                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data         9606                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data         8666                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data         8912                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        27184                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    306745501                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      9150000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     11919000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     23381500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     44450500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        95500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        95500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3608469500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   5075161500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  10056705012                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  18740336012                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    732632500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   1908425001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   1941197018                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   4582254519                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2308918013                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   2818373501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data   5595188544                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  10722480058                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data    384451000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data    580665000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   1458533500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total   2423649500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    732632500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   5917387513                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   1908425001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   7893535001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst   1941197018                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data  15651893556                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  34351816090                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    732632500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   5917387513                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   1908425001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   7893535001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst   1941197018                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data  15651893556                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  34351816090                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    853214500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    766744000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    791147500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   2411106000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data    853214500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data    766744000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data    791147500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   2411106000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.004211                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.131264                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.126485                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.144501                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.081310                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.198058                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.196303                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.191022                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.115750                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003842                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.038099                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.034659                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.035063                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021111                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.180077                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.197064                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.235847                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.099807                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.017151                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.017151                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 78271.370503                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18983.402490                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18979.299363                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.907392                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18987.825716                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        47750                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        47750                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71639.259480                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72271.039815                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 90198.708570                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 80746.334432                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75002.119961                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74522.093180                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74761.883946                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80238.463604                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77467.290341                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18745.477595                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19446.900432                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20257.972444                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19806.559829                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169322.186942                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167521.083679                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172100.826626                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169640.892141                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88820.997293                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88477.267482                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 88773.283214                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 88695.776928                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       2692221                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1332095                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         2857                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76739                       # Transaction distribution
system.membus.trans_dist::ReadResp             448186                       # Transaction distribution
system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
system.membus.trans_dist::WriteResp             33648                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1094121                       # Transaction distribution
system.membus.trans_dist::CleanEvict           202838                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4443                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1867                       # Transaction distribution
system.membus.trans_dist::ReadExReq            416227                       # Transaction distribution
system.membus.trans_dist::ReadExResp           416227                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        371447                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        603124                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       437026                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6762                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3707227                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3836623                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       302374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       302374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4138997                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13524                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    113227104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    113396466                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7366016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7366016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               120762482                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              546                       # Total snoops (count)
system.membus.snoopTraffic                      34880                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2213347                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.016167                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.126119                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2177563     98.38%     98.38% # Request fanout histogram
system.membus.snoop_fanout::1                   35784      1.62%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2213347                       # Request fanout histogram
system.membus.reqLayer0.occupancy            45757000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1572000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          3230054159                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2350415750                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy            2301227                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     52031861                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     26343539                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         3136                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2272                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2272                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq            1497693                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          23955179                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33648                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33648                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      8020839                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     15900080                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2311396                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           28791                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          28798                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2005082                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2005082                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15900700                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6556911                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1231319                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1226027                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47787527                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29554737                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       797902                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1720271                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              79860437                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2035409428                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1033316830                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2813832                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      5963920                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3077504010                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1542362                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  65849016                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         38107926                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.016628                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.127874                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               37474258     98.34%     98.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 633668      1.66%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           38107926                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        31293825988                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           519265                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       15589080685                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        7944642139                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         286385229                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         714971913                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------