path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.278396                       # Number of seconds simulated
sim_ticks                                51278396244000                       # Number of ticks simulated
final_tick                               51278396244000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 287420                       # Simulator instruction rate (inst/s)
host_op_rate                                   337741                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            17381457033                       # Simulator tick rate (ticks/s)
host_mem_usage                                 688188                       # Number of bytes of host memory used
host_seconds                                  2950.18                       # Real time elapsed on the host
sim_insts                                   847940135                       # Number of instructions simulated
sim_ops                                     996397451                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        80128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        85632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2427380                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         43615880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        26944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        22528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           448704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          6225152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker        27008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker        28160                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          1496000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          7976640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker        59008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker        56384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst          1720000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data         14392384                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        422080                       # Number of bytes read from this memory
system.physmem.bytes_read::total             79110012                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2427380                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       448704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      1496000                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst      1720000                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6092084                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67404672                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67425252                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1252                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1338                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             78335                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            681511                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          421                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          352                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              7011                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             97268                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker          422                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker          440                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             23375                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            124635                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker          922                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker          881                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst             26875                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data            224881                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6595                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1276514                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1053198                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1055771                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1563                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1670                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               47337                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              850570                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           525                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker           439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst                8750                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              121399                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker           549                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               29174                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              155556                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1151                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker          1100                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst               33542                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data              280671                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8231                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1542755                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          47337                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst           8750                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          29174                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst          33542                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             118804                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1314485                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1314886                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1314485                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1563                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1670                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              47337                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             850972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker          439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst               8750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             121399                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker          549                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              29174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             155556                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1151                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker         1100                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst              33542                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data             280671                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8231                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2857641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        511823                       # Number of read requests accepted
system.physmem.writeReqs                       447580                       # Number of write requests accepted
system.physmem.readBursts                      511823                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     447580                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 32737280                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19392                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  28644032                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  32756672                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               28645120                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      303                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               29703                       # Per bank write bursts
system.physmem.perBankRdBursts::1               34345                       # Per bank write bursts
system.physmem.perBankRdBursts::2               31026                       # Per bank write bursts
system.physmem.perBankRdBursts::3               30271                       # Per bank write bursts
system.physmem.perBankRdBursts::4               32199                       # Per bank write bursts
system.physmem.perBankRdBursts::5               37423                       # Per bank write bursts
system.physmem.perBankRdBursts::6               31570                       # Per bank write bursts
system.physmem.perBankRdBursts::7               30956                       # Per bank write bursts
system.physmem.perBankRdBursts::8               30714                       # Per bank write bursts
system.physmem.perBankRdBursts::9               34361                       # Per bank write bursts
system.physmem.perBankRdBursts::10              33202                       # Per bank write bursts
system.physmem.perBankRdBursts::11              32791                       # Per bank write bursts
system.physmem.perBankRdBursts::12              32230                       # Per bank write bursts
system.physmem.perBankRdBursts::13              32440                       # Per bank write bursts
system.physmem.perBankRdBursts::14              29459                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28830                       # Per bank write bursts
system.physmem.perBankWrBursts::0               25970                       # Per bank write bursts
system.physmem.perBankWrBursts::1               28442                       # Per bank write bursts
system.physmem.perBankWrBursts::2               26808                       # Per bank write bursts
system.physmem.perBankWrBursts::3               27272                       # Per bank write bursts
system.physmem.perBankWrBursts::4               29035                       # Per bank write bursts
system.physmem.perBankWrBursts::5               31977                       # Per bank write bursts
system.physmem.perBankWrBursts::6               28169                       # Per bank write bursts
system.physmem.perBankWrBursts::7               28603                       # Per bank write bursts
system.physmem.perBankWrBursts::8               27151                       # Per bank write bursts
system.physmem.perBankWrBursts::9               29537                       # Per bank write bursts
system.physmem.perBankWrBursts::10              28051                       # Per bank write bursts
system.physmem.perBankWrBursts::11              28561                       # Per bank write bursts
system.physmem.perBankWrBursts::12              27796                       # Per bank write bursts
system.physmem.perBankWrBursts::13              28123                       # Per bank write bursts
system.physmem.perBankWrBursts::14              26050                       # Per bank write bursts
system.physmem.perBankWrBursts::15              26018                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          29                       # Number of times write queue was full causing retry
system.physmem.totGap                    51277395805500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  511823                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 447580                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    363555                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     93711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     31585                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     19104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       420                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       374                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       356                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       769                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       457                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       237                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      242                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       87                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       79                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       70                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       66                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       577                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     8731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    19434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    21637                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    24704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    25741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    25599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    25799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    26255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    26532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    27053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    28426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    27490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    27929                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    30961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    26710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    26732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    25592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       71                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       257915                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      237.988981                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     144.092695                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     278.727383                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         118797     46.06%     46.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        64316     24.94%     71.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        23486      9.11%     80.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        11936      4.63%     84.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         8805      3.41%     88.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         5543      2.15%     90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4520      1.75%     92.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3591      1.39%     93.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16921      6.56%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         257915                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         24705                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.705080                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       14.399508                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-63            24532     99.30%     99.30% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-127            158      0.64%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-191             5      0.02%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-255             5      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-319             1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-575             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-703             2      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1088-1151            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           24705                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         24705                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.116292                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.314740                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.551029                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                22      0.09%      0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                13      0.05%      0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               13      0.05%      0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              49      0.20%      0.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           23047     93.29%     93.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             446      1.81%     95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             165      0.67%     96.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             178      0.72%     96.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              51      0.21%     97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              35      0.14%     97.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              69      0.28%     97.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.04%     97.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             185      0.75%     98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              38      0.15%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              14      0.06%     98.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              28      0.11%     98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             125      0.51%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              16      0.06%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              10      0.04%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              68      0.28%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              94      0.38%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             5      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             5      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            10      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           24705                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10604540202                       # Total ticks spent queuing
system.physmem.totMemAccLat               20195540202                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2557600000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20731.43                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39481.43                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.56                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.64                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                     390042                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    311121                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.25                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.51                       # Row buffer hit rate for writes
system.physmem.avgGap                     53447191.44                       # Average gap between requests
system.physmem.pageHitRate                      73.11                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  987139440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  536905875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                2008390800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               1466203680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3310428600960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1177085104875                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           30106909725750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34599422071380                       # Total energy per rank (pJ)
system.physmem_0.averagePower              666.667509                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   48872262134916                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1692448160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    119734785584                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  962629920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  523549125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1981395000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               1433900880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3310428600960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1177786265580                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29667035331750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34160151673215                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.621174                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   48871271616428                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1692448160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    120718837572                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    90127                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong                90127                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples        90127                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          90127    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        90127                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 389002834492                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.524244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -203932266508    -52.42%    -52.42% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1   592935101000    152.42%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 389002834492                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        65772     85.00%     85.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11604     15.00%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        77376                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90127                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90127                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77376                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77376                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       167503                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    64859725                       # DTB read hits
system.cpu0.dtb.read_misses                     68631                       # DTB read misses
system.cpu0.dtb.write_hits                   59094124                       # DTB write hits
system.cpu0.dtb.write_misses                    21496                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1195                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              16177                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    384                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   40401                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2751                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     7419                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                64928356                       # DTB read accesses
system.cpu0.dtb.write_accesses               59115620                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        123953849                       # DTB hits
system.cpu0.dtb.misses                          90127                       # DTB misses
system.cpu0.dtb.accesses                    124043976                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    53226                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                53226                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        53226                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          53226    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        53226                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 389002834492                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.524351                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -203974019508    -52.44%    -52.44% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   592976854000    152.44%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 389002834492                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        46188     94.90%     94.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2484      5.10%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        48672                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53226                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53226                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48672                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48672                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       101898                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   346140401                       # ITB inst hits
system.cpu0.itb.inst_misses                     53226                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1195                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              16177                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    384                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   28414                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               346193627                       # ITB inst accesses
system.cpu0.itb.hits                        346140401                       # DTB hits
system.cpu0.itb.misses                          53226                       # DTB misses
system.cpu0.itb.accesses                    346193627                       # DTB accesses
system.cpu0.numCycles                       417471005                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16511                       # number of quiesce instructions executed
system.cpu0.committedInsts                  345998217                       # Number of instructions committed
system.cpu0.committedOps                    406905705                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            373867604                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                363074                       # Number of float alu accesses
system.cpu0.num_func_calls                   20947482                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     52475381                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   373867604                       # number of integer instructions
system.cpu0.num_fp_insts                       363074                       # number of float instructions
system.cpu0.num_int_register_reads          545388282                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         296679828                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              584270                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             311304                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            89963697                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           89731719                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    124026394                       # number of memory refs
system.cpu0.num_load_insts                   64916857                       # Number of load instructions
system.cpu0.num_store_insts                  59109537                       # Number of store instructions
system.cpu0.num_idle_cycles              408121506.428325                       # Number of idle cycles
system.cpu0.num_busy_cycles              9349498.571675                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.022396                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.977604                       # Percentage of idle cycles
system.cpu0.Branches                         77230042                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                282115014     69.29%     69.29% # Class of executed instruction
system.cpu0.op_class::IntMult                  908017      0.22%     69.51% # Class of executed instruction
system.cpu0.op_class::IntDiv                    41532      0.01%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             48729      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                64916857     15.94%     85.48% # Class of executed instruction
system.cpu0.op_class::MemWrite               59109537     14.52%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 407139686                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          9649816                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          292739937                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9650328                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.334714                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.097568                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.975954                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.503732                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data     4.422464                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972847                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.009719                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.008796                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.008638                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1240452518                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1240452518                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     60697634                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     18777257                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     26142693                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data     44948482                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      150566066                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     55906928                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     17271712                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     23345865                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data     37782358                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     134306863                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       159073                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47007                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        77709                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data       113008                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       396797                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       126017                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data        45823                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data        59716                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data        97286                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       328842                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1444166                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       434424                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       579867                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       933968                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3392425                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1534667                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       472976                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       630117                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1067463                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3705223                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    116604562                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     36048969                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     49488558                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     82730840                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       284872929                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    116763635                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     36095976                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     49566267                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     82843848                       # number of overall hits
system.cpu0.dcache.overall_hits::total      285269726                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2054873                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       645438                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       971207                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data      3440752                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7112270                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       839053                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       258864                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       597119                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      3449762                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      5144798                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       459594                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       152322                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       206104                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data       350750                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1168770                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       686647                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       108408                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data       151049                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data       279871                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1225975                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        91254                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        38759                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        50526                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       171973                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       352512                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2893926                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       904302                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1568326                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      6890514                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      12257068                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3353520                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1056624                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1774430                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      7241264                       # number of overall misses
system.cpu0.dcache.overall_misses::total     13425838                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10693475500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  16789198500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  60054572500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  87537246500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9893449500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22002273500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 116544874640                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 148440597640                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   3721833000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   5259250500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  11075466859                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  20056550359                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    550414500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    751937500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2294222000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3596574000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  20586925000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  38791472000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 176599447140                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 235977844140                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  20586925000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  38791472000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 176599447140                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 235977844140                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     62752507                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     19422695                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     27113900                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data     48389234                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    157678336                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     56745981                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     17530576                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     23942984                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data     41232120                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    139451661                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       618667                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       199329                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       283813                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       463758                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1565567                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       812664                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       154231                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       210765                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       377157                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1554817                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1535420                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       473183                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       630393                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1105941                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3744937                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1534668                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       472976                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       630117                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1067464                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3705225                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    119498488                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     36953271                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     51056884                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     89621354                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    297129997                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    120117155                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     37152600                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     51340697                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     90085112                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    298695564                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032746                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033231                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035820                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071106                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.045106                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014786                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014766                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.024939                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083667                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.036893                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.742878                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.764174                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.726196                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.756321                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.746547                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.844933                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.702894                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.716670                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.742054                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788501                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059433                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081911                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.080150                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.155499                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.094130                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024217                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024472                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030717                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076885                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.041252                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027919                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028440                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034562                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080382                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.044948                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16567.781104                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17286.941404                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17453.909058                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12307.919483                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38218.715233                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36847.384692                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33783.453653                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 28852.560905                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34331.719061                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34818.174897                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39573.470845                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16359.673206                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14200.946877                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14882.189368                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13340.594163                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10202.699483                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        41000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22765.541821                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24734.316717                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25629.357569                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19252.389245                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19483.681045                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21861.370694                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24387.931049                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17576.395912                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     14582944                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        41803                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           883633                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            391                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.503395                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   106.913043                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7469710                       # number of writebacks
system.cpu0.dcache.writebacks::total          7469710                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3285                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       124429                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1909922                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2037636                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4905                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       264011                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2867438                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3136354                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           23                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2121                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         2144                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8176                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10487                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       105681                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       124344                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         8190                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       388440                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      4777360                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      5173990                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         8190                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       388440                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      4777360                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      5173990                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       642153                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       846778                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1530830                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3019761                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       253959                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       333108                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       582324                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1169391                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       151941                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       203469                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       343395                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       698805                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       108408                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       151026                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       277750                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       537184                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30583                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        40039                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        66292                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       136914                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       896112                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      1179886                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data      2113154                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4189152                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1048053                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      1383355                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data      2456549                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4887957                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6903                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6938                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7170                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        21011                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6403                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6456                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6887                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19746                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13306                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        13394                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        14057                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40757                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9834011500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13414476000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26248104500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49496592000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9425671500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  11707052500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21288427290                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  42421151290                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3120110500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4040690000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6773951000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13934751500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3613425000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   5107026000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10670616859                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  19391067859                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    396226000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    532705500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    945307500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1874239000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  19259683000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25121528500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  47536531790                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  91917743290                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  22379793500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29162218500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  54310482790                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 105852494790                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1362861000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1366136000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1368520000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4097517000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1303404500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1305231500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1342048955                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3950684955                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2666265500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2671367500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2710568955                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8048201955                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033062                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031230                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031636                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019151                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014487                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013913                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014123                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008386                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.762262                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.716912                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.740462                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.446359                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.702894                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.716561                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.736431                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.345497                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064632                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.063514                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.059942                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036560                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024250                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023109                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023579                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.014099                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028209                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.026945                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027269                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.016364                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15314.125294                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15841.786159                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17146.322257                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16390.897160                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37114.933907                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35144.915463                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36557.702052                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36276.276532                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20535.013591                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19858.995719                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19726.411276                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19940.829702                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33331.719061                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33815.541695                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38418.062499                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36097.627366                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12955.759736                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13304.665451                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.752308                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13689.169844                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21492.495358                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21291.487906                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22495.535957                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21941.849637                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21353.684880                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21080.791626                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22108.446764                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21655.774548                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197430.247718                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196906.313059                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190867.503487                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195017.705012                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203561.533656                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202173.404585                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 194866.989255                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200075.202826                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200380.692920                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199445.087353                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 192826.986910                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197467.967588                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         15707105                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.971411                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          557754178                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15707617                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.508517                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11785355500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.312770                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     3.251841                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    23.846438                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.560362                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934205                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.006351                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.046575                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012813                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          151                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        589528421                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       589528421                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    340625874                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    105592046                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     63997933                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst     47538325                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      557754178                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    340625874                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    105592046                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     63997933                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst     47538325                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       557754178                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    340625874                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    105592046                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     63997933                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst     47538325                       # number of overall hits
system.cpu0.icache.overall_hits::total      557754178                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5563199                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1667816                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      3866259                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst      4969275                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     16066549                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5563199                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1667816                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      3866259                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst      4969275                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      16066549                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5563199                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1667816                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      3866259                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst      4969275                       # number of overall misses
system.cpu0.icache.overall_misses::total     16066549                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22564855500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  53176348000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  67096069815                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 142837273315                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  22564855500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  53176348000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst  67096069815                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 142837273315                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  22564855500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  53176348000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst  67096069815                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 142837273315                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    346189073                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    107259862                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     67864192                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst     52507600                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    573820727                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    346189073                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    107259862                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     67864192                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst     52507600                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    573820727                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    346189073                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    107259862                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     67864192                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst     52507600                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    573820727                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016070                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015549                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.056971                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.094639                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027999                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016070                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015549                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.056971                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.094639                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027999                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016070                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015549                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.056971                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.094639                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027999                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.583299                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13753.953887                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13502.184889                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8890.351831                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13529.583299                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13753.953887                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13502.184889                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8890.351831                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13529.583299                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13753.953887                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13502.184889                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8890.351831                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        59004                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             3622                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.290447                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     15707105                       # number of writebacks
system.cpu0.icache.writebacks::total         15707105                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       358855                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       358855                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst       358855                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       358855                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst       358855                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       358855                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1667816                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3866259                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4610420                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10144495                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1667816                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      3866259                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst      4610420                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10144495                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1667816                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      3866259                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst      4610420                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10144495                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  20897039500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  49310089000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59222114846                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 129429243346                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  20897039500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  49310089000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59222114846                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 129429243346                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  20897039500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  49310089000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59222114846                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 129429243346                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.056971                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087805                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017679                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.056971                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087805                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.017679                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015549                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.056971                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087805                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.017679                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.583299                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12753.953887                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.275451                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12758.569386                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.583299                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12753.953887                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.275451                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12758.569386                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.583299                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12753.953887                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.275451                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12758.569386                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    31889                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                31889                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4559                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23393                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        31883                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.878211                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev   156.811692                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047        31882    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        31883                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        27958                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25168.842550                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21742.406424                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16076.029843                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        18219     65.17%     65.17% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535         9556     34.18%     99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071            2      0.01%     99.35% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839          143      0.51%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           15      0.05%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375            4      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           12      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            1      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        27958                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1140126012                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.890541                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1015329500    -89.05%    -89.05% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -2155455512    189.05%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1140126012                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        23393     83.69%     83.69% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         4559     16.31%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        27952                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31889                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31889                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        59841                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    20102110                       # DTB read hits
system.cpu1.dtb.read_misses                     24529                       # DTB read misses
system.cpu1.dtb.write_hits                   18166884                       # DTB write hits
system.cpu1.dtb.write_misses                     7360                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               5389                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    137                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   18327                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   952                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2685                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                20126639                       # DTB read accesses
system.cpu1.dtb.write_accesses               18174244                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         38268994                       # DTB hits
system.cpu1.dtb.misses                          31889                       # DTB misses
system.cpu1.dtb.accesses                     38300883                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    20281                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                20281                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          944                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17917                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        20281                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          20281    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        20281                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        18861                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28459.466624                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25212.666818                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18596.263354                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        18677     99.02%     99.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          158      0.84%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143            7      0.04%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           10      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            5      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        18861                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        17917     94.99%     94.99% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          944      5.01%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        18861                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20281                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20281                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18861                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18861                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        39142                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   107259862                       # ITB inst hits
system.cpu1.itb.inst_misses                     20281                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               5389                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    137                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   13712                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               107280143                       # ITB inst accesses
system.cpu1.itb.hits                        107259862                       # DTB hits
system.cpu1.itb.misses                          20281                       # DTB misses
system.cpu1.itb.accesses                    107280143                       # DTB accesses
system.cpu1.numCycles                      1186091604                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  107180280                       # Number of instructions committed
system.cpu1.committedOps                    125798339                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            115609456                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                108829                       # Number of float alu accesses
system.cpu1.num_func_calls                    6343191                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     16252887                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   115609456                       # number of integer instructions
system.cpu1.num_fp_insts                       108829                       # number of float instructions
system.cpu1.num_int_register_reads          167399256                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          91770929                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              176307                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              89468                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            27813306                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27752983                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     38266694                       # number of memory refs
system.cpu1.num_load_insts                   20101554                       # Number of load instructions
system.cpu1.num_store_insts                  18165140                       # Number of store instructions
system.cpu1.num_idle_cycles              1160685667.067715                       # Number of idle cycles
system.cpu1.num_busy_cycles              25405936.932285                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.021420                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.978580                       # Percentage of idle cycles
system.cpu1.Branches                         23816903                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 87315881     69.37%     69.37% # Class of executed instruction
system.cpu1.op_class::IntMult                  273375      0.22%     69.58% # Class of executed instruction
system.cpu1.op_class::IntDiv                    10716      0.01%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             11213      0.01%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.60% # Class of executed instruction
system.cpu1.op_class::MemRead                20101554     15.97%     85.57% # Class of executed instruction
system.cpu1.op_class::MemWrite               18165140     14.43%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 125877921                       # Class of executed instruction
system.cpu2.branchPred.lookups               39521108                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         27394498                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          1977688                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            28624019                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               20176228                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            70.487055                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                4882878                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            320724                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    93699                       # Table walker walks requested
system.cpu2.dtb.walker.walksLong                93699                       # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6670                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        29108                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        93699                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          93699    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        93699                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples        35778                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 25406.269216                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22092.991962                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 16331.424603                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535        35575     99.43%     99.43% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607          169      0.47%     99.90% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143            8      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679           13      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-393215            3      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751            7      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-524287            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::524288-589823            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total        35778                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000224000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000224000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000224000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K        29108     81.36%     81.36% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M         6670     18.64%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total        35778                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93699                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93699                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        35778                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        35778                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total       129477                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    28306173                       # DTB read hits
system.cpu2.dtb.read_misses                     78188                       # DTB read misses
system.cpu2.dtb.write_hits                   24883433                       # DTB write hits
system.cpu2.dtb.write_misses                    15511                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid               6582                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    193                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   22329                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                       81                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  1959                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                     3725                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                28384361                       # DTB read accesses
system.cpu2.dtb.write_accesses               24898944                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         53189606                       # DTB hits
system.cpu2.dtb.misses                          93699                       # DTB misses
system.cpu2.dtb.accesses                     53283305                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                    27049                       # Table walker walks requested
system.cpu2.itb.walker.walksLong                27049                       # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1824                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22699                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples        27049                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0          27049    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total        27049                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples        24523                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 29055.621254                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25956.010792                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 17576.904821                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767        12420     50.65%     50.65% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535        11833     48.25%     98.90% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839          203      0.83%     99.73% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607           48      0.20%     99.92% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911            7      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total        24523                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K        22699     92.56%     92.56% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M         1824      7.44%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total        24523                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27049                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27049                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24523                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24523                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total        51572                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    67920418                       # ITB inst hits
system.cpu2.itb.inst_misses                     27049                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid               6582                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    193                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   16678                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                    53297                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                67947467                       # ITB inst accesses
system.cpu2.itb.hits                         67920418                       # DTB hits
system.cpu2.itb.misses                          27049                       # DTB misses
system.cpu2.itb.accesses                     67947467                       # DTB accesses
system.cpu2.numCycles                      6665733461                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                  145260015                       # Number of instructions committed
system.cpu2.committedOps                    170560320                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                     13528820                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                     1578                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                 95889999557                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             45.888288                       # CPI: cycles per instruction
system.cpu2.ipc                              0.021792                       # IPC: instructions per cycle
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                      269818486                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     6395914975                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               73106744                       # Number of BP lookups
system.cpu3.branchPred.condPredicted         49439775                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect          3283160                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups            49494170                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits               35647247                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            72.023123                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                9537276                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect            105421                       # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                   494727                       # Table walker walks requested
system.cpu3.dtb.walker.walksLong               494727                       # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8139                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49597                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore       307402                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples       187325                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean  2316.431336                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 13967.085425                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535       186132     99.36%     99.36% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071          667      0.36%     99.72% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607          353      0.19%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143           78      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679           59      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751           16      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287            9      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total       187325                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples       229787                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 22726.216017                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18353.180951                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 18914.444967                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535       225128     97.97%     97.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3594      1.56%     99.54% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607          720      0.31%     99.85% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143           65      0.03%     99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679          153      0.07%     99.94% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215           80      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751           33      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total       229787                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -29283845516                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean     0.245317                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -29839367516    101.90%    101.90% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7    306582000     -1.05%    100.85% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11    107118000     -0.37%    100.48% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15     65892000     -0.23%    100.26% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19     24591000     -0.08%    100.18% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23     14226000     -0.05%    100.13% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27     14020500     -0.05%    100.08% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31     18907500     -0.06%    100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35      4030000     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39       146000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43         9000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -29283845516                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K        49597     85.90%     85.90% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M         8139     14.10%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total        57736                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       494727                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       494727                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        57736                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        57736                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total       552463                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                    58246352                       # DTB read hits
system.cpu3.dtb.read_misses                    339748                       # DTB read misses
system.cpu3.dtb.write_hits                   45232753                       # DTB write hits
system.cpu3.dtb.write_misses                   154979                       # DTB write misses
system.cpu3.dtb.flush_tlb                        1185                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid              11213                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                    305                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                   29617                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                       79                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                  4718                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                    32277                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                58586100                       # DTB read accesses
system.cpu3.dtb.write_accesses               45387732                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                        103479105                       # DTB hits
system.cpu3.dtb.misses                         494727                       # DTB misses
system.cpu3.dtb.accesses                    103973832                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                    60127                       # Table walker walks requested
system.cpu3.itb.walker.walksLong                60127                       # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1977                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41370                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore         8202                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples        51925                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1583.187289                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev  9631.832849                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767        51469     99.12%     99.12% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535          278      0.54%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303           39      0.08%     99.73% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071           41      0.08%     99.81% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839           70      0.13%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607           14      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143            4      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911            3      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total        51925                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples        51549                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 29040.146269                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 24568.436348                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 21519.136506                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535        50502     97.97%     97.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071          358      0.69%     98.66% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-196607          600      1.16%     99.83% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-262143           30      0.06%     99.89% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679           32      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215           16      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-458751            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::524288-589823            3      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total        51549                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -29286303016                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     0.896957                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev     0.299007                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0    -2976637360     10.16%     10.16% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1   -26347752656     89.97%    100.13% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2       35165500     -0.12%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3        2840000     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4          71000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5          10500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -29286303016                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K        41370     95.44%     95.44% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M         1977      4.56%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total        43347                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60127                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60127                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43347                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43347                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total       103474                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                    52640414                       # ITB inst hits
system.cpu3.itb.inst_misses                     60127                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                        1185                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid              11213                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                    305                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                   23184                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                   115097                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                52700541                       # ITB inst accesses
system.cpu3.itb.hits                         52640414                       # DTB hits
system.cpu3.itb.misses                          60127                       # DTB misses
system.cpu3.itb.accesses                     52700541                       # DTB accesses
system.cpu3.numCycles                       367415947                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles         138047852                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                     324925438                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   73106744                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches          45184523                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                    206488551                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                7421915                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                   1494390                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                8711                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles             1919                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles      2933513                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        92576                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles         5529                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                 52507671                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes              2023167                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                  24008                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples         352783845                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.078296                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.326372                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0               272678491     77.29%     77.29% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                 9999177      2.83%     80.13% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                10154215      2.88%     83.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 7447502      2.11%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                15397984      4.36%     89.48% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                 5025734      1.42%     90.91% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 5401897      1.53%     92.44% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                 4807386      1.36%     93.80% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                21871459      6.20%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total           352783845                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.198975                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.884353                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles               112906719                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles            170627658                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                 59194480                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles              7143620                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles               2909626                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved            10993587                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred               812434                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts             355125435                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts              2492983                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles               2909626                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles               117007450                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles               13956942                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles     135354583                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                 62147599                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles             21405678                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts             346848000                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                65680                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents               1218522                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                931993                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents              11105485                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents            2097                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands          331495484                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            531299079                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups       409883872                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups           498256                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps            278579121                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                52916358                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts           7952838                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts       6842362                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                 39655118                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads            56090576                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores           47550992                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          7265418                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         7939600                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                 329496362                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded            7936863                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                329269236                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued           468664                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined       44300133                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     28411196                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved        197124                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples    352783845                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.933346                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.659424                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0          224815035     63.73%     63.73% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1           52801661     14.97%     78.69% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2           24147394      6.84%     85.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3           17186087      4.87%     90.41% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4           12829115      3.64%     94.05% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5            9014914      2.56%     96.60% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6            6070700      1.72%     98.32% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7            3552216      1.01%     99.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8            2366723      0.67%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total      352783845                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                1655726     25.42%     25.42% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                 16802      0.26%     25.68% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                   1467      0.02%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.70% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead               2658135     40.82%     66.52% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite              2180482     33.48%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass               27      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu            223168493     67.78%     67.78% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult              780707      0.24%     68.01% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                40175      0.01%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                174      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               1      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc         42531      0.01%     68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead            59412355     18.04%     86.08% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite           45824773     13.92%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total             329269236                       # Type of FU issued
system.cpu3.iq.rate                          0.896176                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                    6512612                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.019779                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads        1017639354                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes        381768294                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses    317351059                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads             664239                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes            330816                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses       296027                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses             335426759                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                 355062                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads         2617033                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      8910571                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses        11930                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation       371819                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores      4873914                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads      2093383                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked      4209996                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles               2909626                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                8686652                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles              4058716                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts          337508586                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts           999497                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts             56090576                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts            47550992                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts           6693033                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                115188                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents              3897473                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents        371819                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect       1479948                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect      1304525                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts             2784473                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts            325518299                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts             58237072                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts          3261982                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        75361                       # number of nop insts executed
system.cpu3.iew.exec_refs                   103468304                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                60421077                       # Number of branches executed
system.cpu3.iew.exec_stores                  45231232                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.885967                       # Inst execution rate
system.cpu3.iew.wb_sent                     318319204                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                    317647086                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                156971025                       # num instructions producing a value
system.cpu3.iew.wb_consumers                272519290                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      0.864544                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.576000                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts       44325764                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls        7739739                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts          2481675                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples    345244332                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.849060                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.846955                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0    238738698     69.15%     69.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1     51567808     14.94%     84.09% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2     18622481      5.39%     89.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      8388535      2.43%     91.91% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4      6065452      1.76%     93.67% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5      3663652      1.06%     94.73% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6      3429214      0.99%     95.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7      2148576      0.62%     96.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8     12619916      3.66%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total    345244332                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts           249501623                       # Number of instructions committed
system.cpu3.commit.committedOps             293133087                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      89857082                       # Number of memory references committed
system.cpu3.commit.loads                     47180004                       # Number of loads committed
system.cpu3.commit.membars                    1961101                       # Number of memory barriers committed
system.cpu3.commit.branches                  55730410                       # Number of branches committed
system.cpu3.commit.fp_insts                    284466                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                269318634                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             7382541                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu       202599565     69.12%     69.12% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult         609386      0.21%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv           30413      0.01%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc        36641      0.01%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.35% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead       47180004     16.10%     85.44% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite      42677078     14.56%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total        293133087                       # Class of committed instruction
system.cpu3.commit.bw_lim_events             12619916                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                   668027626                       # The number of ROB reads
system.cpu3.rob.rob_writes                  682469296                       # The number of ROB writes
system.cpu3.timesIdled                        2366991                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                       14632102                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                 98631076285                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                  249501623                       # Number of Instructions Simulated
system.cpu3.committedOps                    293133087                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.472599                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.472599                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.679071                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.679071                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads               383683244                       # number of integer regfile reads
system.cpu3.int_regfile_writes              227091338                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                   575742                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                  354224                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                 69408942                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                70047711                       # number of cc regfile writes
system.cpu3.misc_regfile_reads              653726404                       # number of misc regfile reads
system.cpu3.misc_regfile_writes               7798013                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40238                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40238                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136511                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136511                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29444                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122464                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353498                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7491974                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             34324500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               218500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                5500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13530000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            21519000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           268744919                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            59904000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            77390000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115459                       # number of replacements
system.iocache.tags.tagsinuse               10.420604                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13089166746509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.547315                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.873289                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221707                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429581                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651288                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide   1097461741                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1097461741                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   6290187178                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6290187178                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   1097461741                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1097461741                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   1097461741                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1097461741                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124527.600250                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124006.976384                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58971.979093                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58971.979093                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124527.600250                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123964.954366                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124527.600250                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123964.954366                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22895                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 2302                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.945699                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide         5727                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         5727                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        50000                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        50000                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide         5727                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         5727                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide         5727                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         5727                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide    811111741                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    811111741                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3787932075                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3787932075                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide    811111741                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    811111741                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide    811111741                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    811111741                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.649835                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.647119                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.468762                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.468762                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.649835                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.646899                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.649835                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.646899                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141629.429195                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 141629.429195                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75758.641500                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75758.641500                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 141629.429195                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 141629.429195                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 141629.429195                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 141629.429195                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1134655                       # number of replacements
system.l2c.tags.tagsinuse                65348.585655                       # Cycle average of tags in use
system.l2c.tags.total_refs                   47218951                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1196839                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    39.453052                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36858.424918                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   139.336234                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   207.961932                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3464.040368                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     8073.434256                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    31.851614                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    46.563538                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      388.442961                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2039.653767                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    38.632115                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker    59.555007                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1814.509325                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3538.387838                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    81.542571                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker   121.893588                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     2682.398731                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     5761.956894                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.562415                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002126                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003173                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052857                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.123191                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000711                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.005927                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.031123                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000589                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000909                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.027687                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.053992                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001244                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker     0.001860                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.040930                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.087920                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997140                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          269                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        61915                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          268                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          568                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2797                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5091                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53356                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004105                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.944748                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                417874191                       # Number of tag accesses
system.l2c.tags.data_accesses               417874191                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       157547                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       107991                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        56540                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        42358                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       150716                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        57617                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker       285535                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker       108659                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 966963                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7469710                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7469710                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     15704683                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        15704683                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            3849                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1299                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            1546                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data            2673                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9367                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           642784                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           197897                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           265419                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data           474003                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1580103                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       5527952                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       1660805                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst       3842883                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst       4583462                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15615102                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      2499377                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       796548                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data      1051090                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data      1860386                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6207401                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       289262                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data        89246                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data       125740                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data       228993                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           733241                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        157547                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        107991                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             5527952                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3142161                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         56540                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         42358                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1660805                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              994445                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        150716                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         57617                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             3842883                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             1316509                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker        285535                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker        108659                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst             4583462                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data             2334389                       # number of demand (read+write) hits
system.l2c.demand_hits::total                24369569                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       157547                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       107991                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            5527952                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3142161                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        56540                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        42358                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1660805                       # number of overall hits
system.l2c.overall_hits::cpu1.data             994445                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       150716                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        57617                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            3842883                       # number of overall hits
system.l2c.overall_hits::cpu2.data            1316509                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker       285535                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker       108659                       # number of overall hits
system.l2c.overall_hits::cpu3.inst            4583462                       # number of overall hits
system.l2c.overall_hits::cpu3.data            2334389                       # number of overall hits
system.l2c.overall_hits::total               24369569                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1252                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1338                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          421                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker          352                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker          422                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker          440                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker          924                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker          892                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6041                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         13973                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4552                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          5817                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data          9421                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             33763                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         178447                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          50211                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          60375                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data          98714                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             387747                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        35247                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         7011                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst        23376                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst        26876                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           92510                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       106344                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        28129                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        39147                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data        77644                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         251264                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       397385                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        19162                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data        25286                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data        48757                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         490590                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1252                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1338                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             35247                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            284791                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          421                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          352                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              7011                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             78340                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker          422                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker          440                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             23376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             99522                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker          924                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker          892                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst             26876                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data            176358                       # number of demand (read+write) misses
system.l2c.demand_misses::total                737562                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1252                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1338                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            35247                       # number of overall misses
system.l2c.overall_misses::cpu0.data           284791                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          421                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          352                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             7011                       # number of overall misses
system.l2c.overall_misses::cpu1.data            78340                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker          422                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker          440                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            23376                       # number of overall misses
system.l2c.overall_misses::cpu2.data            99522                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker          924                       # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker          892                       # number of overall misses
system.l2c.overall_misses::cpu3.inst            26876                       # number of overall misses
system.l2c.overall_misses::cpu3.data           176358                       # number of overall misses
system.l2c.overall_misses::total               737562                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     56414500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker     48383000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     57823500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker     59723000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    126486500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker    121800000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      470630500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    180440500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data    237646000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data    390941500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    809028000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   6592113000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   7946110000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data  14567039000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  29105262000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    923100500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst   3124017500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst   3653424999                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   7700542999                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   3739908000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   5269271500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data  10960372000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  19969551500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data   2513729500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data   3528376000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data   7538845500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  13580951000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     56414500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     48383000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    923100500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  10332021000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker     57823500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker     59723000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   3124017500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data  13215381500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker    126486500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker    121800000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst   3653424999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data  25527411000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     57245986999                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     56414500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     48383000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    923100500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  10332021000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker     57823500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker     59723000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   3124017500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data  13215381500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker    126486500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker    121800000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst   3653424999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data  25527411000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    57245986999                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       158799                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       109329                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        56961                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        42710                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       151138                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        58057                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker       286459                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker       109551                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             973004                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7469710                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7469710                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     15704683                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     15704683                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        17822                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5851                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         7363                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data        12094                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           43130                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       821231                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       248108                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       325794                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data       572717                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1967850                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      5563199                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1667816                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst      3866259                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst      4610338                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15707612                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      2605721                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       824677                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data      1090237                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data      1938030                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6458665                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       686647                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       108408                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data       151026                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data       277750                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1223831                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       158799                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       109329                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         5563199                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         3426952                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        56961                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        42710                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1667816                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1072785                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       151138                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        58057                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         3866259                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         1416031                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker       286459                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker       109551                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst         4610338                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data         2510747                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            25107131                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       158799                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       109329                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        5563199                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        3426952                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        56961                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        42710                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1667816                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1072785                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       151138                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        58057                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        3866259                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        1416031                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker       286459                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker       109551                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst        4610338                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data        2510747                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           25107131                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007884                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012238                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.007391                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.008242                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002792                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.007579                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003226                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008142                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006209                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784031                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.777987                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.790031                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.778981                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782819                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.217292                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.202376                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.185316                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.172361                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.197041                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006336                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004204                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006046                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005830                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005890                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.040812                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034109                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035907                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040063                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.038903                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.578733                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.176758                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data     0.167428                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data     0.175543                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.400864                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007884                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012238                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006336                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.083103                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.007391                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.008242                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.004204                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.073025                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002792                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.007579                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.006046                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.070282                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003226                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker     0.008142                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.005830                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.070241                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.029377                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007884                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012238                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006336                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.083103                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.007391                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.008242                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.004204                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.073025                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002792                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.007579                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.006046                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.070282                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003226                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker     0.008142                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.005830                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.070241                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.029377                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 134001.187648                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137451.704545                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 137022.511848                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 135734.090909                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 136890.151515                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 136547.085202                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 77906.058600                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39639.828647                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 40853.704659                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 41496.815625                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 23961.970204                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131288.223696                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 131612.587992                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147568.115971                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75062.507253                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131664.598488                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133642.090178                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 135936.337215                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 83240.114571                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132955.597426                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 134602.178966                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141161.866983                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 79476.373456                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 131183.044567                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 139538.717077                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 154620.782657                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 27682.894066                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 134001.187648                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137451.704545                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131664.598488                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131886.916007                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 137022.511848                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 135734.090909                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 133642.090178                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 132788.544241                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 136890.151515                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 136547.085202                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 135936.337215                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 144747.678019                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77615.152352                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 134001.187648                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137451.704545                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131664.598488                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131886.916007                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 137022.511848                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 135734.090909                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 133642.090178                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 132788.544241                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 136890.151515                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 136547.085202                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 135936.337215                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 144747.678019                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77615.152352                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              946567                       # number of writebacks
system.l2c.writebacks::total                   946567                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            2                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            7                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker            2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 21                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker            2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                21                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          421                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          352                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          422                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          440                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker          922                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          881                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            3438                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4552                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         5817                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data         9421                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        19790                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        50211                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        60375                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data        98714                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        209300                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         7011                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        23376                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        26875                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        57262                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        28129                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        39142                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data        77642                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       144913                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        19162                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data        25286                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data        48757                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total        93205                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          421                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          352                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         7011                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        78340                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker          422                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker          440                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        23376                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        99517                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker          922                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker          881                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst        26875                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data       176356                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           414913                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          421                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          352                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         7011                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        78340                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker          422                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker          440                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        23376                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        99517                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker          922                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker          881                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst        26875                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data       176356                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          414913                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6903                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6938                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         7170                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        21011                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6403                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         6456                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6887                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        19746                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13306                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data        13394                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        14057                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        40757                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     52204500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     44863000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     53603500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     55323000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker    117076501                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker    111660000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    434730501                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    309280000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    395583000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    640663000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1345526000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   6090003000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   7342359002                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  13579897004                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  27012259006                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    852990500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2890257500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3384647006                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   7127895006                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3458618000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   4877372500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10183719501                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  18519710001                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2322109500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   3275516000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   7051275500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  12648901000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     52204500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     44863000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    852990500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   9548621000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     53603500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     55323000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   2890257500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data  12219731502                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    117076501                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    111660000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst   3384647006                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data  23763616505                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  53094594514                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     52204500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     44863000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    852990500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   9548621000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     53603500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     55323000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   2890257500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data  12219731502                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    117076501                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    111660000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst   3384647006                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data  23763616505                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  53094594514                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1276511500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1279406000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1278862500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3834780000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1229770000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1230900500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1262767998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   3723438498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2506281500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2510306500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2541630498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7558218498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007391                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.008242                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002792                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.007579                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003219                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008042                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.003533                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.777987                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.790031                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.778981                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.458845                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.202376                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.185316                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.172361                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.106360                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004204                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006046                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005829                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003645                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034109                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035902                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.040062                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022437                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.176758                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.167428                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.175543                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.076158                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007391                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.008242                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004204                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.073025                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002792                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.007579                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006046                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.070279                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003219                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008042                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005829                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.070240                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.016526                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007391                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.008242                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004204                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.073025                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002792                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.007579                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006046                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.070279                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003219                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008042                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005829                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.070240                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.016526                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 126448.662304                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67943.760984                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68004.641568                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68003.715105                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67990.197069                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121288.223696                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 121612.571462                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137568.095751                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129060.004806                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121664.598488                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123642.090178                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125940.353712                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124478.624673                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122955.597426                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124607.135558                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131162.508707                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127798.817228                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121183.044567                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129538.717077                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 144620.782657                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135710.541280                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121664.598488                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121886.916007                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123642.090178                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122790.392616                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125940.353712                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134747.989890                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 127965.608487                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121664.598488                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121886.916007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123642.090178                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122790.392616                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125940.353712                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134747.989890                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 127965.608487                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184921.266116                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184405.592390                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178362.970711                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182512.969397                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192061.533656                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190659.928748                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183355.306810                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188566.722273                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188357.244852                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187420.225474                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 180808.885111                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 185445.898815                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76702                       # Transaction distribution
system.membus.trans_dist::ReadResp             435346                       # Transaction distribution
system.membus.trans_dist::WriteReq              33616                       # Transaction distribution
system.membus.trans_dist::WriteResp             33616                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1053198                       # Transaction distribution
system.membus.trans_dist::CleanEvict           195936                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34438                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           14271                       # Transaction distribution
system.membus.trans_dist::ReadExReq            877665                       # Transaction distribution
system.membus.trans_dist::ReadExResp           877665                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        358644                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        56664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122464                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6736                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3728417                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3857678                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       295106                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       295106                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4152784                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    139314336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    139483644                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7302016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7302016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               146785660                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1643                       # Total snoops (count)
system.membus.snoop_fanout::samples           2736894                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2736894    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2736894                       # Request fanout histogram
system.membus.reqLayer0.occupancy            69642000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1869502                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          3024540179                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2745498213                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           28895247                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     51377281                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     26019251                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         2963                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           1998                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         1998                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            1480293                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          23646990                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33616                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33616                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      7917317                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     15707105                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2286569                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           43130                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          43132                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1967850                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1967850                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15707694                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6464392                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1273831                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1223831                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47208661                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29171496                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       814900                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1708889                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              78903946                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2010714388                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1017569896                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2939088                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6022496                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3037245868                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1649773                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         37956541                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.016464                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.127251                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               37331626     98.35%     98.35% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 624915      1.65%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           37956541                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        30638283989                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           663187                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       15222114677                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        7813255878                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         290580214                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         698608876                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------