path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.274675                       # Number of seconds simulated
sim_ticks                                51274674635500                       # Number of ticks simulated
final_tick                               51274674635500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 308954                       # Simulator instruction rate (inst/s)
host_op_rate                                   363040                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            18009090527                       # Simulator tick rate (ticks/s)
host_mem_usage                                 661116                       # Number of bytes of host memory used
host_seconds                                  2847.16                       # Real time elapsed on the host
sim_insts                                   879639951                       # Number of instructions simulated
sim_ops                                    1033631621                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::realview.ide        391104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker       245504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       412480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2683060                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         32648008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        82560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       137216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           615744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          8957184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker       211392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker       332480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          2079744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data         22931008                       # Number of bytes read from this memory
system.physmem.bytes_read::total             71727484                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2683060                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       615744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      2079744                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5378548                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     40940416                       # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide      6826496                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data      59033572                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data      12553152                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data      28525952                       # Number of bytes written to this memory
system.physmem.bytes_written::total         147879588                       # Number of bytes written to this memory
system.physmem.num_reads::realview.ide           6111                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker         3836                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         6445                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             82330                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            510138                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1290                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2144                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              9621                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            139956                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker         3303                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker         5195                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             32496                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            358297                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1161162                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          639694                       # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide        106664                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data           924651                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data           196143                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data           445718                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              2312870                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide             7628                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker          4788                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          8045                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               52327                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              636728                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1610                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2676                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               12009                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              174690                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker          4123                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker          6484                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               40561                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              447219                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1398887                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          52327                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          12009                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          40561                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             104897                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks            798453                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide          133136                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data            1151320                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data             244822                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data             556336                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2884067                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks            798453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide          140763                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4788                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         8045                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              52327                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1788048                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2676                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              12009                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             419512                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker         4123                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker         6484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              40561                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1003555                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4282954                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        556099                       # Number of read requests accepted
system.physmem.writeReqs                       996967                       # Number of write requests accepted
system.physmem.readBursts                      556099                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     996967                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 35500160                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     90176                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  61170112                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  35590336                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               63805888                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1409                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   41184                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          18778                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               32891                       # Per bank write bursts
system.physmem.perBankRdBursts::1               34922                       # Per bank write bursts
system.physmem.perBankRdBursts::2               33947                       # Per bank write bursts
system.physmem.perBankRdBursts::3               34663                       # Per bank write bursts
system.physmem.perBankRdBursts::4               34185                       # Per bank write bursts
system.physmem.perBankRdBursts::5               37826                       # Per bank write bursts
system.physmem.perBankRdBursts::6               34767                       # Per bank write bursts
system.physmem.perBankRdBursts::7               37084                       # Per bank write bursts
system.physmem.perBankRdBursts::8               34802                       # Per bank write bursts
system.physmem.perBankRdBursts::9               37662                       # Per bank write bursts
system.physmem.perBankRdBursts::10              34607                       # Per bank write bursts
system.physmem.perBankRdBursts::11              34013                       # Per bank write bursts
system.physmem.perBankRdBursts::12              33947                       # Per bank write bursts
system.physmem.perBankRdBursts::13              34396                       # Per bank write bursts
system.physmem.perBankRdBursts::14              33124                       # Per bank write bursts
system.physmem.perBankRdBursts::15              31854                       # Per bank write bursts
system.physmem.perBankWrBursts::0               51538                       # Per bank write bursts
system.physmem.perBankWrBursts::1               50883                       # Per bank write bursts
system.physmem.perBankWrBursts::2               55756                       # Per bank write bursts
system.physmem.perBankWrBursts::3               53410                       # Per bank write bursts
system.physmem.perBankWrBursts::4               72819                       # Per bank write bursts
system.physmem.perBankWrBursts::5               60009                       # Per bank write bursts
system.physmem.perBankWrBursts::6               50793                       # Per bank write bursts
system.physmem.perBankWrBursts::7               81282                       # Per bank write bursts
system.physmem.perBankWrBursts::8               66815                       # Per bank write bursts
system.physmem.perBankWrBursts::9               79578                       # Per bank write bursts
system.physmem.perBankWrBursts::10              79171                       # Per bank write bursts
system.physmem.perBankWrBursts::11              57649                       # Per bank write bursts
system.physmem.perBankWrBursts::12              53518                       # Per bank write bursts
system.physmem.perBankWrBursts::13              50714                       # Per bank write bursts
system.physmem.perBankWrBursts::14              46719                       # Per bank write bursts
system.physmem.perBankWrBursts::15              45129                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          45                       # Number of times write queue was full causing retry
system.physmem.totGap                    51273477930500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  556099                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 996967                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    389698                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    112133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     36470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     14160                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       527                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       309                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       262                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       212                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       147                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       91                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       79                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    25995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    37928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    42662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    45878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    50737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    55571                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    55063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    61456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    62119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    67007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    62568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    56729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    57939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    47309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    45594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    44878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    43071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1235                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      867                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      820                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      732                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      580                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      506                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      114                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       313965                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      307.901429                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     171.041097                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     348.087880                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         132720     42.27%     42.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        70601     22.49%     64.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        25843      8.23%     72.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        12745      4.06%     77.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         9334      2.97%     80.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         6247      1.99%     82.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         5388      1.72%     83.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6641      2.12%     85.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        44446     14.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         313965                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         40272                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        13.773590                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      142.393884                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          40271    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           40272                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         40272                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        23.733189                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       21.769670                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.088668                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                 6      0.01%      0.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 2      0.00%      0.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                4      0.01%      0.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              68      0.17%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           21743     53.99%     54.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            7529     18.70%     72.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             844      2.10%     74.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31            2202      5.47%     80.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35            3572      8.87%     89.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             961      2.39%     91.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             568      1.41%     93.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47             548      1.36%     94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             664      1.65%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             107      0.27%     96.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              86      0.21%     96.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63             131      0.33%     96.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             645      1.60%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71             191      0.47%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75             148      0.37%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             110      0.27%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              71      0.18%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87              17      0.04%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               8      0.02%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               9      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             5      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             6      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             4      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           40272                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10784853014                       # Total ticks spent queuing
system.physmem.totMemAccLat               21185290514                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2773450000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19443.03                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38193.03                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.69                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.19                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.69                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.24                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.80                       # Average write queue length when enqueuing
system.physmem.readRowHits                     423817                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    772691                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.41                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  80.84                       # Row buffer hit rate for writes
system.physmem.avgGap                     33014358.65                       # Average gap between requests
system.physmem.pageHitRate                      79.21                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     49344562776500                       # Time in different power states
system.physmem.memoryStateTime::REF      1712173840000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      217931188500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                1214869320                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                1158706080                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 662875125                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 632230500                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               2186223000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               2140359000                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              3087655200                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              3105818640                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3349012031040                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3349012031040                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1215657712530                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1211135236200                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          29698434260250                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          29702401344750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            34270255626465                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            34269585726210                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.366215                       # Core power per rank (mW)
system.physmem.averagePower::1             668.353150                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq              512200                       # Transaction distribution
system.membus.trans_dist::ReadResp             512200                       # Transaction distribution
system.membus.trans_dist::WriteReq              33772                       # Transaction distribution
system.membus.trans_dist::WriteResp             33772                       # Transaction distribution
system.membus.trans_dist::Writeback            639694                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq      1670603                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp      1670603                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36363                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36366                       # Transaction distribution
system.membus.trans_dist::ReadExReq            685391                       # Transaction distribution
system.membus.trans_dist::ReadExResp           685391                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122952                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6750                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6155552                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6285312                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       229159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       229159                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6514471                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156082                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13500                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    212389664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    212559378                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7272512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7272512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               219831890                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1887                       # Total snoops (count)
system.membus.snoop_fanout::samples           3467502                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3467502    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3467502                       # Request fanout histogram
system.membus.reqLayer0.occupancy            48925999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1640000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9861261476                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6001066379                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           87450398                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                   829792                       # number of replacements
system.l2c.tags.tagsinuse                64538.969055                       # Cycle average of tags in use
system.l2c.tags.total_refs                   28099922                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   891020                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    31.536803                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle             13806560382000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35856.169681                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   191.429036                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   290.837170                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3857.675402                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9456.283942                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    48.759094                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    73.219747                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      709.055197                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2692.383155                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker   111.816270                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker   164.499208                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     2725.095268                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     8361.745885                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.547122                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002921                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004438                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.058863                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.144291                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000744                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.001117                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.010819                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.041083                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001706                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.002510                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.041582                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.127590                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.984787                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          502                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        60726                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::0            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1            4                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            7                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          489                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2207                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4867                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53302                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.007660                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.926605                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                265686556                       # Number of tag accesses
system.l2c.tags.data_accesses               265686556                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       200882                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       128104                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst            6599762                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data            3104423                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        71894                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        47918                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst            2040254                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data             973662                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       383209                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker       140169                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst            5756088                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data            2406989                       # number of ReadReq hits
system.l2c.ReadReq_hits::total               21853354                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         6807908                       # number of Writeback hits
system.l2c.Writeback_hits::total              6807908                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            5076                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1634                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            4357                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               11067                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           707211                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           212100                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           483663                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1402974                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker        200882                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        128104                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6599762                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3811634                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         71894                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         47918                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             2040254                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             1185762                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        383209                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker        140169                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             5756088                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             2890652                       # number of demand (read+write) hits
system.l2c.demand_hits::total                23256328                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       200882                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       128104                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6599762                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3811634                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        71894                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        47918                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            2040254                       # number of overall hits
system.l2c.overall_hits::cpu1.data            1185762                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       383209                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker       140169                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            5756088                       # number of overall hits
system.l2c.overall_hits::cpu2.data            2890652                       # number of overall hits
system.l2c.overall_hits::total               23256328                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         3836                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         6445                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            39229                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           153846                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         1290                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2144                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst             9621                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data            42836                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker         3311                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker         5220                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst            32496                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data           126310                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               426584                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17268                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          5409                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data         13103                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35780                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         356597                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          97202                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data         232172                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             685971                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3836                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         6445                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             39229                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            510443                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1290                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2144                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              9621                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            140038                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker         3311                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker         5220                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             32496                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data            358482                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1112555                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3836                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         6445                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            39229                       # number of overall misses
system.l2c.overall_misses::cpu0.data           510443                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1290                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2144                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             9621                       # number of overall misses
system.l2c.overall_misses::cpu1.data           140038                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker         3311                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker         5220                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            32496                       # number of overall misses
system.l2c.overall_misses::cpu2.data           358482                       # number of overall misses
system.l2c.overall_misses::total              1112555                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     98176250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    165694000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst    710409250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   3173067500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker    260580226                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker    407293488                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst   2545464971                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data  10430324641                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    17791010326                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     64697721                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data    151206011                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    215903732                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        23499                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data        22999                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        46498                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   6960631918                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data  20491301758                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  27451933676                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     98176250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    165694000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    710409250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  10133699418                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker    260580226                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker    407293488                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   2545464971                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data  30921626399                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     45242944002                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     98176250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    165694000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    710409250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  10133699418                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker    260580226                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker    407293488                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   2545464971                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data  30921626399                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    45242944002                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       204718                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       134549                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst        6638991                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        3258269                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        73184                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        50062                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst        2049875                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data        1016498                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       386520                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker       145389                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst        5788584                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data        2533299                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total           22279938                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      6807908                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          6807908                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        22344                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         7043                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data        17460                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           46847                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1063808                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       309302                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       715835                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2088945                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       204718                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       134549                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6638991                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4322077                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        73184                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        50062                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         2049875                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1325800                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       386520                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker       145389                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         5788584                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         3249134                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            24368883                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       204718                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       134549                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6638991                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4322077                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        73184                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        50062                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        2049875                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1325800                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       386520                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker       145389                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        5788584                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        3249134                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           24368883                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.005909                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.047217                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.004693                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.042141                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst      0.005614                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data      0.049860                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.019147                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.772825                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.767997                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.750458                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.763763                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.335208                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.314262                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.324337                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.328382                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005909                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.118101                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.004693                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.105625                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.005614                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.110332                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.045655                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.018738                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.047901                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005909                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.118101                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.017627                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.042827                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.004693                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.105625                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.008566                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.035904                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.005614                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.110332                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.045655                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73839.439767                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74074.785227                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78331.639925                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 82577.188196                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 41705.760943                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11961.124237                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11539.800885                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6034.201565                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        23499                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 11499.500000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15499.333333                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71609.966030                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88259.143041                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 40019.087798                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 73839.439767                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 72363.925634                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 78331.639925                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 86257.124204                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 40665.804389                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76105.620155                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 77282.649254                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 73839.439767                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 72363.925634                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 78701.366959                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 78025.572414                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 78331.639925                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 86257.124204                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 40665.804389                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              639694                       # number of writebacks
system.l2c.writebacks::total                   639694                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker            8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.itb.walker           25                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data             4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                37                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.dtb.walker            8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.itb.walker           25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 37                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.dtb.walker            8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.itb.walker           25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                37                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         1290                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2144                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst         9621                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data        42836                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker         3303                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker         5195                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst        32496                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data       126306                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          223191                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         5409                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data        13103                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        18512                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        97202                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data       232172                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        329374                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1290                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2144                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         9621                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       140038                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker         3303                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker         5195                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        32496                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data       358478                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           552565                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1290                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2144                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         9621                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       140038                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker         3303                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker         5195                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        32496                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data       358478                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          552565                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    139178500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    588487750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   2634900000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst   2138403529                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data   8858602217                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  15001935210                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   3923029000                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data  10580910001                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  14503939001                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     54095409                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    131333088                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    185428497                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        10001                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        20002                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5718766582                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data  17592121130                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  23310887712                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    139178500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    588487750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   8353666582                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   2138403529                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data  26450723347                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  38312822922                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     82180750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    139178500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    588487750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   8353666582                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker    218871226                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker    341311238                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   2138403529                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data  26450723347                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  38312822922                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    884253000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1618942500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   2503195500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    835101000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1639869500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2474970500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1719354000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   3258812000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4978166000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.042141                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.049858                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.010018                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.767997                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.750458                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.395159                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.314262                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.324337                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.157675                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.105625                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.110330                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.022675                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.017627                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.042827                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004693                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.105625                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.008545                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.035732                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005614                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.110330                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.022675                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61511.345597                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70136.036427                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 67215.681681                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10023.131191                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.664704                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58833.836567                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75771.932576                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70773.308494                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59652.855525                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73786.183105                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69336.318663                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63706.007752                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 64915.345149                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61167.004469                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59652.855525                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66264.373600                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 65699.949567                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65805.130755                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73786.183105                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69336.318663                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq           22792948                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          22787515                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33772                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33772                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          6807908                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq      1600102                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp      1563939                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           46847                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             6                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          46853                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2088945                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2088945                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     29041280                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27958653                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       843900                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1753644                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              59597477                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    926729300                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1105413310                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3095064                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6286720                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2041524394                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          368391                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         33333670                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            5.003466                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.058768                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5               33218144     99.65%     99.65% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                 115526      0.35%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           33333670                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        25204206978                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1129500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       35295410102                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       21026275011                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         267100118                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         646797339                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40334                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40334                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136600                       # Transaction distribution
system.iobus.trans_dist::WriteResp              66161                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq           65                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        70504                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48070                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230966                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353998                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48090                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156082                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492464                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             17794000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 2000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             9530000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy               91000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            16563000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               71000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           339092871                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            44416000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            84714602                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              144000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    79163453                       # DTB read hits
system.cpu0.dtb.read_misses                     85617                       # DTB read misses
system.cpu0.dtb.write_hits                   72660708                       # DTB write hits
system.cpu0.dtb.write_misses                    28291                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1291                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21000                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   52340                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3792                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9968                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                79249070                       # DTB read accesses
system.cpu0.dtb.write_accesses               72688999                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        151824161                       # DTB hits
system.cpu0.dtb.misses                         113908                       # DTB misses
system.cpu0.dtb.accesses                    151938069                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   424925918                       # ITB inst hits
system.cpu0.itb.inst_misses                     64800                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1291                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21000                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   37053                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               424990718                       # ITB inst accesses
system.cpu0.itb.hits                        424925918                       # DTB hits
system.cpu0.itb.misses                          64800                       # DTB misses
system.cpu0.itb.accesses                    424990718                       # DTB accesses
system.cpu0.numCycles                       511314689                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  424739937                       # Number of instructions committed
system.cpu0.committedOps                    499770936                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            458702697                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                419703                       # Number of float alu accesses
system.cpu0.num_func_calls                   25504192                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     64716286                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   458702697                       # number of integer instructions
system.cpu0.num_fp_insts                       419703                       # number of float instructions
system.cpu0.num_int_register_reads          675611920                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         364415309                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              677474                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             352628                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           112049346                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          111774000                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    151917751                       # number of memory refs
system.cpu0.num_load_insts                   79236622                       # Number of load instructions
system.cpu0.num_store_insts                  72681129                       # Number of store instructions
system.cpu0.num_idle_cycles              499253695.584872                       # Number of idle cycles
system.cpu0.num_busy_cycles              12060993.415128                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.023588                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.976412                       # Percentage of idle cycles
system.cpu0.Branches                         94879530                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                346985072     69.39%     69.39% # Class of executed instruction
system.cpu0.op_class::IntMult                 1058214      0.21%     69.60% # Class of executed instruction
system.cpu0.op_class::IntDiv                    47254      0.01%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.61% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             51204      0.01%     69.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.62% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.62% # Class of executed instruction
system.cpu0.op_class::MemRead                79236622     15.85%     85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite               72681129     14.53%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 500059496                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16293                       # number of quiesce instructions executed
system.cpu0.icache.tags.replacements         14476947                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.977197                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          610391871                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         14477459                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            42.161533                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       8950087250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   497.229242                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     6.558404                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst     8.189551                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.971151                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.012809                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.015995                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999955                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          246                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        639762187                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       639762187                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    418346381                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    129402990                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     62642500                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      610391871                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    418346381                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    129402990                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     62642500                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       610391871                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    418346381                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    129402990                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     62642500                       # number of overall hits
system.cpu0.icache.overall_hits::total      610391871                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6638991                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      2049875                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      6203870                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     14892736                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6638991                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      2049875                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      6203870                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      14892736                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6638991                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      2049875                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      6203870                       # number of overall misses
system.cpu0.icache.overall_misses::total     14892736                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  27332922248                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  82496329525                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 109829251773                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  27332922248                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  82496329525                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 109829251773                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  27332922248                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  82496329525                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 109829251773                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    424985372                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    131452865                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     68846370                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    625284607                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    424985372                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    131452865                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     68846370                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    625284607                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    424985372                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    131452865                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     68846370                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    625284607                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015622                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015594                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.090112                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.023818                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015622                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015594                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.090112                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.023818                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015622                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015594                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.090112                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.023818                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13333.945849                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13297.559350                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  7374.686006                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13333.945849                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13297.559350                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  7374.686006                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13333.945849                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13297.559350                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  7374.686006                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        37721                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             3310                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.396073                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst       415156                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       415156                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst       415156                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       415156                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst       415156                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       415156                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      2049875                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      5788714                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      7838589                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      2049875                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      5788714                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      7838589                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      2049875                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      5788714                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      7838589                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  23229700752                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  67401467898                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  90631168650                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  23229700752                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  67401467898                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  90631168650                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  23229700752                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  67401467898                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  90631168650                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.012536                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.012536                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015594                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.084082                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.012536                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11562.178939                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11562.178939                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11332.252333                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11643.599580                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11562.178939                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements         10128409                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999720                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          303013393                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10128921                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            29.915664                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.552561                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     7.756281                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.690878                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.971782                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015149                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013068                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          203                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1287987504                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1287987504                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     73967004                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     23189496                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     58636674                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      155793174                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     68735212                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     21073027                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     49137576                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     138945815                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       193443                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        57150                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data       141238                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       391831                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       922078                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       196143                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data       445718                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total      1563939                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1801315                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       562780                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data      1217494                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3581589                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1914885                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       606233                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data      1395393                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3916511                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    142702216                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     44262523                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data    107774250                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       294738989                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    142895659                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     44319673                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data    107915488                       # number of overall hits
system.cpu0.dcache.overall_hits::total      295130820                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2516282                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       796205                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data      4618007                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7930494                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1086152                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       320705                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data      4288284                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      5695141                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       627582                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       187561                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       448945                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1264088                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       114405                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        43721                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data       223929                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       382055                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data            5                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            6                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3602434                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      1116910                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      8906291                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      13625635                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4230016                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1304471                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      9355236                       # number of overall misses
system.cpu0.dcache.overall_misses::total     14889723                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  12447991000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  82795568309                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  95243559309                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  10567240491                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 177246244923                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 187813485414                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    612526750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data   3159923284                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3772450034                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        26501                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        90002                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       116503                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  23015231491                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 260041813232                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 283057044723                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  23015231491                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 260041813232                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 283057044723                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     76483286                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     23985701                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     63254681                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    163723668                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     69821364                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     21393732                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     53425860                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    144640956                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       821025                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       244711                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       590183                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1655919                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       922078                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       196143                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data       445718                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1563939                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1915720                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       606501                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data      1441423                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3963644                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1914885                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       606234                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data      1395398                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3916517                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    146304650                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     45379433                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data    116680541                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    308364624                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    147125675                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     45624144                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data    117270724                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    310020543                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032900                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033195                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.073007                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.048438                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015556                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014991                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.080266                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.039374                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764388                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.766459                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.760688                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.763376                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059719                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.072087                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.155353                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.096390                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024623                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024613                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.076331                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.044187                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028751                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028592                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.079775                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.048028                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15634.153265                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17928.852925                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12009.788963                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32950.033492                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 41332.674077                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 32977.846451                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14009.897990                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14111.273145                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9874.101985                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        26501                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 18000.400000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19417.166667                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20606.164768                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 29197.542864                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20773.860794                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17643.344690                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27796.392655                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 19010.229050                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     21434212                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        26746                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          1267990                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            380                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.904086                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    70.384211                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                1563939                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      6807908                       # number of writebacks
system.cpu0.dcache.writebacks::total          6807908                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data          948                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data      2610303                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2611251                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4360                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      3551132                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3555492                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         9967                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data       136103                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       146070                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         5308                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data      6161435                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      6166743                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         5308                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data      6161435                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      6166743                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       795257                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data      2007704                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      2802961                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       316345                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       729165                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1045510                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       187487                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       441899                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       629386                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        33754                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        87826                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       121580                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            5                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      1111602                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      2736869                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      3848471                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1299089                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      3178768                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4477857                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  10787340750                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  30936267343                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  41723608093                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   9783657259                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  28438527940                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  38222185199                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2771251250                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   9108575422                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  11879826672                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data   6372956000                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data  16470207883                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  22843163883                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    406720000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data   1117052111                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1523772111                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        24499                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        79998                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       104497                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  20570998009                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  59374795283                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  79945793292                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  23342249259                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  68483370705                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  91825619964                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    959248000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1745955500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2705203500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    898794000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1756075958                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2654869958                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1858042000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3502031458                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   5360073458                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033155                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031740                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.017120                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014787                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.013648                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007228                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.766157                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.748749                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.380083                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.055654                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.060930                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.030674                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024496                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023456                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.012480                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028474                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027106                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.014444                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13564.597042                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15408.779055                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14885.547139                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30927.175264                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 39001.498893                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36558.411875                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14781.031485                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20612.346762                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18875.263625                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12049.534870                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12718.922768                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12533.082012                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        24499                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15999.600000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17416.166667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18505.722380                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21694.423549                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20773.391119                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17968.167892                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21543.997771                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20506.599466                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    24842678                       # DTB read hits
system.cpu1.dtb.read_misses                     30288                       # DTB read misses
system.cpu1.dtb.write_hits                   22204387                       # DTB write hits
system.cpu1.dtb.write_misses                     9453                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1282                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               6426                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   22120                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  1240                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2953                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                24872966                       # DTB read accesses
system.cpu1.dtb.write_accesses               22213840                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         47047065                       # DTB hits
system.cpu1.dtb.misses                          39741                       # DTB misses
system.cpu1.dtb.accesses                     47086806                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                   131452865                       # ITB inst hits
system.cpu1.itb.inst_misses                     23431                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1282                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               6426                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    146                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   16167                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               131476296                       # ITB inst accesses
system.cpu1.itb.hits                        131452865                       # DTB hits
system.cpu1.itb.misses                          23431                       # DTB misses
system.cpu1.itb.accesses                    131476296                       # DTB accesses
system.cpu1.numCycles                      1282114185                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  131358204                       # Number of instructions committed
system.cpu1.committedOps                    154205938                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            141499337                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                128756                       # Number of float alu accesses
system.cpu1.num_func_calls                    7727196                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     20146536                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   141499337                       # number of integer instructions
system.cpu1.num_fp_insts                       128756                       # number of float instructions
system.cpu1.num_int_register_reads          205950168                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         112374883                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              204901                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             115300                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            34581843                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           34518712                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     47044288                       # number of memory refs
system.cpu1.num_load_insts                   24842081                       # Number of load instructions
system.cpu1.num_store_insts                  22202207                       # Number of store instructions
system.cpu1.num_idle_cycles              1255604442.364680                       # Number of idle cycles
system.cpu1.num_busy_cycles              26509742.635320                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.020677                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.979323                       # Percentage of idle cycles
system.cpu1.Branches                         29364446                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                106871098     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                  352774      0.23%     69.49% # Class of executed instruction
system.cpu1.op_class::IntDiv                    14834      0.01%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             17563      0.01%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::MemRead                24842081     16.10%     85.61% # Class of executed instruction
system.cpu1.op_class::MemWrite               22202207     14.39%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 154300599                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               95476448                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         64928073                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          4299413                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            64784895                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               46332623                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            71.517632                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS               12285804                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            131917                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    77077341                       # DTB read hits
system.cpu2.dtb.read_misses                    441139                       # DTB read misses
system.cpu2.dtb.write_hits                   58693711                       # DTB write hits
system.cpu2.dtb.write_misses                   191612                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1283                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid              14423                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    383                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   37244                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                       88                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  5986                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                    37589                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                77518480                       # DTB read accesses
system.cpu2.dtb.write_accesses               58885323                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                        135771052                       # DTB hits
system.cpu2.dtb.misses                         632751                       # DTB misses
system.cpu2.dtb.accesses                    136403803                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.inst_hits                    69012170                       # ITB inst hits
system.cpu2.itb.inst_misses                     76652                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1283                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid              14423                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    383                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   28880                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                   143189                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                69088822                       # ITB inst accesses
system.cpu2.itb.hits                         69012170                       # DTB hits
system.cpu2.itb.misses                          76652                       # DTB misses
system.cpu2.itb.accesses                     69088822                       # DTB accesses
system.cpu2.numCycles                       465978411                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles         177853142                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                     424737263                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   95476448                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          58618427                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                    260785808                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                9691059                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                   1879827                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                8981                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles             2007                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles      3759830                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles       120446                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles         3389                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                 68846411                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes              2635973                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                  29904                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples         449258797                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.104850                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.350365                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0               344689329     76.72%     76.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                13175573      2.93%     79.66% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                13441142      2.99%     82.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 9727641      2.17%     84.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                19687409      4.38%     89.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                 6520571      1.45%     90.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                 7057131      1.57%     92.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                 6252659      1.39%     93.61% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                28707342      6.39%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total           449258797                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.204895                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.911496                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles               145040906                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles            213951941                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 77038080                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              9368936                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles               3856816                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved            14196524                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred              1002861                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts             463271274                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts              3090116                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles               3856816                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles               150407499                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles               19371841                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles     168106415                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 80889236                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles             26624521                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts             452059055                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                70033                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents               1786376                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents               1304038                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents              13315771                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.FullRegisterEvents            3626                       # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands          431846627                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            688168989                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups       533483946                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups           696961                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps            360553438                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                71293189                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts           9871202                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts       8455912                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                 51921554                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads            73490892                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores           61773042                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads          9381483                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores        10099562                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                 429589038                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded            9855415                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                428971223                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued           602179                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined       55645947                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     38557670                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved        233014                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples    449258797                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.954842                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.673453                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0          283324312     63.06%     63.06% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1           67630078     15.05%     78.12% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2           31491211      7.01%     85.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3           22481401      5.00%     90.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4           17057859      3.80%     93.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5           11702074      2.60%     96.53% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6            7876083      1.75%     98.29% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7            4650016      1.04%     99.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8            3045763      0.68%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total      449258797                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                2154851     25.07%     25.07% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                 17173      0.20%     25.27% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                   1684      0.02%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead               3571205     41.55%     66.84% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite              2850152     33.16%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu            289729991     67.54%     67.54% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult             1034875      0.24%     67.78% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                48976      0.01%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                286      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.79% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc         48552      0.01%     67.80% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     67.80% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.80% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead            78627004     18.33%     86.13% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite           59481539     13.87%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total             428971223                       # Type of FU issued
system.cpu2.iq.rate                          0.920582                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                    8595065                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.020036                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads        1315569237                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes        495173501                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses    412035990                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads             829250                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes            394091                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses       358547                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses             437122606                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                 443682                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads         3384290                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads     12185839                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses        16415                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation       485486                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores      6512236                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads      2660066                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked      6807125                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles               3856816                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles               10978406                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles              6986714                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts          439540206                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts          1332617                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts             73490892                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts            61773042                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts           8263038                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                174452                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents              6729882                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents        485486                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect       1971342                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect      1708494                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts             3679836                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts            423953682                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts             77064700                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts          4393197                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                        95753                       # number of nop insts executed
system.cpu2.iew.exec_refs                   135758319                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                78468818                       # Number of branches executed
system.cpu2.iew.exec_stores                  58693619                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.909814                       # Inst execution rate
system.cpu2.iew.wb_sent                     413267935                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                    412394537                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                203830371                       # num instructions producing a value
system.cpu2.iew.wb_consumers                353623803                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.885008                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.576405                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts       59831265                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls        9622401                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts          3310537                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples    439132239                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.864557                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.865641                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0    302394835     68.86%     68.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1     65341940     14.88%     83.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2     24189817      5.51%     89.25% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3     10943430      2.49%     91.74% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4      7703754      1.75%     93.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5      4855013      1.11%     94.60% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6      4328620      0.99%     95.59% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7      2957558      0.67%     96.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8     16417272      3.74%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total    439132239                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts           323541810                       # Number of instructions committed
system.cpu2.commit.committedOps             379654747                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                     116565859                       # Number of memory references committed
system.cpu2.commit.loads                     61305053                       # Number of loads committed
system.cpu2.commit.membars                    2541238                       # Number of memory barriers committed
system.cpu2.commit.branches                  72175443                       # Number of branches committed
system.cpu2.commit.fp_insts                    344817                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                348881889                       # Number of committed integer instructions.
system.cpu2.commit.function_calls             9429592                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu       262221519     69.07%     69.07% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult         789172      0.21%     69.28% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv           36211      0.01%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     69.29% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc        41986      0.01%     69.30% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     69.30% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.30% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.30% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead       61305053     16.15%     85.44% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite      55260806     14.56%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total        379654747                       # Class of committed instruction
system.cpu2.commit.bw_lim_events             16417272                       # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads                   859553355                       # The number of ROB reads
system.cpu2.rob.rob_writes                  889110894                       # The number of ROB writes
system.cpu2.timesIdled                        2948522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                       16719614                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                 99518769709                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                  323541810                       # Number of Instructions Simulated
system.cpu2.committedOps                    379654747                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.440242                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.440242                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.694328                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.694328                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads               498743361                       # number of integer regfile reads
system.cpu2.int_regfile_writes              295064264                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                   684469                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                  420852                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                 90009576                       # number of cc regfile reads
system.cpu2.cc_regfile_writes                90769749                       # number of cc regfile writes
system.cpu2.misc_regfile_reads             1656723881                       # number of misc regfile reads
system.cpu2.misc_regfile_writes               9715045                       # number of misc regfile writes
system.iocache.tags.replacements               115464                       # number of replacements
system.iocache.tags.tagsinuse               10.421560                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115480                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13085874574509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.547265                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.874295                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221704                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429643                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651348                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040224                       # Number of tag accesses
system.iocache.tags.data_accesses             1040224                       # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide       106664                       # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total       106664                       # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8819                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8856                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide           65                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total           65                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8819                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8859                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8819                       # number of overall misses
system.iocache.overall_misses::total             8859                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      2752000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1272471430                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1275223430                       # number of ReadReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      2752000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1272471430                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1275223430                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      2752000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1272471430                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1275223430                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8819                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8856                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106729                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106729                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8819                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8859                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8819                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8859                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide     0.000609                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total     0.000609                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 144287.496315                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 143995.418925                       # average ReadReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 144287.496315                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 143946.656508                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet        68800                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 144287.496315                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 143946.656508                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         36080                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3735                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.659973                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                     106664                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ethernet           16                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         5668                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         5684                       # number of ReadReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           16                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         5668                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         5684                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           16                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         5668                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         5684                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      1920000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide    977655446                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    979575446                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide   2261356027                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   2261356027                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      1920000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide    977655446                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    979575446                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      1920000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide    977655446                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    979575446                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet     0.432432                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.641825                       # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.641607                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet     0.400000                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.642703                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.641607                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet       120000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172486.846507                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 172339.100281                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total          inf                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 172486.846507                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 172339.100281                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet       120000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 172486.846507                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 172339.100281                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------