path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.278388                       # Number of seconds simulated
sim_ticks                                51278388278000                       # Number of ticks simulated
final_tick                               51278388278000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 269488                       # Simulator instruction rate (inst/s)
host_op_rate                                   316679                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            16295713635                       # Simulator tick rate (ticks/s)
host_mem_usage                                 687640                       # Number of bytes of host memory used
host_seconds                                  3146.74                       # Real time elapsed on the host
sim_insts                                   848009832                       # Number of instructions simulated
sim_ops                                     996505618                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        80512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        85376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2480372                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         43948744                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        23424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        20864                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           458368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          5839488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker        24512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker        21952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst          1437632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          8179392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker        64832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker        58944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst          1702784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data         14408960                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        423680                       # Number of bytes read from this memory
system.physmem.bytes_read::total             79259836                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2480372                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       458368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst      1437632                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst      1702784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         6079156                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67469760                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67490340                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1258                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1334                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             79163                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            686712                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          366                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker          326                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              7162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             91242                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker          383                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker          343                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst             22463                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data            127803                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker         1013                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker          921                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst             26606                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data            225140                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6620                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1278855                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1054215                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1056788                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1570                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1665                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               48371                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              857062                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker           457                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker           407                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst                8939                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              113878                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker           478                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker           428                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst               28036                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data              159510                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker          1149                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst               33207                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data              280995                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8262                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1545677                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          48371                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst           8939                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst          28036                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst          33207                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             118552                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1315754                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1316156                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1315754                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1570                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1665                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              48371                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             857463                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker          457                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker          407                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst               8939                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             113878                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker          478                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker          428                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst              28036                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data             159510                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker         1149                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst              33207                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data             280995                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8262                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2861833                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        508133                       # Number of read requests accepted
system.physmem.writeReqs                       442708                       # Number of write requests accepted
system.physmem.readBursts                      508133                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     442708                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 32496192                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     24320                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  28331264                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  32520512                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               28333312                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      380                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         172464                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               28425                       # Per bank write bursts
system.physmem.perBankRdBursts::1               32222                       # Per bank write bursts
system.physmem.perBankRdBursts::2               31678                       # Per bank write bursts
system.physmem.perBankRdBursts::3               29785                       # Per bank write bursts
system.physmem.perBankRdBursts::4               32093                       # Per bank write bursts
system.physmem.perBankRdBursts::5               37258                       # Per bank write bursts
system.physmem.perBankRdBursts::6               31249                       # Per bank write bursts
system.physmem.perBankRdBursts::7               31793                       # Per bank write bursts
system.physmem.perBankRdBursts::8               30380                       # Per bank write bursts
system.physmem.perBankRdBursts::9               34315                       # Per bank write bursts
system.physmem.perBankRdBursts::10              33552                       # Per bank write bursts
system.physmem.perBankRdBursts::11              33985                       # Per bank write bursts
system.physmem.perBankRdBursts::12              32112                       # Per bank write bursts
system.physmem.perBankRdBursts::13              32580                       # Per bank write bursts
system.physmem.perBankRdBursts::14              28200                       # Per bank write bursts
system.physmem.perBankRdBursts::15              28126                       # Per bank write bursts
system.physmem.perBankWrBursts::0               25043                       # Per bank write bursts
system.physmem.perBankWrBursts::1               27380                       # Per bank write bursts
system.physmem.perBankWrBursts::2               27369                       # Per bank write bursts
system.physmem.perBankWrBursts::3               27020                       # Per bank write bursts
system.physmem.perBankWrBursts::4               28395                       # Per bank write bursts
system.physmem.perBankWrBursts::5               31777                       # Per bank write bursts
system.physmem.perBankWrBursts::6               27205                       # Per bank write bursts
system.physmem.perBankWrBursts::7               28447                       # Per bank write bursts
system.physmem.perBankWrBursts::8               27006                       # Per bank write bursts
system.physmem.perBankWrBursts::9               30006                       # Per bank write bursts
system.physmem.perBankWrBursts::10              27888                       # Per bank write bursts
system.physmem.perBankWrBursts::11              28964                       # Per bank write bursts
system.physmem.perBankWrBursts::12              27392                       # Per bank write bursts
system.physmem.perBankWrBursts::13              28158                       # Per bank write bursts
system.physmem.perBankWrBursts::14              25051                       # Per bank write bursts
system.physmem.perBankWrBursts::15              25575                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
system.physmem.totGap                    51277388057000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  508133                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 442708                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    359636                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     94580                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     31194                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     18770                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       374                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       374                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       769                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       482                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      260                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       75                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       566                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     8022                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    18082                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    21480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    24501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    25734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    26594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    26643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    27137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    27291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    27367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    29561                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    27445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    27298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    29173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    25766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    25736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    24591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      514                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      260                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       46                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       256507                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      237.135361                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.751053                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     277.773032                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         118370     46.15%     46.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        63779     24.86%     71.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        23560      9.18%     80.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        11879      4.63%     84.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         8772      3.42%     88.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         5502      2.14%     90.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         4497      1.75%     92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         3462      1.35%     93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16686      6.51%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         256507                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         24650                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.597972                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       13.431676                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31            22290     90.43%     90.43% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63            2167      8.79%     99.22% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95             156      0.63%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127             17      0.07%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159             6      0.02%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-191             3      0.01%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-223             1      0.00%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255             2      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287             2      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::320-351             1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::416-447             1      0.00%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::448-479             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::544-575             1      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::640-671             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::672-703             1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           24650                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         24650                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.958458                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.276383                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.669540                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                25      0.10%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                12      0.05%      0.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               19      0.08%      0.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              47      0.19%      0.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           22852     92.71%     93.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             503      2.04%     95.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             178      0.72%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             262      1.06%     96.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              56      0.23%     97.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             180      0.73%     97.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              74      0.30%     98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              10      0.04%     98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              29      0.12%     98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              72      0.29%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              15      0.06%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              17      0.07%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             194      0.79%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              14      0.06%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              52      0.21%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               7      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            10      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           24650                       # Writes before turning the bus around for reads
system.physmem.totQLat                    10544434255                       # Total ticks spent queuing
system.physmem.totMemAccLat               20064803005                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2538765000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20766.86                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39516.86                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.63                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.55                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.63                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.69                       # Average write queue length when enqueuing
system.physmem.readRowHits                     386701                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    307219                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.16                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.40                       # Row buffer hit rate for writes
system.physmem.avgGap                     53928457.08                       # Average gap between requests
system.physmem.pageHitRate                      73.01                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  977757480                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  531832125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1985068800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               1442681280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1177046851320                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           30704731659000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             35197141399605                       # Total energy per rank (pJ)
system.physmem_0.averagePower              665.410484                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   48872276305390                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1692446600000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    119675759110                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  961435440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  522856125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1975334400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               1425859200                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3310425549600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1177208679735                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29690763244500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34183282959000                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.568308                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   48872046794911                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1692446600000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    119910447839                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           196                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             30                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                    90321                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong                90321                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples        90321                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0          90321    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total        90321                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.524259                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0   -203938078758    -52.43%    -52.43% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1   592940707750    152.43%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        65935     84.97%     84.97% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        11661     15.03%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total        77596                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90321                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90321                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        77596                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        77596                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       167917                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    64849168                       # DTB read hits
system.cpu0.dtb.read_misses                     68465                       # DTB read misses
system.cpu0.dtb.write_hits                   59113138                       # DTB write hits
system.cpu0.dtb.write_misses                    21856                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1195                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   40748                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  2820                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     7506                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                64917633                       # DTB read accesses
system.cpu0.dtb.write_accesses               59134994                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        123962306                       # DTB hits
system.cpu0.dtb.misses                          90321                       # DTB misses
system.cpu0.dtb.accesses                    124052627                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    53302                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                53302                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        53302                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          53302    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        53302                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 389002628992                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.524352                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -203974223258    -52.44%    -52.44% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   592976852250    152.44%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 389002628992                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        46280     94.90%     94.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2485      5.10%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        48765                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        53302                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        53302                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        48765                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        48765                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       102067                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   346354960                       # ITB inst hits
system.cpu0.itb.inst_misses                     53302                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1195                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              16233                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    380                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   28697                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               346408262                       # ITB inst accesses
system.cpu0.itb.hits                        346354960                       # DTB hits
system.cpu0.itb.misses                          53302                       # DTB misses
system.cpu0.itb.accesses                    346408262                       # DTB accesses
system.cpu0.numCycles                       417857825                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16514                       # number of quiesce instructions executed
system.cpu0.committedInsts                  346212347                       # Number of instructions committed
system.cpu0.committedOps                    407289562                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            374196807                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                371114                       # Number of float alu accesses
system.cpu0.num_func_calls                   20959157                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     52529410                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   374196807                       # number of integer instructions
system.cpu0.num_fp_insts                       371114                       # number of float instructions
system.cpu0.num_int_register_reads          546236459                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         297045333                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              596552                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             319604                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads            90150585                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           89913729                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    124035099                       # number of memory refs
system.cpu0.num_load_insts                   64906131                       # Number of load instructions
system.cpu0.num_store_insts                  59128968                       # Number of store instructions
system.cpu0.num_idle_cycles              408498118.041102                       # Number of idle cycles
system.cpu0.num_busy_cycles              9359706.958898                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.022399                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.977601                       # Percentage of idle cycles
system.cpu0.Branches                         77291806                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                282487625     69.32%     69.32% # Class of executed instruction
system.cpu0.op_class::IntMult                  909497      0.22%     69.54% # Class of executed instruction
system.cpu0.op_class::IntDiv                    41524      0.01%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             50320      0.01%     69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
system.cpu0.op_class::MemRead                64906131     15.93%     85.49% # Class of executed instruction
system.cpu0.op_class::MemWrite               59128968     14.51%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 407524065                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          9647883                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.999717                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          292725890                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9648395                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.339335                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.728369                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data     5.127427                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     4.702216                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data     4.441704                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.972126                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.010015                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.009184                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data     0.008675                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          172                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1240366941                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1240366941                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     60678163                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     18920478                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data     25986249                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data     44943337                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      150528227                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     55903260                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     17361553                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data     23186798                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data     37880903                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     134332514                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       159106                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        46967                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data        76962                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112922                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       395957                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       126545                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data        46445                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data        59725                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data        96822                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       329537                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1458264                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       430071                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       571691                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       929686                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3389712                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1549495                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data       467643                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       621749                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1067526                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3706413                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    116581423                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data     36282031                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     49173047                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data     82824240                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       284860741                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    116740529                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data     36328998                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     49250009                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data     82937162                       # number of overall hits
system.cpu0.dcache.overall_hits::total      285256698                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2044900                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data       654690                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       963514                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data      3438861                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7101965                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       845622                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       251190                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data       604459                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data      3442356                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      5143627                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       463462                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       145087                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data       209925                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data       351338                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1169812                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       687578                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       110622                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data       150083                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data       277319                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1225602                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        91969                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        37784                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        50321                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       176189                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       356263                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      2890522                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data       905880                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1567973                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data      6881217                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      12245592                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3353984                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      1050967                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1777898                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data      7232555                       # number of overall misses
system.cpu0.dcache.overall_misses::total     13415404                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  10730358500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  16517281500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  60662755500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  87910395500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   9179104000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22761343000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 115052000035                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 146992447035                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   3717932000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   5375214500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data  11073619157                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  20166765657                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    535758000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    751006000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2342018000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   3628782000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data        84500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        84500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  19909462500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  39278624500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 175714755535                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 234902842535                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  19909462500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  39278624500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 175714755535                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 234902842535                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     62723063                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     19575168                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data     26949763                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data     48382198                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    157630192                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     56748882                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     17612743                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data     23791257                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data     41323259                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    139476141                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       622568                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       192054                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       286887                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       464260                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1565769                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       814123                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       157067                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       209808                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       374141                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1555139                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1550233                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       467855                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       622012                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1105875                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3745975                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1549496                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       467643                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       621749                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1067527                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3706415                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    119471945                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data     37187911                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     50741020                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data     89705457                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    297106333                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    120094513                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data     37379965                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     51027907                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data     90169717                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    298672102                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032602                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033445                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.035752                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071077                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.045055                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014901                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014262                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.025407                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.083303                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.036878                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.744436                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.755449                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.731734                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.756770                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747117                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.844563                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.704298                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.715335                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.741215                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788098                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059326                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080760                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.080900                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.159321                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095106                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024194                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024360                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.030901                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data     0.076709                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.041216                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027928                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028116                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.034842                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data     0.080210                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.044917                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16389.983809                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17142.751948                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17640.362754                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12378.320014                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.473825                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37655.726857                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33422.458350                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 28577.586795                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 33609.336298                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35814.945730                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39930.978970                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16454.579592                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14179.493966                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14924.305956                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13292.645965                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10185.683049                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data        84500                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        42250                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21978.035170                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25050.574532                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25535.418449                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19182.644868                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18943.946385                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22092.732260                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24294.976745                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17509.934292                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     14425372                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        42395                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           882588                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            392                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.344401                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   108.150510                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7475106                       # number of writebacks
system.cpu0.dcache.writebacks::total          7475106                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         3650                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       124312                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1904102                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      2032064                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         4908                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       268057                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2861568                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      3134533                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           28                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2036                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         2064                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8313                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10472                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       108224                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       127009                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data         8558                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data       392369                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data      4765670                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      5166597                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data         8558                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data       392369                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data      4765670                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      5166597                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       651040                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       839202                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1534759                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3025001                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       246282                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       336402                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       580788                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1163472                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       144706                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       207290                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       344141                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       696137                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       110622                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       150055                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       275283                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       535960                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        29471                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        39849                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        67965                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137285                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data       897322                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data      1175604                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data      2115547                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      4188473                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      1042028                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data      1382894                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data      2459688                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      4884610                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         6832                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         6962                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         7151                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        20945                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         6305                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6510                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         6865                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        19680                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        13137                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        13472                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data        14016                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        40625                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9843427000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  13182169000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  26527501500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  49553097500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   8718556000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data  12098346000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  21094064660                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  41910966660                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   3026616000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   4207308500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   6719819000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  13953743500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   3607310000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   5223957500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data  10676266657                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  19507534157                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    382668000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    527867500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    968982000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1879517500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data        83500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        83500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  18561983000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  25280515000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  47621566160                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  91464064160                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  21588599000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  29487823500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  54341385160                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 105417807660                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1349798500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1371763500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data   1366987000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   4088549000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1281894000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1318427500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data   1339823955                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   3940145455                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2631692500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   2690191000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data   2706810955                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   8028694455                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033258                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.031139                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031722                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019190                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013983                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014140                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.014055                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008342                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.753465                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.722549                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.741268                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.444598                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.704298                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.715202                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.735773                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.344638                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062992                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.064065                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.061458                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036649                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024129                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.023169                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.023583                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.014098                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027877                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.027101                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.027278                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.016354                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15119.542578                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15707.980915                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17284.473654                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16381.183841                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35400.703259                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35963.953841                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36319.732260                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36022.325127                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20915.622020                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20296.726808                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19526.354023                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20044.536492                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 32609.336298                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34813.618340                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38782.876738                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36397.369500                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12984.561094                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13246.693769                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14257.073494                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13690.625341                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data        83500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        83500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20685.977832                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21504.277801                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22510.285122                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21837.090548                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20717.868426                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21323.270981                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22092.795981                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21581.622209                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197570.038056                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197035.837403                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191160.257307                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195204.058248                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203313.877875                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202523.425499                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 195167.364166                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200210.643039                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200326.748877                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199687.574228                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 193122.927725                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197629.401969                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         15696881                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.971340                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          558297724                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15697393                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.566270                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      11785355500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.712705                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst     4.090332                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    22.639696                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst     6.528608                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934986                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.007989                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.044218                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst     0.012751                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999944                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          152                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          310                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        590046663                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       590046663                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    340808018                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    105888169                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     63991635                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst     47609902                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      558297724                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    340808018                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    105888169                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     63991635                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst     47609902                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       558297724                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    340808018                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    105888169                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     63991635                       # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst     47609902                       # number of overall hits
system.cpu0.icache.overall_hits::total      558297724                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5595707                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      1686311                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst      3834374                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst      4935088                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     16051480                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5595707                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      1686311                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst      3834374                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst      4935088                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      16051480                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5595707                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      1686311                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst      3834374                       # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst      4935088                       # number of overall misses
system.cpu0.icache.overall_misses::total     16051480                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22823417500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52649440500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  66649232311                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 142122090311                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  22823417500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  52649440500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst  66649232311                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 142122090311                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  22823417500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  52649440500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst  66649232311                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 142122090311                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    346403725                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    107574480                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     67826009                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst     52544990                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    574349204                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    346403725                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    107574480                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     67826009                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst     52544990                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    574349204                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    346403725                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    107574480                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     67826009                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst     52544990                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    574349204                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016154                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015676                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.056533                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.093921                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.027947                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016154                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015676                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.056533                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst     0.093921                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.027947                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016154                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015676                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.056533                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst     0.093921                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.027947                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13534.524474                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13730.909009                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13505.176060                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  8854.142441                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13534.524474                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13730.909009                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13505.176060                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  8854.142441                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13534.524474                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13730.909009                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13505.176060                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  8854.142441                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        61485                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             3700                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.617568                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     15696881                       # number of writebacks
system.cpu0.icache.writebacks::total         15696881                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       354021                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       354021                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst       354021                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       354021                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst       354021                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       354021                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1686311                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3834374                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4581067                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     10101752                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      1686311                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst      3834374                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst      4581067                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     10101752                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      1686311                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst      3834374                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst      4581067                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     10101752                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21137106500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48815066500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  58829212841                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 128781385841                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21137106500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48815066500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  58829212841                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 128781385841                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21137106500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48815066500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  58829212841                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 128781385841                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.017588                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.017588                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015676                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.056533                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087184                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.017588                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.420852                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12534.524474                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12730.909009                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12841.814547                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.420852                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                    31728                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong                31728                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4579                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        23199                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            5                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples        31723                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.882640                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev   157.206647                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047        31722    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total        31723                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples        27783                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25230.482669                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21865.634493                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16058.224156                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535        27633     99.46%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          123      0.44%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143            5      0.02%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           12      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total        27783                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   2741941428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.632141                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.482223                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1008648500     36.79%     36.79% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     1733292928     63.21%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   2741941428                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        23199     83.52%     83.52% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M         4579     16.48%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        27778                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31728                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31728                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27778                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27778                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total        59506                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    20241909                       # DTB read hits
system.cpu1.dtb.read_misses                     24578                       # DTB read misses
system.cpu1.dtb.write_hits                   18246308                       # DTB write hits
system.cpu1.dtb.write_misses                     7150                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   17924                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   956                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     2537                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                20266487                       # DTB read accesses
system.cpu1.dtb.write_accesses               18253458                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         38488217                       # DTB hits
system.cpu1.dtb.misses                          31728                       # DTB misses
system.cpu1.dtb.accesses                     38519945                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    20290                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                20290                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2          971                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17908                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        20290                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          20290    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        20290                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        18879                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28298.930028                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25145.287562                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 17574.390852                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        18719     99.15%     99.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          141      0.75%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143            3      0.02%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679            8      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            3      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        18879                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        17908     94.86%     94.86% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          971      5.14%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        18879                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        20290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        20290                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18879                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18879                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total        39169                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   107574480                       # ITB inst hits
system.cpu1.itb.inst_misses                     20290                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid               5242                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   13368                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               107594770                       # ITB inst accesses
system.cpu1.itb.hits                        107574480                       # DTB hits
system.cpu1.itb.misses                          20290                       # DTB misses
system.cpu1.itb.accesses                    107594770                       # DTB accesses
system.cpu1.numCycles                      1186092617                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  107495721                       # Number of instructions committed
system.cpu1.committedOps                    126075283                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            115907756                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                113126                       # Number of float alu accesses
system.cpu1.num_func_calls                    6382091                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     16276077                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   115907756                       # number of integer instructions
system.cpu1.num_fp_insts                       113126                       # number of float instructions
system.cpu1.num_int_register_reads          166908100                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          91871167                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              184275                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes              91240                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            27698310                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           27628060                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     38485648                       # number of memory refs
system.cpu1.num_load_insts                   20241154                       # Number of load instructions
system.cpu1.num_store_insts                  18244494                       # Number of store instructions
system.cpu1.num_idle_cycles              1161627733.273481                       # Number of idle cycles
system.cpu1.num_busy_cycles              24464883.726519                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.020626                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.979374                       # Percentage of idle cycles
system.cpu1.Branches                         23916118                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 87373708     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                  271273      0.22%     69.47% # Class of executed instruction
system.cpu1.op_class::IntDiv                    11107      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             12264      0.01%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::MemRead                20241154     16.04%     85.54% # Class of executed instruction
system.cpu1.op_class::MemWrite               18244494     14.46%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 126154042                       # Class of executed instruction
system.cpu2.branchPred.lookups               39396533                       # Number of BP lookups
system.cpu2.branchPred.condPredicted         27362101                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect          1971184                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            28599658                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits               20206635                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            70.653415                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                4844874                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect            318265                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    92743                       # Table walker walks requested
system.cpu2.dtb.walker.walksLong                92743                       # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         6709                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        28755                       # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples        92743                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0          92743    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        92743                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples        35464                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 24952.261448                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 21836.970286                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 14872.403453                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535        35314     99.58%     99.58% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607          126      0.36%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143            2      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679           14      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751            6      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total        35464                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples   2000224000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0     2000224000    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total   2000224000                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K        28755     81.08%     81.08% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M         6709     18.92%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total        35464                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        92743                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        92743                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        35464                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        35464                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total       128207                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                    28135338                       # DTB read hits
system.cpu2.dtb.read_misses                     77405                       # DTB read misses
system.cpu2.dtb.write_hits                   24723604                       # DTB write hits
system.cpu2.dtb.write_misses                    15338                       # DTB write misses
system.cpu2.dtb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                   22464                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                       74                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                  2032                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                     3778                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                28212743                       # DTB read accesses
system.cpu2.dtb.write_accesses               24738942                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         52858942                       # DTB hits
system.cpu2.dtb.misses                          92743                       # DTB misses
system.cpu2.dtb.accesses                     52951685                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                    27058                       # Table walker walks requested
system.cpu2.itb.walker.walksLong                27058                       # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1852                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22698                       # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples        27058                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0          27058    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total        27058                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples        24550                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 28387.494908                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25558.389161                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 15951.956543                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767        12868     52.42%     52.42% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535        11496     46.83%     99.24% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839          141      0.57%     99.82% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607           26      0.11%     99.92% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375            3      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143            3      0.01%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911            4      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679            5      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::393216-425983            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total        24550                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2000197500    100.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total   2000197500                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K        22698     92.46%     92.46% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M         1852      7.54%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total        24550                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27058                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27058                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24550                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24550                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total        51608                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    67882722                       # ITB inst hits
system.cpu2.itb.inst_misses                     27058                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                        1186                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid               6517                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                    195                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                   16669                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                    53735                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                67909780                       # ITB inst accesses
system.cpu2.itb.hits                         67882722                       # DTB hits
system.cpu2.itb.misses                          27058                       # DTB misses
system.cpu2.itb.accesses                     67909780                       # DTB accesses
system.cpu2.numCycles                      6659969764                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.committedInsts                  144540812                       # Number of instructions committed
system.cpu2.committedOps                    169698177                       # Number of ops (including micro ops) committed
system.cpu2.discardedOps                     13684727                       # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends                     1569                       # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles                 95895764240                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi                             46.076742                       # CPI: cycles per instruction
system.cpu2.ipc                              0.021703                       # IPC: instructions per cycle
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.tickCycles                      269319044                       # Number of cycles that the object actually ticked
system.cpu2.idleCycles                     6390650720                       # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups               73106797                       # Number of BP lookups
system.cpu3.branchPred.condPredicted         49433479                       # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect          3258695                       # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups            49334876                       # Number of BTB lookups
system.cpu3.branchPred.BTBHits               35656978                       # Number of BTB hits
system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct            72.275398                       # BTB Hit Percentage
system.cpu3.branchPred.usedRAS                9555620                       # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect            104634                       # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.dtb.walker.walks                   494873                       # Table walker walks requested
system.cpu3.dtb.walker.walksLong               494873                       # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8038                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        49628                       # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore       307549                       # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples       187324                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean  2356.267750                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 14281.156299                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535       186079     99.34%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071          697      0.37%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607          387      0.21%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143           69      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679           51      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215           11      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751           12      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287           14      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total       187324                       # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples       229131                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 22686.146789                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18317.810397                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 18596.429018                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535       224486     97.97%     97.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071         3513      1.53%     99.51% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607          846      0.37%     99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143           43      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679          153      0.07%     99.96% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215           48      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287           12      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total       229131                       # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -24996742720                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean    -0.101724                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -25553833720    102.23%    102.23% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7    304691500     -1.22%    101.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11    107266500     -0.43%    100.58% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15     67844000     -0.27%    100.31% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19     24788500     -0.10%    100.21% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23     14749500     -0.06%    100.15% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27     13689000     -0.05%    100.10% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31     19439000     -0.08%    100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35      4284000     -0.02%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39       178500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43        52500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47       105500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51         2500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -24996742720                       # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K        49628     86.06%     86.06% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M         8038     13.94%    100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total        57666                       # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       494873                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       494873                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        57666                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        57666                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total       552539                       # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
system.cpu3.dtb.read_hits                    58275132                       # DTB read hits
system.cpu3.dtb.read_misses                    338945                       # DTB read misses
system.cpu3.dtb.write_hits                   45320334                       # DTB write hits
system.cpu3.dtb.write_misses                   155928                       # DTB write misses
system.cpu3.dtb.flush_tlb                        1185                       # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries                   30010                       # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults                       82                       # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults                  4724                       # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults                    33145                       # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses                58614077                       # DTB read accesses
system.cpu3.dtb.write_accesses               45476262                       # DTB write accesses
system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu3.dtb.hits                        103595466                       # DTB hits
system.cpu3.dtb.misses                         494873                       # DTB misses
system.cpu3.dtb.accesses                    104090339                       # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu3.itb.walker.walks                    60079                       # Table walker walks requested
system.cpu3.itb.walker.walksLong                60079                       # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2         1942                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3        41391                       # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore         8262                       # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples        51817                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean  1695.563232                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 10747.357060                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-65535        51612     99.60%     99.60% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-131071           80      0.15%     99.76% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-196607          107      0.21%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-262143           10      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-327679            7      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total        51817                       # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples        51595                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 29163.077818                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 24579.723425                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 21924.280551                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-32767        28123     54.51%     54.51% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-65535        22407     43.43%     97.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-98303          307      0.60%     98.53% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::98304-131071           32      0.06%     98.59% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-163839          434      0.84%     99.43% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::163840-196607          175      0.34%     99.77% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-229375           23      0.04%     99.82% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::229376-262143           26      0.05%     99.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-294911           39      0.08%     99.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::294912-327679           12      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-360447            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-425983            9      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total        51595                       # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -33589148812                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean     1.086684                       # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0     2957203824     -8.80%     -8.80% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1   -36586535136    108.92%    100.12% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2       35384500     -0.11%    100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3        4248500     -0.01%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4         527000     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5          22500     -0.00%    100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -33589148812                       # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K        41391     95.52%     95.52% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M         1942      4.48%    100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total        43333                       # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        60079                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total        60079                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        43333                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total        43333                       # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total       103412                       # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits                    52677682                       # ITB inst hits
system.cpu3.itb.inst_misses                     60079                       # ITB inst misses
system.cpu3.itb.read_hits                           0                       # DTB read hits
system.cpu3.itb.read_misses                         0                       # DTB read misses
system.cpu3.itb.write_hits                          0                       # DTB write hits
system.cpu3.itb.write_misses                        0                       # DTB write misses
system.cpu3.itb.flush_tlb                        1185                       # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid              11379                       # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid                    309                       # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries                   23578                       # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults                   114813                       # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses                       0                       # DTB read accesses
system.cpu3.itb.write_accesses                      0                       # DTB write accesses
system.cpu3.itb.inst_accesses                52737761                       # ITB inst accesses
system.cpu3.itb.hits                         52677682                       # DTB hits
system.cpu3.itb.misses                          60079                       # DTB misses
system.cpu3.itb.accesses                     52737761                       # DTB accesses
system.cpu3.numCycles                       367538464                       # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles         137661230                       # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts                     325116146                       # Number of instructions fetch has processed
system.cpu3.fetch.Branches                   73106797                       # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches          45212598                       # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles                    207107906                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles                7385298                       # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles                   1491112                       # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles                7917                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles             2707                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles      2935817                       # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles        92613                       # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles         5851                       # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines                 52545073                       # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes              2005603                       # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes                  24026                       # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples         352997650                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean             1.078283                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev            2.326168                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0               272813729     77.28%     77.28% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1                10027908      2.84%     80.13% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2                10164479      2.88%     83.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3                 7468497      2.12%     85.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4                15406630      4.36%     89.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5                 5031910      1.43%     90.91% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6                 5399943      1.53%     92.44% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7                 4793152      1.36%     93.80% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8                21891402      6.20%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total           352997650                       # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate                 0.198909                       # Number of branch fetches per cycle
system.cpu3.fetch.rate                       0.884577                       # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles               112522162                       # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles            171201406                       # Number of cycles decode is blocked
system.cpu3.decode.RunCycles                 59221662                       # Number of cycles decode is running
system.cpu3.decode.UnblockCycles              7151544                       # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles               2899090                       # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved            10994019                       # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred               804734                       # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts             355281721                       # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts              2474096                       # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles               2899090                       # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles               116622448                       # Number of cycles rename is idle
system.cpu3.rename.BlockCycles               14081573                       # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles     135939902                       # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles                 62181324                       # Number of cycles rename is running
system.cpu3.rename.UnblockCycles             21271328                       # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts             346993975                       # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents                66296                       # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents               1234254                       # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents                930282                       # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents              10943562                       # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents            2087                       # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands          331516858                       # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups            531452942                       # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups       410096361                       # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups           485069                       # Number of floating rename lookups
system.cpu3.rename.CommittedMaps            278766720                       # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps                52750133                       # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts           7968822                       # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts       6860328                       # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts                 39681669                       # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads            56098818                       # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores           47638464                       # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads          7335407                       # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores         7944863                       # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded                 329650835                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded            7964776                       # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued                329496224                       # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued           469719                       # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined       44173010                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined     28338373                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved        197137                       # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples    352997650                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean        0.933423                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev       1.659576                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0          224922038     63.72%     63.72% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1           52868564     14.98%     78.69% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2           24171570      6.85%     85.54% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3           17197419      4.87%     90.41% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4           12806059      3.63%     94.04% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5            9032778      2.56%     96.60% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6            6064654      1.72%     98.32% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7            3560331      1.01%     99.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8            2374237      0.67%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total      352997650                       # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu                1654999     25.37%     25.37% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult                 15899      0.24%     25.61% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv                   1445      0.02%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult                   0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift                   0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     25.63% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead               2663997     40.83%     66.46% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite              2188300     33.54%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass               19      0.00%      0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu            223294743     67.77%     67.77% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult              773232      0.23%     68.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv                39732      0.01%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc         41118      0.01%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead            59435929     18.04%     86.07% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite           45911451     13.93%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total             329496224                       # Type of FU issued
system.cpu3.iq.rate                          0.896495                       # Inst issue rate
system.cpu3.iq.fu_busy_cnt                    6524640                       # FU busy when requested
system.cpu3.iq.fu_busy_rate                  0.019802                       # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads        1018336747                       # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes        381842202                       # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses    317599035                       # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads             647710                       # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes            321899                       # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses       289386                       # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses             335674602                       # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses                 346243                       # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads         2638413                       # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads      8879523                       # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses        11866                       # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation       381459                       # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores      4873286                       # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads      2106312                       # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked      4209032                       # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles               2899090                       # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles                8833562                       # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles              4011376                       # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts          337691030                       # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts           991613                       # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts             56098818                       # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts            47638464                       # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts           6709459                       # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents                120203                       # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents              3844571                       # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents        381459                       # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect       1469292                       # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect      1295892                       # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts             2765184                       # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts            325759751                       # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts             58266124                       # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts          3247625                       # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
system.cpu3.iew.exec_nop                        75419                       # number of nop insts executed
system.cpu3.iew.exec_refs                   103584875                       # number of memory reference insts executed
system.cpu3.iew.exec_branches                60432321                       # Number of branches executed
system.cpu3.iew.exec_stores                  45318751                       # Number of stores executed
system.cpu3.iew.exec_rate                    0.886328                       # Inst execution rate
system.cpu3.iew.wb_sent                     318561323                       # cumulative count of insts sent to commit
system.cpu3.iew.wb_count                    317888421                       # cumulative count of insts written-back
system.cpu3.iew.wb_producers                157110188                       # num instructions producing a value
system.cpu3.iew.wb_consumers                272714221                       # num instructions consuming a value
system.cpu3.iew.wb_rate                      0.864912                       # insts written-back per cycle
system.cpu3.iew.wb_fanout                    0.576098                       # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts       44200110                       # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls        7767639                       # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts          2464984                       # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples    345475072                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean     0.849389                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev     1.847862                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0    238897207     69.15%     69.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1     51619563     14.94%     84.09% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2     18609130      5.39%     89.48% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3      8398025      2.43%     91.91% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4      6043748      1.75%     93.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5      3655661      1.06%     94.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6      3455010      1.00%     95.72% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7      2146483      0.62%     96.34% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8     12650245      3.66%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total    345475072                       # Number of insts commited each cycle
system.cpu3.commit.committedInsts           249760952                       # Number of instructions committed
system.cpu3.commit.committedOps             293442596                       # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu3.commit.refs                      89984472                       # Number of memory references committed
system.cpu3.commit.loads                     47219294                       # Number of loads committed
system.cpu3.commit.membars                    1969895                       # Number of memory barriers committed
system.cpu3.commit.branches                  55759591                       # Number of branches committed
system.cpu3.commit.fp_insts                    278553                       # Number of committed floating point instructions.
system.cpu3.commit.int_insts                269644169                       # Number of committed integer instructions.
system.cpu3.commit.function_calls             7403511                       # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu       202786729     69.11%     69.11% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult         605783      0.21%     69.31% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv           30019      0.01%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc        35593      0.01%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead       47219294     16.09%     85.43% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite      42765178     14.57%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total        293442596                       # Class of committed instruction
system.cpu3.commit.bw_lim_events             12650245                       # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads                   668392773                       # The number of ROB reads
system.cpu3.rob.rob_writes                  682819370                       # The number of ROB writes
system.cpu3.timesIdled                        2353613                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles                       14540814                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles                 98630935405                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts                  249760952                       # Number of Instructions Simulated
system.cpu3.committedOps                    293442596                       # Number of Ops (including micro ops) Simulated
system.cpu3.cpi                              1.471561                       # CPI: Cycles Per Instruction
system.cpu3.cpi_total                        1.471561                       # CPI: Total CPI of All Threads
system.cpu3.ipc                              0.679551                       # IPC: Instructions Per Cycle
system.cpu3.ipc_total                        0.679551                       # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads               384013216                       # number of integer regfile reads
system.cpu3.int_regfile_writes              227255326                       # number of integer regfile writes
system.cpu3.fp_regfile_reads                   562445                       # number of floating regfile reads
system.cpu3.fp_regfile_writes                  347476                       # number of floating regfile writes
system.cpu3.cc_regfile_reads                 69354543                       # number of cc regfile reads
system.cpu3.cc_regfile_writes                70004499                       # number of cc regfile writes
system.cpu3.misc_regfile_reads              654418825                       # number of misc regfile reads
system.cpu3.misc_regfile_writes               7814462                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40238                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40238                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136511                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136511                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47686                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29444                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122464                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353498                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47706                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155640                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7491974                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             34324500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                5500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            13360500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              141000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            21520500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               46500                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           257733143                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30500                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            59729000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            75398000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115459                       # number of replacements
system.iocache.tags.tagsinuse               10.420601                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13089166487009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.547306                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.873295                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221707                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429581                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651288                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide   1078707234                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1078707234                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   6251807909                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6251807909                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide   1078707234                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1078707234                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide   1078707234                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1078707234                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 122399.549983                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 121887.823051                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58612.164451                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58612.164451                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 122399.549983                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 121846.519146                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 122399.549983                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 121846.519146                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         22659                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 2381                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.516590                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide         5719                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         5719                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        48024                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        48024                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide         5719                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         5719                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide         5719                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         5719                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide    792757234                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    792757234                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   3850607909                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3850607909                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide    792757234                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    792757234                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide    792757234                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    792757234                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.646215                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.450236                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.450236                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.645996                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.648928                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.645996                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138618.155971                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138618.155971                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80180.907650                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80180.907650                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 138618.155971                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 138618.155971                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 138618.155971                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 138618.155971                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1137204                       # number of replacements
system.l2c.tags.tagsinuse                65362.357170                       # Cycle average of tags in use
system.l2c.tags.total_refs                   47194222                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1199974                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    39.329370                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                395986000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   36812.759669                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   141.825850                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   212.294111                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3568.454051                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     8068.997871                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    31.153423                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker    51.715903                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst      455.445147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     2127.472553                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    35.646762                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker    56.154607                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     1628.641788                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     3512.634896                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker    79.313177                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker   110.411472                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst     2677.526600                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data     5791.909290                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.561718                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002164                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003239                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.054450                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.123123                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000475                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.000789                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.006950                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.032463                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000544                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker     0.000857                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.024851                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.053599                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker     0.001210                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker     0.001685                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst       0.040856                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data       0.088378                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997350                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          293                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62477                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          292                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          518                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2805                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5156                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53863                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004471                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.953323                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                417655510                       # Number of tag accesses
system.l2c.tags.data_accesses               417655510                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       156912                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       107943                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker        56684                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker        42472                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker       148559                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker        56956                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker       285459                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker       108502                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 963487                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7475106                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7475106                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     15694537                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        15694537                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            3845                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            1239                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data            1481                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data            2703                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9268                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           645063                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           195358                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data           266475                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data           473467                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1580363                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       5559632                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       1679149                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst       3811910                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst       4554395                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15605086                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      2491204                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       797943                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data      1047469                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data      1865288                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6201904                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       292089                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data        91619                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data       123637                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data       226607                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           733952                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        156912                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        107943                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             5559632                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3136267                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         56684                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker         42472                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             1679149                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              993301                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker        148559                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker         56956                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst             3811910                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data             1313944                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker        285459                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker        108502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst             4554395                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data             2338755                       # number of demand (read+write) hits
system.l2c.demand_hits::total                24350840                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       156912                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       107943                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            5559632                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3136267                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        56684                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker        42472                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            1679149                       # number of overall hits
system.l2c.overall_hits::cpu1.data             993301                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker       148559                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker        56956                       # number of overall hits
system.l2c.overall_hits::cpu2.inst            3811910                       # number of overall hits
system.l2c.overall_hits::cpu2.data            1313944                       # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker       285459                       # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker       108502                       # number of overall hits
system.l2c.overall_hits::cpu3.inst            4554395                       # number of overall hits
system.l2c.overall_hits::cpu3.data            2338755                       # number of overall hits
system.l2c.overall_hits::total               24350840                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1258                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1334                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          366                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker          326                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker          383                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker          343                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker         1015                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker          932                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 5957                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         13982                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          4480                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          5760                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data          9480                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             33702                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         182732                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          45205                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          62745                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data          97688                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             388370                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        36075                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         7162                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst        22464                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst        26607                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           92308                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       109127                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data        27274                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data        38813                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data        79028                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         254242                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       395489                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data        19003                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data        26418                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data        48676                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         489586                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1258                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1334                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             36075                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            291859                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          366                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker          326                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              7162                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             72479                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker          383                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker          343                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst             22464                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data            101558                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker         1015                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker          932                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst             26607                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data            176716                       # number of demand (read+write) misses
system.l2c.demand_misses::total                740877                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1258                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1334                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            36075                       # number of overall misses
system.l2c.overall_misses::cpu0.data           291859                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          366                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker          326                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             7162                       # number of overall misses
system.l2c.overall_misses::cpu1.data            72479                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker          383                       # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker          343                       # number of overall misses
system.l2c.overall_misses::cpu2.inst            22464                       # number of overall misses
system.l2c.overall_misses::cpu2.data           101558                       # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker         1015                       # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker          932                       # number of overall misses
system.l2c.overall_misses::cpu3.inst            26607                       # number of overall misses
system.l2c.overall_misses::cpu3.data           176716                       # number of overall misses
system.l2c.overall_misses::total               740877                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     49999000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker     45195500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     52180000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker     47605000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    140767500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker    128228000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      463975000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    184736500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data    246532500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data    410199500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    841468500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5917060500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   8310740500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data  14350940000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  28578741000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    942461000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst   3002415000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst   3613737999                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   7558613999                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data   3626924000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data   5243614000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data  11147248500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  20017786500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data   2479377500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data   3669438500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data   7575573000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  13724389000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker     49999000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker     45195500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    942461000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   9543984500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker     52180000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker     47605000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst   3002415000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data  13554354500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker    140767500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker    128228000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst   3613737999                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data  25498188500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     56619116499                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker     49999000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker     45195500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    942461000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   9543984500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker     52180000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker     47605000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst   3002415000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data  13554354500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker    140767500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker    128228000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst   3613737999                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data  25498188500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    56619116499                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       158170                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       109277                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker        57050                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker        42798                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker       148942                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker        57299                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker       286474                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker       109434                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             969444                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7475106                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7475106                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     15694537                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     15694537                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        17827                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         5719                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         7241                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data        12183                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           42970                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       827795                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       240563                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       329220                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data       571155                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1968733                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      5595707                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      1686311                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst      3834374                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst      4581002                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15697394                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      2600331                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       825217                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data      1086282                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data      1944316                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6456146                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       687578                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       110622                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data       150055                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data       275283                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1223538                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       158170                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       109277                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         5595707                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         3428126                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        57050                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker        42798                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         1686311                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1065780                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker       148942                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker        57299                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst         3834374                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data         1415502                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker       286474                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.itb.walker       109434                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst         4581002                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data         2515471                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            25091717                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       158170                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       109277                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        5595707                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        3428126                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        57050                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker        42798                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        1686311                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1065780                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker       148942                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker        57299                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst        3834374                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data        1415502                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.dtb.walker       286474                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.itb.walker       109434                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst        4581002                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data        2515471                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           25091717                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006145                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784316                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783354                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.795470                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data     0.778133                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.784315                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.220745                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.187913                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.190587                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data     0.171036                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.197269                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006447                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004247                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.005859                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005808                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005880                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041967                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.033051                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.035730                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.040646                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.039380                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.575191                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.171783                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data     0.176055                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data     0.176822                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.400140                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.085137                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.004247                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.068006                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.005859                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.071747                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst       0.005808                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data       0.070252                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.029527                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007953                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012208                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.085137                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006415                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.007617                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.004247                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.068006                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.002571                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker     0.005986                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.005859                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.071747                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker     0.003543                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker     0.008517                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst      0.005808                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data      0.070252                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.029527                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 77887.359409                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41235.825893                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 42800.781250                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 43269.989451                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 24967.909916                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130893.938724                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132452.633676                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 146905.863566                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73586.376394                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131591.873778                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133654.513889                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 135819.070132                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81884.712040                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132981.007553                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135099.425450                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141054.417422                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 78735.167675                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130472.951639                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 138899.178590                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155632.611554                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 28032.641865                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 76421.749493                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136609.289617                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138636.503067                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131591.873778                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131679.307110                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 136240.208877                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 138790.087464                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 133654.513889                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 133464.173182                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 138687.192118                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137583.690987                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 135819.070132                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 144289.076824                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 76421.749493                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              947584                       # number of writebacks
system.l2c.writebacks::total                   947584                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data            1                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data              4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.dtb.walker            2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data             4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.dtb.walker            2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          366                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          326                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          383                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          343                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1013                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker          921                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            3352                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         4480                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         5760                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data         9480                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        19720                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        45205                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        62745                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data        97688                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        205638                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         7162                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        22464                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        26606                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        56232                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data        27274                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data        38809                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data        79027                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       145110                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data        19003                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data        26418                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data        48676                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total        94097                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          366                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker          326                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         7162                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        72479                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker          383                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker          343                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst        22464                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data       101554                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker         1013                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker          921                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst        26606                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data       176715                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           410332                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          366                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker          326                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         7162                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        72479                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker          383                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker          343                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst        22464                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data       101554                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker         1013                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker          921                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst        26606                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data       176715                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          410332                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         6832                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         6962                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data         7151                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        20945                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         6305                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         6510                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data         6865                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        19680                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        13137                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data        13472                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data        14016                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        40625                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     41935500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     48350000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker    130376500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    428779000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    316657000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data    407624000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data    670775000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1395056000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        72000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        72000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5465010500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   7683290500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  13374060000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  26522361000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    870841000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   2777775000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   3347666499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   6996282499                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   3354184000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   4855123000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data  10356862500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  18566169500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2289347500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data   3405258500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   7088813000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  12783419000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     41935500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    870841000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   8819194500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     48350000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst   2777775000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data  12538413500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker    130376500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst   3347666499                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data  23730922500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  52513591999                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     46339000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     41935500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    870841000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   8819194500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     48350000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     44175000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst   2777775000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data  12538413500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker    130376500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker    117603000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst   3347666499                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data  23730922500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  52513591999                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   1264338500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1284734500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data   1277563000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3826636000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   1209386500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1243481500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data   1260805498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   3713673498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2473725000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2528216000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data   2538368498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7540309498                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.003458                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783354                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.795470                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.778133                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.458925                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.187913                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.190587                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.171036                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.104452                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003582                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.033051                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.035726                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.040645                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.022476                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.171783                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.176055                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.176822                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.076906                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.016353                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006415                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007617                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004247                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.068006                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.002571                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.005986                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.005859                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.071744                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.003536                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.008416                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005808                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data     0.070251                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.016353                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127917.362768                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.366071                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70768.055556                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70756.856540                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70743.204868                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        72000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        72000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120893.938724                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122452.633676                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136905.863566                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 128975.972340                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124418.169352                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122981.007553                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125103.017341                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131054.734458                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127945.486183                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120472.951639                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 128899.178590                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145632.611554                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135853.629765                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121591.873778                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121679.307110                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123654.513889                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123465.481419                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125823.742727                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134289.236907                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 127978.300496                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185061.255855                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184535.262856                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178655.153125                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182699.259967                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191813.877875                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191010.983103                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183657.028114                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188702.921646                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188302.123773                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187664.489311                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 181105.058362                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 185607.618412                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76702                       # Transaction distribution
system.membus.trans_dist::ReadResp             438040                       # Transaction distribution
system.membus.trans_dist::WriteReq              33616                       # Transaction distribution
system.membus.trans_dist::WriteResp             33616                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1054215                       # Transaction distribution
system.membus.trans_dist::CleanEvict           195061                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34374                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           34376                       # Transaction distribution
system.membus.trans_dist::ReadExReq            877287                       # Transaction distribution
system.membus.trans_dist::ReadExResp           877287                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        361338                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122464                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           61                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6736                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3755613                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3884874                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342734                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342734                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4227608                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155640                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          196                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    139526112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    139695420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7304128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7304128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               146999548                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1634                       # Total snoops (count)
system.membus.snoop_fanout::samples           2741682                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2741682    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2741682                       # Request fanout histogram
system.membus.reqLayer0.occupancy            69473500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             1838002                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          2993221129                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2766254947                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          111131085                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     51354926                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     26009056                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         2855                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2048                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2048                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            1478127                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          23632068                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33616                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33616                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      7917832                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     15694537                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2278182                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           42970                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          42972                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1968733                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1968733                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15697459                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6461865                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1271562                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1223538                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47175640                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29164933                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       814493                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1705007                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              78860073                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2009256084                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1017810408                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2934600                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6010000                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3036011092                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1652274                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         37979201                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.016509                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.127422                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               37352210     98.35%     98.35% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 626991      1.65%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           37979201                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        30549015491                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           656694                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       15157992691                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        7808308250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         290510210                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         695723441                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------