path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.289289                       # Number of seconds simulated
sim_ticks                                51289289109000                       # Number of ticks simulated
final_tick                               51289289109000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 116964                       # Simulator instruction rate (inst/s)
host_op_rate                                   137448                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6754182467                       # Simulator tick rate (ticks/s)
host_mem_usage                                 688124                       # Number of bytes of host memory used
host_seconds                                  7593.71                       # Real time elapsed on the host
sim_insts                                   888194021                       # Number of instructions simulated
sim_ops                                    1043742869                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       151872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       139200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4024896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         41634016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       137024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       129408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3236928                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         42391336                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        430592                       # Number of bytes read from this memory
system.physmem.bytes_read::total             92275272                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4024896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3236928                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7261824                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78300352                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78320932                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2373                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2175                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             62889                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            650540                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2141                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2022                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             50577                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            662369                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6728                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1441814                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1223443                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1226016                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2961                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2714                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               78474                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              811749                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2672                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2523                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               63111                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              826514                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8395                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1799114                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          78474                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          63111                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             141586                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1526641                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1527043                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1526641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2961                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2714                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              78474                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             811749                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2672                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2523                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              63111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             826916                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8395                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3326157                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1441814                       # Number of read requests accepted
system.physmem.writeReqs                      1226016                       # Number of write requests accepted
system.physmem.readBursts                     1441814                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1226016                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 92235136                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     40960                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78321024                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  92275272                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78320932                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      640                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         143274                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               85394                       # Per bank write bursts
system.physmem.perBankRdBursts::1               90340                       # Per bank write bursts
system.physmem.perBankRdBursts::2               85251                       # Per bank write bursts
system.physmem.perBankRdBursts::3               84742                       # Per bank write bursts
system.physmem.perBankRdBursts::4               87352                       # Per bank write bursts
system.physmem.perBankRdBursts::5               95958                       # Per bank write bursts
system.physmem.perBankRdBursts::6               87724                       # Per bank write bursts
system.physmem.perBankRdBursts::7               87120                       # Per bank write bursts
system.physmem.perBankRdBursts::8               85128                       # Per bank write bursts
system.physmem.perBankRdBursts::9              115032                       # Per bank write bursts
system.physmem.perBankRdBursts::10              93810                       # Per bank write bursts
system.physmem.perBankRdBursts::11              94841                       # Per bank write bursts
system.physmem.perBankRdBursts::12              83101                       # Per bank write bursts
system.physmem.perBankRdBursts::13              88197                       # Per bank write bursts
system.physmem.perBankRdBursts::14              87648                       # Per bank write bursts
system.physmem.perBankRdBursts::15              89536                       # Per bank write bursts
system.physmem.perBankWrBursts::0               72684                       # Per bank write bursts
system.physmem.perBankWrBursts::1               76025                       # Per bank write bursts
system.physmem.perBankWrBursts::2               73393                       # Per bank write bursts
system.physmem.perBankWrBursts::3               74816                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75820                       # Per bank write bursts
system.physmem.perBankWrBursts::5               81492                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75165                       # Per bank write bursts
system.physmem.perBankWrBursts::7               76353                       # Per bank write bursts
system.physmem.perBankWrBursts::8               74241                       # Per bank write bursts
system.physmem.perBankWrBursts::9               82215                       # Per bank write bursts
system.physmem.perBankWrBursts::10              79031                       # Per bank write bursts
system.physmem.perBankWrBursts::11              79534                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72343                       # Per bank write bursts
system.physmem.perBankWrBursts::13              77292                       # Per bank write bursts
system.physmem.perBankWrBursts::14              76022                       # Per bank write bursts
system.physmem.perBankWrBursts::15              77340                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          16                       # Number of times write queue was full causing retry
system.physmem.totGap                    51289287954000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1441799                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1223443                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    661868                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    399209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    215391                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    158760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       607                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       570                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1170                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       794                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      404                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      203                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      141                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       774                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       763                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    15614                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    29719                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43542                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    73432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    74626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    75089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    77965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    77408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    77909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    84552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    79510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    90590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    97976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    76224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    79969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    72166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      553                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      418                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      397                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      260                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       562786                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      303.056181                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.751782                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     331.834003                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         224740     39.93%     39.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       128751     22.88%     62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        55127      9.80%     72.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26773      4.76%     77.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23233      4.13%     81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12910      2.29%     83.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13583      2.41%     86.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9009      1.60%     87.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        68660     12.20%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         562786                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         70105                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.557036                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      230.792990                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          70100     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           70105                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         70105                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.456187                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.912950                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.915591                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                54      0.08%      0.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                21      0.03%      0.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               10      0.01%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              61      0.09%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           66123     94.32%     94.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1498      2.14%     96.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             202      0.29%     96.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             498      0.71%     97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              79      0.11%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             334      0.48%     98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             212      0.30%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              35      0.05%     98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              78      0.11%     98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             130      0.19%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              31      0.04%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              40      0.06%     99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             445      0.63%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              33      0.05%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              29      0.04%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             119      0.17%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              11      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            25      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           70105                       # Writes before turning the bus around for reads
system.physmem.totQLat                    42013541205                       # Total ticks spent queuing
system.physmem.totMemAccLat               69035553705                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7205870000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29152.30                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47902.30                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.22                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.35                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1183295                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    918857                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.11                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.08                       # Row buffer hit rate for writes
system.physmem.avgGap                     19225096.03                       # Average gap between requests
system.physmem.pageHitRate                      78.88                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2114615160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1153807875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5490264000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3925247040                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3349966598160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1237156507125                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29688344543250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34288151582610                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.524687                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49388977684769                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1712661860000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    187649331731                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2140047000                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1167684375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5750846400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4004756640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3349966598160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1240738244055                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29685202677000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34288970853630                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.540660                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49383704909692                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1712661860000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    192921720308                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1024                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2148                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst         1088                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1024                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           17                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              131510280                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         89076411                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5754624                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            89205696                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               64088886                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.843939                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17216191                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            189076                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   879879                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               879879                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16451                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88924                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       539694                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       340185                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2660.496495                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15843.329302                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       337511     99.21%     99.21% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1400      0.41%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          868      0.26%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          160      0.05%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679          148      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           35      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           25      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       340185                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       407005                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23314.236926                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18617.801732                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 20825.488249                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       397459     97.65%     97.65% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         7042      1.73%     99.38% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1712      0.42%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          113      0.03%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          415      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          146      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823           12      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       407005                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 376382023716                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.109107                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.663618                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 375374134216     99.73%     99.73% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    555470000      0.15%     99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    199772500      0.05%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    117350500      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     45444000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     24549500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     26272500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     32439000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      6175500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       322000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        41000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47        35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51        18000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 376382023716                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        88924     84.39%     84.39% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        16451     15.61%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       105375                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       879879                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       879879                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       105375                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       105375                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       985254                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   104450342                       # DTB read hits
system.cpu0.dtb.read_misses                    607388                       # DTB read misses
system.cpu0.dtb.write_hits                   80999803                       # DTB write hits
system.cpu0.dtb.write_misses                   272491                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1103                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21264                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    532                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   54933                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      199                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9612                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    55908                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               105057730                       # DTB read accesses
system.cpu0.dtb.write_accesses               81272294                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        185450145                       # DTB hits
system.cpu0.dtb.misses                         879879                       # DTB misses
system.cpu0.dtb.accesses                    186330024                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   105425                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               105425                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3033                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        71538                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14522                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        90903                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1916.366897                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 12628.127488                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        89834     98.82%     98.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          539      0.59%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303           99      0.11%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          130      0.14%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839          200      0.22%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           51      0.06%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375           18      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        90903                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        89093                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29737.628096                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24673.282560                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 24049.122605                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        86936     97.58%     97.58% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          600      0.67%     98.25% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1294      1.45%     99.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           93      0.10%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679          133      0.15%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           25      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        89093                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 303340156184                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.819271                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -248434536268    -81.90%    -81.90% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   551700406452    181.88%     99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       66884500      0.02%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        6271500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         916000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          53500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6         160500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 303340156184                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        71538     95.93%     95.93% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         3033      4.07%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        74571                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       105425                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       105425                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        74571                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        74571                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       179996                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    94464352                       # ITB inst hits
system.cpu0.itb.inst_misses                    105425                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1103                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21264                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    532                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   41067                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   204534                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                94569777                       # ITB inst accesses
system.cpu0.itb.hits                         94464352                       # DTB hits
system.cpu0.itb.misses                         105425                       # DTB misses
system.cpu0.itb.accesses                     94569777                       # DTB accesses
system.cpu0.numCycles                       693727147                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         245689923                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     583659918                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  131510280                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          81305077                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    403973689                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13146062                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2696063                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               24792                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             6132                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      5442737                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       182065                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         4382                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 94242396                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3550844                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  42244                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         664592540                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.028282                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.281038                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               520383096     78.30%     78.30% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                18093254      2.72%     81.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                18296207      2.75%     83.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13332643      2.01%     85.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                28010014      4.21%     90.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 9092439      1.37%     91.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9727305      1.46%     92.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8422108      1.27%     94.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                39235474      5.90%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           664592540                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.189571                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.841339                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               199631749                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            341256701                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                105213142                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13320667                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5167977                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19724467                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1425325                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             637042209                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4387868                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5167977                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               207139071                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               31235122                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     259336821                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                110889608                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             50821415                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             622130396                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               110301                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2210574                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1917918                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              31535075                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            3960                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          595274899                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            956990256                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       735490255                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           762145                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            501553477                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                93721422                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          14866567                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      12875390                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 74435077                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           100241817                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           85151630                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13697674                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14727627                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 590625310                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           14935431                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                591459977                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           828967                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       78563814                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     50313782                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        364460                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    664592540                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.889959                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.628761                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          433116455     65.17%     65.17% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           96939801     14.59%     79.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           43307418      6.52%     86.27% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           30869552      4.64%     90.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           22882943      3.44%     94.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           15965693      2.40%     96.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10866497      1.64%     98.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6415983      0.97%     99.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4228198      0.64%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      664592540                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                3016734     25.85%     25.85% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 25376      0.22%     26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2604      0.02%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               2      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     26.08% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4797053     41.10%     67.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3830581     32.82%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass                4      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            401312314     67.85%     67.85% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1456904      0.25%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                65858      0.01%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                165      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   1      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               4      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         60568      0.01%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           106521284     18.01%     86.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           82042825     13.87%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             591459977                       # Type of FU issued
system.cpu0.iq.rate                          0.852583                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11672350                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019735                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1858987169                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        684321714                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    570020326                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1026642                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            511393                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       456189                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             602584344                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 547979                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4688231                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     15870823                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        20812                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       719682                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      8709865                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3916695                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      7873559                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5167977                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               16609605                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles             12703167                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          605694561                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1733726                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            100241817                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            85151630                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          12585145                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                227737                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents             12390007                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        719682                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2598504                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2279450                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4877954                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            584896168                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            104440997                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5696378                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       133820                       # number of nop insts executed
system.cpu0.iew.exec_refs                   185440040                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               108756194                       # Number of branches executed
system.cpu0.iew.exec_stores                  80999043                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.843121                       # Inst execution rate
system.cpu0.iew.wb_sent                     571697028                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    570476515                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                281622326                       # num instructions producing a value
system.cpu0.iew.wb_consumers                489116164                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.822336                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.575778                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       78604829                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       14570971                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4349296                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    651171717                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.809306                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.808418                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    458185820     70.36%     70.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     94765025     14.55%     84.92% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     33137681      5.09%     90.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     15077927      2.32%     92.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10931676      1.68%     94.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6537456      1.00%     95.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6054601      0.93%     95.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3871079      0.59%     96.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22610452      3.47%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    651171717                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           448537783                       # Number of instructions committed
system.cpu0.commit.committedOps             526996927                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     160812759                       # Number of memory references committed
system.cpu0.commit.loads                     84370994                       # Number of loads committed
system.cpu0.commit.membars                    3712862                       # Number of memory barriers committed
system.cpu0.commit.branches                 100457713                       # Number of branches committed
system.cpu0.commit.fp_insts                    437537                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                483805259                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13348009                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       364956602     69.25%     69.25% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1127311      0.21%     69.47% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           49300      0.01%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            8      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp           13      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt           21      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        50913      0.01%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       84370994     16.01%     85.49% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      76441765     14.51%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        526996927                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22610452                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1230217301                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1224645571                       # The number of ROB writes
system.cpu0.timesIdled                        4130146                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       29134607                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 48521219733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  448537783                       # Number of Instructions Simulated
system.cpu0.committedOps                    526996927                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.546641                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.546641                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.646562                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.646562                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               689663562                       # number of integer regfile reads
system.cpu0.int_regfile_writes              407539482                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   822896                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  494260                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                125263725                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               126423537                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1208432146                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              14685746                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10442064                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.972968                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          299912904                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10442576                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.720203                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   306.410459                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   205.562509                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.598458                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.401489                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           23                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1323031608                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1323031608                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80041652                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     78145564                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      158187216                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     67282411                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     66174015                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     133456426                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       208357                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       193759                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       402116                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       179575                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       144785                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       324360                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1768308                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1713443                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3481751                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2038321                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1974130                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4012451                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    147324063                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    144319579                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       291643642                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    147532420                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    144513338                       # number of overall hits
system.cpu0.dcache.overall_hits::total      292045758                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6276474                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6183597                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12460071                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6322158                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6339058                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12661216                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       639187                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       638043                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1277230                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       615392                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       622485                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1237877                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       328942                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       317586                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       646528                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           14                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     12598632                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     12522655                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      25121287                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     13237819                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     13160698                       # number of overall misses
system.cpu0.dcache.overall_misses::total     26398517                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112360682500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 108979382500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 221340065000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 275146028128                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 278942428574                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 554088456702                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  44475704107                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47058017442                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  91533721549                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4608102000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4295538500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   8903640500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       178500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       151500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       330000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 387506710628                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 387921811074                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 775428521702                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 387506710628                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 387921811074                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 775428521702                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     86318126                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     84329161                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    170647287                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73604569                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     72513073                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146117642                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       847544                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       831802                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1679346                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       794967                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       767270                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1562237                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2097250                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2031029                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4128279                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2038329                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1974136                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4012465                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    159922695                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    156842234                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    316764929                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    160770239                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    157674036                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    318444275                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.072713                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.073327                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.073017                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.085894                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.087420                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.086651                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754164                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.767061                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760552                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.774110                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.811298                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792375                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.156844                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.156367                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156610                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.078780                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079842                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.079306                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.082340                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.083468                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.082898                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17901.879702                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17623.946467                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17763.948937                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43520.903484                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44003.766581                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43762.657292                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72272.151908                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 75597.030357                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73944.116862                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14008.858705                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13525.591493                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13771.469294                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22312.500000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        25250                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23571.428571                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30757.840266                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30977.601082                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30867.388351                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29272.700482                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29475.777886                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29373.942548                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     88168676                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       110752                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3495525                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1064                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.223300                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   104.090226                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8003050                       # number of writebacks
system.cpu0.dcache.writebacks::total          8003050                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3450278                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3389516                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6839794                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5251049                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5273458                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10524507                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3747                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3282                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         7029                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       203336                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       195633                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       398969                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8701327                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8662974                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17364301                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8701327                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8662974                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17364301                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2826196                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2794081                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5620277                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1071109                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1065600                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2136709                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       626536                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       626309                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1252845                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       611645                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       619203                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230848                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       125606                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121953                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       247559                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           14                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3897305                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3859681                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7756986                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4523841                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4485990                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      9009831                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16464                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17213                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33677                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15292                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18404                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31756                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35617                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67373                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49680928000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  48547045000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98227973000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  49497765698                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  49329695702                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  98827461400                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12314245500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12444174500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24758420000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  43627522607                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  46272791442                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89900314049                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1845699500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1727387000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3573086500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       170500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       145500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       316000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99178693698                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97876740702                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 197055434400                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111492939198                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110320915202                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 221813854400                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2819562500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3022126000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841688500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2713847000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3108432498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5822279498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5533409500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6130558498                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11663967998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032742                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033133                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032935                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014552                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014695                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014623                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.739237                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.752954                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746031                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.769397                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.807021                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787875                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059891                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060045                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059967                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024370                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024609                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024488                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028139                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028451                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028293                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17578.727024                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17374.959781                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17477.425579                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46211.698061                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46292.882603                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46252.185674                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19654.489926                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19869.065429                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19761.758238                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71328.176650                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74729.598277                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73039.330648                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14694.357754                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14164.366600                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14433.272472                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21312.500000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        24250                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22571.428571                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25448.019516                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25358.764287                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25403.608360                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24645.636130                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24592.323033                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24619.091568                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171256.225705                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175572.300006                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173462.259109                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177468.414857                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168899.831450                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172788.446641                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174247.685477                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172124.505096                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173125.257863                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         15993913                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921230                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          168728933                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15994425                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.549234                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      23717372500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   279.340793                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   232.580437                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.545587                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.454259                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        201947025                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       201947025                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     85474040                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     83254893                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      168728933                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     85474040                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     83254893                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       168728933                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     85474040                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     83254893                       # number of overall hits
system.cpu0.icache.overall_hits::total      168728933                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8755198                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8468352                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17223550                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8755198                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8468352                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17223550                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8755198                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8468352                       # number of overall misses
system.cpu0.icache.overall_misses::total     17223550                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 117852647827                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113231353367                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 231084001194                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 117852647827                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 113231353367                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 231084001194                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 117852647827                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 113231353367                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 231084001194                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     94229238                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     91723245                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    185952483                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     94229238                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     91723245                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    185952483                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     94229238                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     91723245                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    185952483                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.092914                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.092325                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092623                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.092914                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.092325                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092623                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.092914                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.092325                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092623                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13460.877507                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13371.120304                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.746327                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13460.877507                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13371.120304                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13416.746327                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13460.877507                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13371.120304                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13416.746327                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       127389                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             8523                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.946498                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       625847                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       603161                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1229008                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       625847                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       603161                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1229008                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       625847                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       603161                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1229008                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8129351                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      7865191                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     15994542                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      8129351                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      7865191                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     15994542                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      8129351                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      7865191                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     15994542                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103957984374                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  99931045411                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 203889029785                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103957984374                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  99931045411                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 203889029785                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103957984374                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  99931045411                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 203889029785                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675462000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960778000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636240000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675462000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960778000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636240000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086014                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.086014                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086272                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085749                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.086014                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12747.412823                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12747.412823                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12787.980784                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12705.482348                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12747.412823                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups              128002334                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         87000769                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5591841                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            87469952                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               62728816                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            71.714703                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16690428                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            184044                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   888625                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               888625                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16515                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89516                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       551182                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       337443                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2618.907490                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15834.815336                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       334927     99.25%     99.25% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1259      0.37%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          844      0.25%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          153      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679          151      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           37      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       337443                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       414261                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23202.362762                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18749.985984                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 19280.784036                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       405371     97.85%     97.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6574      1.59%     99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1705      0.41%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           91      0.02%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          347      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          109      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           45      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       414261                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 346681338644                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.164180                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.727467                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 345667955144     99.71%     99.71% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    547148000      0.16%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    197378500      0.06%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    124829500      0.04%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     46718000      0.01%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     26902000      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     29536000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     34566500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      5689000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       518500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43        43000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47        27500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51        26500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55          500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 346681338644                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        89517     84.42%     84.42% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        16515     15.58%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       106032                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       888625                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       888625                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       106032                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       106032                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       994657                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   102078491                       # DTB read hits
system.cpu1.dtb.read_misses                    609526                       # DTB read misses
system.cpu1.dtb.write_hits                   79752942                       # DTB write hits
system.cpu1.dtb.write_misses                   279099                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1097                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21138                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    525                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   54374                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      189                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  9195                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    57003                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               102688017                       # DTB read accesses
system.cpu1.dtb.write_accesses               80032041                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        181831433                       # DTB hits
system.cpu1.dtb.misses                         888625                       # DTB misses
system.cpu1.dtb.accesses                    182720058                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   103286                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               103286                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2985                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        70650                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        14185                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        89101                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1880.887981                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 12259.575091                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        88607     99.45%     99.45% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          208      0.23%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607          245      0.27%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           23      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679            9      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        89101                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        87820                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29448.206559                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24574.367788                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23374.084602                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        85760     97.65%     97.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          575      0.65%     98.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1268      1.44%     99.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           74      0.08%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          108      0.12%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           17      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           15      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        87820                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 303729046684                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     1.808269                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0   -245416179168    -80.80%    -80.80% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   549075630852    180.78%     99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       61607500      0.02%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        7072500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         899500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          15500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 303729046684                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        70650     95.95%     95.95% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         2985      4.05%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        73635                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       103286                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       103286                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        73635                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        73635                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       176921                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    91956391                       # ITB inst hits
system.cpu1.itb.inst_misses                    103286                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1097                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21138                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    525                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   40049                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   202974                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                92059677                       # ITB inst accesses
system.cpu1.itb.hits                         91956391                       # DTB hits
system.cpu1.itb.misses                         103286                       # DTB misses
system.cpu1.itb.accesses                     92059677                       # DTB accesses
system.cpu1.numCycles                       683589124                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         238009169                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     571176057                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  128002334                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          79419244                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    404719127                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               12774600                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2616585                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               24222                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             5589                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      5368087                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       160870                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         2610                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 91730802                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3443412                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  41301                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         657293286                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.017856                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.272002                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               516237120     78.54%     78.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                17632958      2.68%     81.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                17654036      2.69%     83.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13091323      1.99%     85.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                27900711      4.24%     90.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 8639588      1.31%     91.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9467175      1.44%     92.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8151646      1.24%     94.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                38518729      5.86%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           657293286                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.187250                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.835555                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               193664291                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            342800105                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                102542010                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13254966                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5029491                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            18937376                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1377136                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             623890493                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4237673                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5029491                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               201058836                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31048942                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     259190035                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                108261392                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             52701935                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             609359225                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents               108791                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               2049420                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1849812                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              33430397                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3628                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          583294874                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            940667365                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       720819975                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           791427                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            492359028                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                90935841                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          15032233                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      13124059                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 74465076                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            97949385                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           83816258                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13144575                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14065563                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 578164482                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15125943                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                579632592                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           823862                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       76544478                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     48922532                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        353577                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    657293286                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.881848                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.622601                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          429426254     65.33%     65.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           96715112     14.71%     80.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           42097823      6.40%     86.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           29977053      4.56%     91.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           22357761      3.40%     94.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           15606240      2.37%     96.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10657458      1.62%     98.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6260997      0.95%     99.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4194588      0.64%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      657293286                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2920465     25.31%     25.31% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 23164      0.20%     25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   2858      0.02%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4710924     40.83%     66.37% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3880904     33.63%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            393199833     67.84%     67.84% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1396367      0.24%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                66291      0.01%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                 69      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         68890      0.01%     68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           104108183     17.96%     86.06% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           80792947     13.94%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             579632592                       # Type of FU issued
system.cpu1.iq.rate                          0.847925                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11538316                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019906                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1827853747                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        669983955                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    558625373                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1066901                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            527037                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       476493                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             590600685                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 570212                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4591636                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     15509069                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        19434                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       687053                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      8553480                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3778771                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      7833875                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5029491                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               16246993                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             12738129                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          593422501                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1696916                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             97949385                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            83816258                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12835084                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                232041                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents             12419302                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        687053                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2537334                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2208748                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4746082                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            573207937                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            102068127                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5548487                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       132076                       # number of nop insts executed
system.cpu1.iew.exec_refs                   181824390                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               105934255                       # Number of branches executed
system.cpu1.iew.exec_stores                  79756263                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.838527                       # Inst execution rate
system.cpu1.iew.wb_sent                     560287134                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    559101866                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                276158020                       # num instructions producing a value
system.cpu1.iew.wb_consumers                479351020                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.817892                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.576108                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       76588811                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14772366                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4233759                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    644213743                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.802134                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.802116                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    454416895     70.54%     70.54% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     94019038     14.59%     85.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     32034419      4.97%     90.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     14900535      2.31%     92.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10532700      1.63%     94.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6339894      0.98%     95.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5911008      0.92%     95.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3813889      0.59%     96.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     22245365      3.45%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    644213743                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           439656238                       # Number of instructions committed
system.cpu1.commit.committedOps             516745942                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     157703093                       # Number of memory references committed
system.cpu1.commit.loads                     82440315                       # Number of loads committed
system.cpu1.commit.membars                    3590265                       # Number of memory barriers committed
system.cpu1.commit.branches                  97880986                       # Number of branches committed
system.cpu1.commit.fp_insts                    458119                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                474489741                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12901444                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       357849627     69.25%     69.25% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1084383      0.21%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           49292      0.01%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        59547      0.01%     69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       82440315     15.95%     85.44% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      75262778     14.56%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        516745942                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             22245365                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1211389031                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1199768965                       # The number of ROB writes
system.cpu1.timesIdled                        3993228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       26295838                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 52679663676                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  439656238                       # Number of Instructions Simulated
system.cpu1.committedOps                    516745942                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.554826                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.554826                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.643159                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.643159                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               676354635                       # number of integer regfile reads
system.cpu1.int_regfile_writes              399072274                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   856252                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  508516                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                122966367                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               124089822                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1193194921                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14876268                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40295                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40295                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353732                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492144                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           566083715                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147708000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115455                       # number of replacements
system.iocache.tags.tagsinuse               10.418427                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115471                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13100950746000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.907029                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.511398                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.369189                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.281962                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651152                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039623                       # Number of tag accesses
system.iocache.tags.data_accesses             1039623                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8810                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8847                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8810                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8850                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8810                       # number of overall misses
system.iocache.overall_misses::total             8850                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1682627953                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1687696953                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13827060762                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13827060762                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1682627953                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1688047953                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1682627953                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1688047953                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8810                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8847                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8810                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8850                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8810                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8850                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 190990.687060                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190764.886741                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129631.935442                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129631.935442                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 190990.687060                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190739.881695                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 190990.687060                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190739.881695                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         34328                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3540                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.697175                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8810                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8847                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8810                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8850                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8810                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8850                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1242127953                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1245346953                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8493860762                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8493860762                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1242127953                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1245547953                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1242127953                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1245547953                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140990.687060                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140764.886741                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79631.935442                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79631.935442                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140990.687060                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140739.881695                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140990.687060                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140739.881695                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1323890                       # number of replacements
system.l2c.tags.tagsinuse                65259.173207                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49503955                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1386900                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    35.693961                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              22417690500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35449.280973                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   177.543359                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   251.636127                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3743.427577                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11664.257926                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   184.830913                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   267.828045                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3663.308299                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9857.059987                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.540913                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002709                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003840                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.057120                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.177982                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002820                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004087                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.055898                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.150407                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995776                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          340                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62670                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            2                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          338                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          522                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2822                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5058                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54162                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.956268                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                439519380                       # Number of tag accesses
system.l2c.tags.data_accesses               439519380                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       521678                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       191582                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       519241                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       187306                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1419807                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         8003050                       # number of Writeback hits
system.l2c.Writeback_hits::total              8003050                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            4987                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4929                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9916                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             7                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                12                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           801026                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           796134                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1597160                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       8079380                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       7822011                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15901391                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3419295                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3389369                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6808664                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       366665                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       355660                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           722325                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        521678                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        191582                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             8079380                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4220321                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        519241                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        187306                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             7822011                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4185503                       # number of demand (read+write) hits
system.l2c.demand_hits::total                25727022                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       521678                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       191582                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            8079380                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4220321                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       519241                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       187306                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            7822011                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4185503                       # number of overall hits
system.l2c.overall_hits::total               25727022                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2385                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2209                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2157                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2046                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8797                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17872                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17867                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35739                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         253766                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         252883                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             506649                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        49787                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        43083                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           92870                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       152502                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       146761                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         299263                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       244980                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       263543                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         508523                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2385                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2209                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             49787                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            406268                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2157                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2046                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             43083                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            399644                       # number of demand (read+write) misses
system.l2c.demand_misses::total                907579                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2385                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2209                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            49787                       # number of overall misses
system.l2c.overall_misses::cpu0.data           406268                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2157                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2046                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            43083                       # number of overall misses
system.l2c.overall_misses::cpu1.data           399644                       # number of overall misses
system.l2c.overall_misses::total               907579                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    330587500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    305529000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    297439000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    279631000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1213186500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    736393000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    731683000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1468076000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       162000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  37974955500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  37838601500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  75813557000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   6745602000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   5821443000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total  12567045000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  21410161500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  20684911000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  42095072500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  38132344500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  40861691500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  78994036000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    330587500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    305529000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6745602000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  59385117000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    297439000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    279631000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   5821443000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  58523512500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    131688861000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    330587500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    305529000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6745602000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  59385117000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    297439000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    279631000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   5821443000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  58523512500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   131688861000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       524063                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       193791                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       521398                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       189352                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1428604                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      8003050                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          8003050                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        22859                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22796                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45655                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            8                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            14                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1054792                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1049017                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2103809                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      8129167                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      7865094                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15994261                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3571797                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3536130                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7107927                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       611645                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       619203                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1230848                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       524063                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       193791                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         8129167                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4626589                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       521398                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       189352                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         7865094                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4585147                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            26634601                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       524063                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       193791                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        8129167                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4626589                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       521398                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       189352                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        7865094                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4585147                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           26634601                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004551                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011399                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004137                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.010805                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006158                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781836                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783778                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782806                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.125000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.166667                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.142857                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.240584                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.241067                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.240825                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006124                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005478                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005806                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042696                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041503                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.042103                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.400526                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.425616                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.413148                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004551                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011399                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006124                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.087812                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004137                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.010805                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005478                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.087161                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.034075                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004551                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011399                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006124                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.087812                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004137                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.010805                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005478                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.087161                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.034075                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138611.111111                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138311.000453                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137894.761242                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 136672.043011                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 137909.116744                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41203.726500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 40951.642693                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 41077.702230                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        81000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        81000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149645.561265                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149628.885690                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 149637.238009                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135489.224095                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135121.579277                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135318.671261                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140392.660424                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140942.832224                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140662.469133                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155654.928974                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155047.531143                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 155340.143907                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138611.111111                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138311.000453                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135489.224095                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 146172.272982                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137894.761242                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136672.043011                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135121.579277                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146439.112060                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145099.061349                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138611.111111                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138311.000453                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135489.224095                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 146172.272982                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137894.761242                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136672.043011                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135121.579277                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146439.112060                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145099.061349                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1116813                       # number of writebacks
system.l2c.writebacks::total                  1116813                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           34                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                86                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           13                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker           16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                111                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker           12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker           16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               111                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2373                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2175                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2141                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2022                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8711                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks         1086                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1086                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17872                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17867                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35739                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       253766                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       252883                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        506649                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        49786                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        43081                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        92867                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       152493                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       146748                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       299241                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       244980                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       263543                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       508523                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2373                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2175                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        49786                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       406259                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2141                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2022                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        43081                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       399631                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           907468                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2373                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2175                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        49786                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       406259                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2141                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2022                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        43081                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       399631                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          907468                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16464                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17213                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54323                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15292                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18404                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31756                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35617                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88019                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    305217000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    279837500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    274141000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    256675000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1115870500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1264455500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1264017500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2528473000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        71000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        71000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       142000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  35437295500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  35309771500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  70747067000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   6247713000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   5390595500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total  11638308500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19883985000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19215795500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  39099780500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  35682544500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  38226261500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  73908806000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    305217000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    279837500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6247713000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  55321280500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    274141000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    256675000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   5390595500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  54525567000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 122601026500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    305217000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    279837500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6247713000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  55321280500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    274141000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    256675000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   5390595500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  54525567000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 122601026500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472102000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2613760500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844005498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2806963500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7736831498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2537968000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2895218500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5433186500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472102000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5151728500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844005498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5702182000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13170017998                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004528                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011223                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004106                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.010679                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006098                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781836                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783778                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.782806                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.125000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.142857                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.240584                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.241067                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.240825                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005806                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042694                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041500                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042100                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.400526                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.425616                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.413148                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004528                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011223                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.087810                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004106                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010679                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.087158                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034071                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004528                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011223                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006124                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.087810                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004106                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010679                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005477                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.087158                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034071                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 128099.012743                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70750.643465                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70745.928248                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70748.286186                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139645.561265                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139628.885690                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 139637.238009                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125322.326553                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130392.772127                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130944.173004                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130663.179511                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145654.928974                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145047.531143                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145340.143907                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136172.442949                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136439.783200                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135102.313801                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125491.363034                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136172.442949                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125126.981732                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136439.783200                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135102.313801                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158756.104227                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163072.300006                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142422.758279                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165967.041590                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157314.632689                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161241.289767                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162228.507998                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160097.200775                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 149626.989605                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54323                       # Transaction distribution
system.membus.trans_dist::ReadResp             463989                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::Writeback           1223443                       # Transaction distribution
system.membus.trans_dist::CleanEvict           213592                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36616                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36618                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1014298                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1014298                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        409666                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6856                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4273089                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4402725                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342054                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4744779                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    163341292                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    163512986                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7254912                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7254912                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               170767898                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2786                       # Total snoops (count)
system.membus.snoop_fanout::samples           3094626                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3094626    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3094626                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113794499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5590500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8281023093                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7728395442                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228381503                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     53734904                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     27297777                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         4493                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2110                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2110                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            2021207                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25124422                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          9226509                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict        18644458                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45658                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            14                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45672                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2103809                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2103809                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15994542                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7116774                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1337512                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1230848                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48020569                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31553133                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       908522                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2486966                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              82969190                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1024954048                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1101984346                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3065144                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8363688                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2138367226                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2094185                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         56528569                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.014634                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.120081                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               55701347     98.54%     98.54% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 827222      1.46%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           56528569                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        35506762964                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1418902                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24036893583                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14511308139                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         525798129                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1444244841                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16329                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------