path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.329060                       # Number of seconds simulated
sim_ticks                                51329059921000                       # Number of ticks simulated
final_tick                               51329059921000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 136441                       # Simulator instruction rate (inst/s)
host_op_rate                                   160331                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7875321628                       # Simulator tick rate (ticks/s)
host_mem_usage                                 694032                       # Number of bytes of host memory used
host_seconds                                  6517.71                       # Real time elapsed on the host
sim_insts                                   889279572                       # Number of instructions simulated
sim_ops                                    1044993075                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       138560                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       132032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3631936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         41395808                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       145856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       130368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3527872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         42283560                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        424576                       # Number of bytes read from this memory
system.physmem.bytes_read::total             91810568                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3631936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3527872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7159808                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78035520                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78056100                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2165                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2063                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             56749                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            646818                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2279                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2037                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             55123                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            660685                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6634                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1434553                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1219305                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1221878                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2699                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2572                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               70758                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              806479                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2842                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2540                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               68731                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              823774                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8272                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1788666                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          70758                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          68731                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             139488                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1520299                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1520700                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1520299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2699                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2572                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              70758                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             806479                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2842                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2540                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              68731                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             824175                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8272                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3309366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1434553                       # Number of read requests accepted
system.physmem.writeReqs                      1221878                       # Number of write requests accepted
system.physmem.readBursts                     1434553                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1221878                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 91768384                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     43008                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78056128                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  91810568                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78056100                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      672                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         354445                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               86303                       # Per bank write bursts
system.physmem.perBankRdBursts::1               88556                       # Per bank write bursts
system.physmem.perBankRdBursts::2               87585                       # Per bank write bursts
system.physmem.perBankRdBursts::3               86132                       # Per bank write bursts
system.physmem.perBankRdBursts::4               85519                       # Per bank write bursts
system.physmem.perBankRdBursts::5               93403                       # Per bank write bursts
system.physmem.perBankRdBursts::6               87506                       # Per bank write bursts
system.physmem.perBankRdBursts::7               86099                       # Per bank write bursts
system.physmem.perBankRdBursts::8               84644                       # Per bank write bursts
system.physmem.perBankRdBursts::9              113970                       # Per bank write bursts
system.physmem.perBankRdBursts::10              93714                       # Per bank write bursts
system.physmem.perBankRdBursts::11              93674                       # Per bank write bursts
system.physmem.perBankRdBursts::12              83678                       # Per bank write bursts
system.physmem.perBankRdBursts::13              89960                       # Per bank write bursts
system.physmem.perBankRdBursts::14              85105                       # Per bank write bursts
system.physmem.perBankRdBursts::15              88033                       # Per bank write bursts
system.physmem.perBankWrBursts::0               73419                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74799                       # Per bank write bursts
system.physmem.perBankWrBursts::2               75041                       # Per bank write bursts
system.physmem.perBankWrBursts::3               76138                       # Per bank write bursts
system.physmem.perBankWrBursts::4               74959                       # Per bank write bursts
system.physmem.perBankWrBursts::5               79592                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75110                       # Per bank write bursts
system.physmem.perBankWrBursts::7               75651                       # Per bank write bursts
system.physmem.perBankWrBursts::8               74129                       # Per bank write bursts
system.physmem.perBankWrBursts::9               81022                       # Per bank write bursts
system.physmem.perBankWrBursts::10              78327                       # Per bank write bursts
system.physmem.perBankWrBursts::11              79368                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72597                       # Per bank write bursts
system.physmem.perBankWrBursts::13              77989                       # Per bank write bursts
system.physmem.perBankWrBursts::14              74762                       # Per bank write bursts
system.physmem.perBankWrBursts::15              76724                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    51329058678000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1434538                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1219305                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    657679                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    396498                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    215329                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    158489                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       891                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       626                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       551                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       765                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       399                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      190                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       93                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       799                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       783                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       779                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       767                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    15449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    29688                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    42902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    73169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    74512                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    75065                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    77780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    77068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    77521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    84532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    78913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    91198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    97883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    75890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    80091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    71759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      360                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      328                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      345                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       15                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       561036                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      302.697381                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.440606                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     331.820574                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         224613     40.04%     40.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       128067     22.83%     62.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        54948      9.79%     72.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26347      4.70%     77.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23416      4.17%     81.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12898      2.30%     83.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13342      2.38%     86.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8863      1.58%     87.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        68542     12.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         561036                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         69852                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.526986                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      231.209031                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          69847     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           69852                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         69852                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.460159                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.920258                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.852761                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                44      0.06%      0.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                27      0.04%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               11      0.02%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              61      0.09%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           65855     94.28%     94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1487      2.13%     96.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             231      0.33%     96.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             500      0.72%     97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              71      0.10%     97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             334      0.48%     98.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             206      0.29%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              35      0.05%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              69      0.10%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             137      0.20%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              25      0.04%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              32      0.05%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             488      0.70%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              32      0.05%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              34      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             111      0.16%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            24      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           69852                       # Writes before turning the bus around for reads
system.physmem.totQLat                    41803653811                       # Total ticks spent queuing
system.physmem.totMemAccLat               68688922561                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7169405000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29154.20                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47904.20                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.79                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.79                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.57                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1177173                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    915297                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.05                       # Row buffer hit rate for writes
system.physmem.avgGap                     19322564.25                       # Average gap between requests
system.physmem.pageHitRate                      78.86                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2106662040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1149468375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5468603400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3918514320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1237967178795                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29711496726750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34314671476320                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.523347                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49427496871292                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1713989940000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    187567949958                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2134770120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1164805125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5715621600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3984668640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352564322640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1240798843035                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29709012810750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34315375841910                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.537070                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49423322508450                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1713989940000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    191746853550                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1024                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2148                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst         1088                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1024                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           17                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              128171553                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         86901839                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5585684                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            86828453                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               62767092                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            72.288622                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16853141                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            186956                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   885239                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               885239                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16068                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        88252                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       546727                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       338512                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2698.944203                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 16449.109677                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       335800     99.20%     99.20% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1393      0.41%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          884      0.26%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          153      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679          156      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           36      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           43      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287           32      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823           10      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       338512                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       409508                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23024.226633                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18496.792158                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19848.076678                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       400961     97.91%     97.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6256      1.53%     99.44% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1568      0.38%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          126      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          350      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          156      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            9      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       409508                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 369272261460                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.199871                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.721140                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 368268104460     99.73%     99.73% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    539578000      0.15%     99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    201182000      0.05%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    121167500      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     48555500      0.01%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     26406000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     26984000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     34302000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      5588500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       301000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        52000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47        18000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 369272261460                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        88253     84.60%     84.60% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        16068     15.40%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       104321                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       885239                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       885239                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104321                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104321                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       989560                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   102290715                       # DTB read hits
system.cpu0.dtb.read_misses                    610545                       # DTB read misses
system.cpu0.dtb.write_hits                   79331513                       # DTB write hits
system.cpu0.dtb.write_misses                   274694                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1105                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   54684                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9578                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    56017                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               102901260                       # DTB read accesses
system.cpu0.dtb.write_accesses               79606207                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        181622228                       # DTB hits
system.cpu0.dtb.misses                         885239                       # DTB misses
system.cpu0.dtb.accesses                    182507467                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   102914                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               102914                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2949                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69039                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14347                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        88567                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1898.844942                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 12048.773919                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        87489     98.78%     98.78% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          597      0.67%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303           92      0.10%     99.56% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          110      0.12%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839          199      0.22%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           35      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        88567                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        86335                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29628.748480                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24429.301414                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 24451.958978                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        84088     97.40%     97.40% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          706      0.82%     98.22% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1293      1.50%     99.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           86      0.10%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679          119      0.14%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           18      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           16      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        86335                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 279075367244                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.887042                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -247471426488    -88.68%    -88.68% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   526476465732    188.65%     99.97% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       62141000      0.02%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        6800000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4        1085000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5         302000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 279075367244                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        69039     95.90%     95.90% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2949      4.10%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        71988                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102914                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102914                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71988                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71988                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       174902                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    91881601                       # ITB inst hits
system.cpu0.itb.inst_misses                    102914                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1105                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21571                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    526                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   40429                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   204535                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                91984515                       # ITB inst accesses
system.cpu0.itb.hits                         91881601                       # DTB hits
system.cpu0.itb.misses                         102914                       # DTB misses
system.cpu0.itb.accesses                     91984515                       # DTB accesses
system.cpu0.numCycles                       691170563                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         239962884                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     570438077                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  128171553                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          79620233                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    407738854                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               12781952                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2594971                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               25425                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             5359                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      5458708                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       162648                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         3329                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 91660544                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3463851                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  41672                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         662342878                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.009072                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.262587                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               521294405     78.70%     78.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                17644727      2.66%     81.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                17609553      2.66%     84.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13023217      1.97%     85.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                28132742      4.25%     90.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 8705409      1.31%     91.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9465006      1.43%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8172202      1.23%     94.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                38295617      5.78%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           662342878                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.185441                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.825322                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               194658503                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            347202119                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                101960102                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13505854                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5013938                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19069784                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1396202                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             622839427                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4306034                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5013938                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               202133183                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               32047845                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     264605257                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                107868981                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             50671063                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             608332366                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                94298                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2196276                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1835605                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              31002598                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            3774                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          582920651                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            941800609                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       719611293                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           780673                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            492512857                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                90407789                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          15406324                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13476597                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 76098764                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            97666868                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           83390194                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13497619                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14417995                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 576927509                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           15532510                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                579347297                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           823601                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       76188435                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     48806754                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        359672                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    662342878                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.874694                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.613558                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          433272632     65.42%     65.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           98115954     14.81%     80.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           42214584      6.37%     86.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           29957655      4.52%     91.13% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           22351656      3.37%     94.50% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           15512359      2.34%     96.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10588779      1.60%     98.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6205955      0.94%     99.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4123304      0.62%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      662342878                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                2935970     25.32%     25.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 23101      0.20%     25.52% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2125      0.02%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.54% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4825862     41.62%     67.16% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3807172     32.84%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            393154923     67.86%     67.86% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1386126      0.24%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                65806      0.01%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 67      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         58960      0.01%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           104322059     18.01%     86.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           80359344     13.87%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             579347297                       # Type of FU issued
system.cpu0.iq.rate                          0.838212                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11594230                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.020013                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1832414752                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        668808824                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    557946251                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1040551                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            514226                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       463065                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             590385045                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 556471                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4593967                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     15457682                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        19886                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       685587                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      8559329                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3807037                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      8317580                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5013938                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               16283569                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles             13949536                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          592593872                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1684559                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             97666868                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            83390194                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13181889                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                225552                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents             13639351                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        685587                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2515735                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2200394                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4716129                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            572987032                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            102282970                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5487366                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       133853                       # number of nop insts executed
system.cpu0.iew.exec_refs                   181615455                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               106143494                       # Number of branches executed
system.cpu0.iew.exec_stores                  79332485                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.829010                       # Inst execution rate
system.cpu0.iew.wb_sent                     559590255                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    558409316                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                275573262                       # num instructions producing a value
system.cpu0.iew.wb_consumers                478603193                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.807918                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.575787                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       76231429                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15172838                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4208370                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    649315784                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.795101                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.790427                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    458104846     70.55%     70.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     95694647     14.74%     85.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     32190614      4.96%     90.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     14675845      2.26%     92.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10626542      1.64%     94.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6339406      0.98%     95.12% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      5863967      0.90%     96.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3778167      0.58%     96.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22041750      3.39%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    649315784                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           439229242                       # Number of instructions committed
system.cpu0.commit.committedOps             516271579                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     157040050                       # Number of memory references committed
system.cpu0.commit.loads                     82209185                       # Number of loads committed
system.cpu0.commit.membars                    3679399                       # Number of memory barriers committed
system.cpu0.commit.branches                  98142600                       # Number of branches committed
system.cpu0.commit.fp_insts                    444854                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                473776942                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13048594                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       358050943     69.35%     69.35% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1081428      0.21%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           48877      0.01%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        50281      0.01%     69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.58% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       82209185     15.92%     85.51% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      74830865     14.49%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        516271579                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22041750                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1215785177                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1198053925                       # The number of ROB writes
system.cpu0.timesIdled                        4064231                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       28827685                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 52470002692                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  439229242                       # Number of Instructions Simulated
system.cpu0.committedOps                    516271579                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.573599                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.573599                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.635486                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.635486                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               676011417                       # number of integer regfile reads
system.cpu0.int_regfile_writes              398349827                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   844800                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  475036                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                123341922                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               124453917                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1200774516                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15268687                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10441215                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.972989                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          300350847                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10441727                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.764480                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   278.618843                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   233.354146                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.544177                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.455770                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           24                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1324703631                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1324703631                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77691173                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     80692342                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      158383515                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     65479208                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     68217846                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     133697054                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204861                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       196710                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       401571                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173286                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       151828                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       325114                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1754825                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1726209                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3481034                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2015188                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1998716                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4013904                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    143170381                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    148910188                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       292080569                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    143375242                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    149106898                       # number of overall hits
system.cpu0.dcache.overall_hits::total      292482140                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6274582                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6195801                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12470383                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6551010                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6079210                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12630220                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       672252                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604348                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1276600                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       607594                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       629524                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1237118                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       316888                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       332062                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       648950                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     12825592                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     12275011                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      25100603                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     13497844                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     12879359                       # number of overall misses
system.cpu0.dcache.overall_misses::total     26377203                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110046320000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111087741500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 221134061500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 282950530887                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 268653294230                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 551603825117                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43457890636                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47921476510                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  91379367146                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4290157000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4634510500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   8924667500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       150500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       207500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       358000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 392996850887                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 379741035730                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 772737886617                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 392996850887                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 379741035730                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 772737886617                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     83965755                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     86888143                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    170853898                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     72030218                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297056                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146327274                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       877113                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       801058                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1678171                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       780880                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       781352                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1562232                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2071713                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2058271                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4129984                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2015194                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1998721                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4013915                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    155995973                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    161185199                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    317181172                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    156873086                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    161986257                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    318859343                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074728                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071308                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.072989                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090948                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.081823                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.086315                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766437                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.754437                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.760709                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.778089                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.805686                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791891                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.152959                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.161331                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.157131                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082217                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.076155                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.079136                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086043                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.079509                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.082724                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17538.430448                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17929.520574                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17732.740165                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.894210                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44192.139148                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43673.334678                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71524.555272                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76123.351151                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73864.713912                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13538.401580                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13956.762593                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13752.473226                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25083.333333                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        41500                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32545.454545                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30641.614897                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30936.105534                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30785.630394                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29115.527701                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29484.467024                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29295.671972                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     87920844                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       114851                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3496537                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1061                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.145120                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   108.247879                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8016148                       # number of writebacks
system.cpu0.dcache.writebacks::total          8016148                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3459904                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3385993                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6845897                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5454136                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5045051                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10499187                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3486                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3453                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         6939                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       195002                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       204372                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       399374                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8914040                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8431044                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17345084                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8914040                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8431044                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17345084                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2814678                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2809808                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5624486                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1096874                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1034159                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2131033                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       658655                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       593550                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1252205                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       604108                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       626071                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230179                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       121886                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       127690                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       249576                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3911552                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3843967                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7755519                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4570207                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4437517                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      9007724                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15990                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17689                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33679                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14658                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19039                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30648                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        36728                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67376                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48435084000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49650597000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98085681000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50577189739                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  47912432297                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  98489622036                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13555749500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11111774000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24667523500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42652248636                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47094090510                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89746339146                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1696955500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1893897000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3590852500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       144500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       202500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       347000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99012273739                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97563029297                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 196575303036                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112568023239                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 108674803297                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 221242826536                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2881077500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3350690000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231767500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2752373000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3455424991                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207797991                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5633450500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6806114991                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12439565491                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033522                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032338                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032920                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015228                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.013919                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014563                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750935                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.740958                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746172                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.773625                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.801266                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787450                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058833                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062038                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060430                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025075                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023848                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024451                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029133                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027394                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028250                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17208.037296                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17670.458978                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17439.047941                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46110.300489                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46329.850919                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46216.845087                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20580.955887                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18720.872715                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19699.269289                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70603.681189                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75221.645005                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72953.886504                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13922.480843                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14831.991542                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14387.811729                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24083.333333                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        40500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 31545.454545                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25312.784731                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25380.818643                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25346.505248                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24630.836905                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24490.002697                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24561.457093                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180179.956223                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189422.239810                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185034.220137                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187772.752081                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181491.937129                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184224.055287                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183811.358001                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185311.342600                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184629.029491                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         16004570                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921303                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          169009090                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         16005082                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.559714                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      23708267500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   282.699542                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   229.221761                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.552148                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.447699                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           54                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        202254376                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       202254376                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     83086352                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     85922738                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      169009090                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     83086352                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     85922738                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       169009090                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     83086352                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     85922738                       # number of overall hits
system.cpu0.icache.overall_hits::total      169009090                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8561048                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8679036                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17240084                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8561048                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8679036                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17240084                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8561048                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8679036                       # number of overall misses
system.cpu0.icache.overall_misses::total     17240084                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115218528364                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 117350183832                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 232568712196                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 115218528364                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 117350183832                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 232568712196                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 115218528364                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 117350183832                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 232568712196                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     91647400                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     94601774                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    186249174                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     91647400                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     94601774                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    186249174                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     91647400                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     94601774                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    186249174                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093413                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091743                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092565                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093413                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091743                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092565                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093413                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091743                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092565                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13458.460736                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13521.108085                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.998784                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13458.460736                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13521.108085                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13489.998784                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.460736                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13521.108085                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13489.998784                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       127898                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             8453                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.130486                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     16004570                       # number of writebacks
system.cpu0.icache.writebacks::total         16004570                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       610799                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       624083                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1234882                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       610799                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       624083                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1234882                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       610799                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       624083                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1234882                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7950249                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8054953                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     16005202                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      7950249                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      8054953                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     16005202                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      7950249                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      8054953                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     16005202                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101752782407                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103549068385                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 205301850792                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101752782407                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103549068385                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 205301850792                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101752782407                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103549068385                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 205301850792                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085934                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.085934                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086748                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085146                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.085934                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12827.195233                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12798.691262                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.328688                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12827.195233                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups              131672686                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         89355343                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5781214                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            89724326                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               64173033                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            71.522446                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17121716                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            186515                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   890074                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               890074                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16464                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90676                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       549449                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       340625                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2662.717064                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 16656.719504                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       337983     99.22%     99.22% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1343      0.39%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          873      0.26%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          159      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679          157      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           28      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287           31      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::720896-786431            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::786432-851967            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::851968-917503            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::917504-983039            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::983040-1.04858e+06            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       340625                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       415755                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23534.974925                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18938.344998                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 20176.522890                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       406038     97.66%     97.66% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7288      1.75%     99.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1678      0.40%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          118      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          407      0.10%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          121      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           66      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       415755                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 351694007776                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.068501                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.668276                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 350661865276     99.71%     99.71% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    565026500      0.16%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    204421500      0.06%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    121176000      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     47649500      0.01%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     25922000      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     25482500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     35190500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      6889500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       280500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43        36000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47        45500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51        22500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 351694007776                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        90676     84.63%     84.63% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        16464     15.37%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       107140                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       890074                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       890074                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107140                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107140                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       997214                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   104588302                       # DTB read hits
system.cpu1.dtb.read_misses                    610979                       # DTB read misses
system.cpu1.dtb.write_hits                   81672452                       # DTB write hits
system.cpu1.dtb.write_misses                   279095                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1101                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   55425                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      192                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  9142                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    57336                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               105199281                       # DTB read accesses
system.cpu1.dtb.write_accesses               81951547                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        186260754                       # DTB hits
system.cpu1.dtb.misses                         890074                       # DTB misses
system.cpu1.dtb.accesses                    187150828                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   107237                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               107237                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3106                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        74018                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        14783                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        92454                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1914.233024                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 12442.896364                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        91334     98.79%     98.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          604      0.65%     99.44% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303           90      0.10%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          135      0.15%     99.69% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839          192      0.21%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           45      0.05%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375           20      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143           13      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911           11      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::425984-458751            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-491519            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        92454                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        91907                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29826.585570                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25014.091101                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23207.372292                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        89740     97.64%     97.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          728      0.79%     98.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1203      1.31%     99.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           89      0.10%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          102      0.11%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           19      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        91907                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 308743335316                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     1.811344                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0   -250411422516    -81.11%    -81.11% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   559080989832    181.08%     99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       64275500      0.02%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        7864000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4        1253500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         141000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6         234000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 308743335316                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        74018     95.97%     95.97% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         3106      4.03%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        77124                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       107237                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       107237                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        77124                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        77124                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       184361                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    94835234                       # ITB inst hits
system.cpu1.itb.inst_misses                    107237                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1101                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              20830                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   41604                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   202082                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                94942471                       # ITB inst accesses
system.cpu1.itb.hits                         94835234                       # DTB hits
system.cpu1.itb.misses                         107237                       # DTB misses
system.cpu1.itb.accesses                     94942471                       # DTB accesses
system.cpu1.numCycles                       690312922                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         244529898                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     585856252                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  131672686                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          81294749                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    402345645                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13192141                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2778573                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               21795                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             5943                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      5312997                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       174263                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         3566                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 94609332                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3554739                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  42315                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         661768476                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.036278                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.289766                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               517207044     78.16%     78.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                18129888      2.74%     80.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                18375332      2.78%     83.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13432056      2.03%     85.70% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                27838578      4.21%     89.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 9027951      1.36%     91.27% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9770345      1.48%     92.75% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8415200      1.27%     94.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                39572082      5.98%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           661768476                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.190743                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.848682                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               199426637                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            337927065                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                106132516                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13075533                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5204264                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19655517                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1411698                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             639761275                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4339654                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5204264                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               206862514                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               30693400                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     255298873                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                111614723                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             52092053                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             624767105                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents               119693                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               2051470                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1928200                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              33207471                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3875                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          596912920                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            957883599                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       738584518                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           769692                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            502441681                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                94471239                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14502575                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12526593                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 72768072                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           100816739                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           85870948                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13475308                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14310498                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 593385744                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           14541945                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                593302844                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           834025                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       79206193                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     50535241                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        362086                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    661768476                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.896541                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.637280                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          430990787     65.13%     65.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           95612119     14.45%     79.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           43322710      6.55%     86.12% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           31009109      4.69%     90.81% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           22951412      3.47%     94.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           16184580      2.45%     96.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10912216      1.65%     98.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6468210      0.98%     99.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4317333      0.65%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      661768476                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                3013963     25.80%     25.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 25479      0.22%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   3319      0.03%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.04% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4708735     40.30%     66.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3932373     33.66%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            402293875     67.81%     67.81% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1465613      0.25%     68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                66790      0.01%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                152      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         70080      0.01%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           106673645     17.98%     86.06% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           82732640     13.94%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             593302844                       # Type of FU issued
system.cpu1.iq.rate                          0.859469                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11683870                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019693                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1859837992                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        687326005                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    572108496                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1054067                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            524138                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       469445                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             604424270                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 562442                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4728038                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     15991835                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        20369                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       727913                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      8786210                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3909440                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      7480668                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5204264                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               16486033                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             12035619                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          608060202                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1765454                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            100816739                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            85870948                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12241352                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                233009                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents             11715765                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        727913                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2628157                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2293591                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4921748                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            586639297                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            104576028                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5786024                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       132513                       # number of nop insts executed
system.cpu1.iew.exec_refs                   186249978                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               108834662                       # Number of branches executed
system.cpu1.iew.exec_stores                  81673950                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.849816                       # Inst execution rate
system.cpu1.iew.wb_sent                     573803675                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    572577941                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                282811002                       # num instructions producing a value
system.cpu1.iew.wb_consumers                490863765                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.829447                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.576150                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       79254249                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14179859                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4389133                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    648242205                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.815623                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.819454                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    456295445     70.39%     70.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     93190134     14.38%     84.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     33049230      5.10%     89.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15421896      2.38%     92.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10834364      1.67%     93.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6534810      1.01%     94.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      6130401      0.95%     95.87% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3914098      0.60%     96.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     22871827      3.53%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    648242205                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           450050330                       # Number of instructions committed
system.cpu1.commit.committedOps             528721496                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     161909642                       # Number of memory references committed
system.cpu1.commit.loads                     84824904                       # Number of loads committed
system.cpu1.commit.membars                    3632926                       # Number of memory barriers committed
system.cpu1.commit.branches                 100459992                       # Number of branches committed
system.cpu1.commit.fp_insts                    451058                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                485698001                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13255700                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       365572080     69.14%     69.14% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1129275      0.21%     69.36% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           50278      0.01%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        60179      0.01%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       84824904     16.04%     85.42% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      77084738     14.58%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        528721496                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             22871827                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1229476063                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1229500763                       # The number of ROB writes
system.cpu1.timesIdled                        4141402                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       28544446                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 48806249668                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  450050330                       # Number of Instructions Simulated
system.cpu1.committedOps                    528721496                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.533857                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.533857                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.651951                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.651951                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               691759463                       # number of integer regfile reads
system.cpu1.int_regfile_writes              409243112                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   834045                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  529652                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                125054676                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               126221670                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1204731271                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14298109                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             47821000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25458500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              172500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            40147500                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              127000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           565671459                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               45000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115458                       # number of replacements
system.iocache.tags.tagsinuse               10.422741                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13100980146000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.902457                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.520285                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.368904                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.282518                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651421                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1698093507                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1703163007                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13865016452                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13865016452                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1698093507                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1703514007                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1698093507                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1703514007                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 192680.529559                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 192447.797401                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.778932                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129987.778932                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 192422.230543                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 192680.529559                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 192422.230543                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         37009                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3636                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.178493                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1257443507                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1260663007                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8531816452                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8531816452                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1257443507                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1260864007                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1257443507                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1260864007                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142680.529559                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 142447.797401                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.778932                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.778932                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 142680.529559                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 142422.230543                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 142680.529559                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 142422.230543                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1318326                       # number of replacements
system.l2c.tags.tagsinuse                65288.938042                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49534529                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1380698                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    35.876440                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              22398666000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35503.403742                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   177.290447                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   268.045616                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3654.613344                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    10777.196597                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   178.643969                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   246.380396                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3657.335195                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10826.028735                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.541739                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002705                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004090                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.055765                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.164447                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002726                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003759                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.055807                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.165192                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996230                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          345                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62027                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          344                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          522                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2801                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5049                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53552                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005264                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.946457                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                439709140                       # Number of tag accesses
system.l2c.tags.data_accesses               439709140                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       516692                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       183733                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       528381                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       196932                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1425738                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      8016148                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         8016148                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     16001128                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        16001128                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            4984                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4868                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9852                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           820290                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           772489                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1592779                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       7906464                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       8007151                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15913615                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3440520                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3376951                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6817471                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       364532                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       357882                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           722414                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        516692                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        183733                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             7906464                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4260810                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        528381                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        196932                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             8007151                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4149440                       # number of demand (read+write) hits
system.l2c.demand_hits::total                25749603                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       516692                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       183733                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            7906464                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4260810                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       528381                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       196932                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            8007151                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4149440                       # number of overall hits
system.l2c.overall_hits::total               25749603                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2179                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2088                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2288                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2071                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8626                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         18166                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17727                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35893                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         258857                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         245202                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             504059                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        43661                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        47614                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           91275                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       149276                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       147973                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         297249                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       239576                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       268187                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         507763                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2179                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2088                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             43661                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            408133                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2288                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2071                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             47614                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            393175                       # number of demand (read+write) misses
system.l2c.demand_misses::total                901209                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2179                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2088                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            43661                       # number of overall misses
system.l2c.overall_misses::cpu0.data           408133                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2288                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2071                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            47614                       # number of overall misses
system.l2c.overall_misses::cpu1.data           393175                       # number of overall misses
system.l2c.overall_misses::total               901209                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    300730000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    288356500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    318102000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    286190000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1193378500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    734088000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    738700500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1472788500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  38644566500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  36735616500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  75380183000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   5906509500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   6479989998                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total  12386499498                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  21069380500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  20753678500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  41823059000                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  37193130000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  41637080500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  78830210500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    300730000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    288356500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5906509500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  59713947000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    318102000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    286190000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6479989998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  57489295000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    130783119998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    300730000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    288356500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5906509500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  59713947000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    318102000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    286190000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6479989998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  57489295000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   130783119998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       518871                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       185821                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       530669                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       199003                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1434364                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      8016148                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      8016148                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     16001128                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     16001128                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23150                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22595                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45745                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1079147                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1017691                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2096838                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      7950125                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      8054765                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      16004890                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3589796                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3524924                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7114720                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       604108                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       626069                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1230177                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       518871                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       185821                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         7950125                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4668943                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       530669                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       199003                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         8054765                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4542615                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            26650812                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       518871                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       185821                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        7950125                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4668943                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       530669                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       199003                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        8054765                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4542615                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           26650812                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004200                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011237                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004312                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.010407                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006014                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784708                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784554                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.784632                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.166667                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.272727                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.239872                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.240940                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.240390                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005492                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005911                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005703                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041583                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041979                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.041779                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.396578                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.428367                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.412756                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004200                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011237                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005492                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.087414                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004312                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.010407                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.086553                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.033815                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004200                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011237                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005492                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.087414                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004312                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.010407                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.086553                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.033815                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138012.849931                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138101.772031                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 139030.594406                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138189.280541                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 138346.684442                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 40409.996697                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41670.925707                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 41032.750118                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        39750                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149289.246572                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149817.768615                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 149546.348741                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135281.131903                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 136094.215945                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135705.280723                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141143.790696                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140253.144155                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140700.419514                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155245.642301                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155253.910518                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 155250.009355                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138012.849931                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138101.772031                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135281.131903                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 146310.019038                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139030.594406                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138189.280541                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 136094.215945                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146218.083551                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145119.633734                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138012.849931                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138101.772031                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135281.131903                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 146310.019038                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139030.594406                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138189.280541                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 136094.215945                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146218.083551                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145119.633734                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1112675                       # number of writebacks
system.l2c.writebacks::total                  1112675                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           14                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           25                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           34                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                82                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           11                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker           14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           25                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                105                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker           14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           25                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               105                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2165                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2063                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2279                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2037                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8544                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        18166                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17727                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35893                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       258857                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       245202                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        504059                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        43660                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        47613                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        91273                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       149265                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       147963                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       297228                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       239576                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       268187                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       507763                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2063                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        43660                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       408122                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2279                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2037                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        47613                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       393165                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           901104                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2063                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        43660                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       408122                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2279                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2037                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        47613                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       393165                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          901104                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15990                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17689                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54325                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        14658                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19039                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30648                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        36728                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88022                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    277338500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    264753500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    294182000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    261573000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1097847000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1285399500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1254191000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2539590500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        71000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       141500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       212500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36055996500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  34283596500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  70339593000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   5469883500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6003848498                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total  11473731998                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19575562500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19272573500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  38848136000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  34797370000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  38955210500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  73752580500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    277338500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    264753500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5469883500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  55631559000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    294182000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    261573000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6003848498                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  53556170000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 121759307998                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    277338500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    264753500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5469883500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  55631559000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    294182000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    261573000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6003848498                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  53556170000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 121759307998                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2681108500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3129478000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8126836998                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2583747500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3234873998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5818621498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5264856000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6364351998                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13945458496                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005957                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784708                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784554                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.784632                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.239872                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240940                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.240390                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005703                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041580                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041976                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041776                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.396578                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.428367                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.412756                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.033812                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004173                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011102                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005492                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.087412                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004295                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010236                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005911                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.086550                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.033812                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 128493.328652                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.532423                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70750.324364                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70754.478589                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70750                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139289.246572                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139817.768615                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 139546.348741                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125707.843481                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131146.367199                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130252.654380                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130701.468233                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.642301                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145253.910518                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145250.009355                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125283.634906                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136311.100602                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126096.832756                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136218.050946                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135122.369891                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167674.077548                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176916.614845                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149596.631348                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176268.761086                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169907.768160                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172674.763273                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171784.651527                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173283.380473                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 158431.511395                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54325                       # Transaction distribution
system.membus.trans_dist::ReadResp             460220                       # Transaction distribution
system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1219305                       # Transaction distribution
system.membus.trans_dist::CleanEvict           210974                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36812                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36815                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1010906                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1010906                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        405895                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6862                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4252499                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4382141                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       341858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       341858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4723999                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13724                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    162617772                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    162789478                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7248896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7248896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               170038374                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2884                       # Total snoops (count)
system.membus.snoop_fanout::samples           3081006                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3081006    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3081006                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113865000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5486002                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8251811507                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7689965068                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          227507173                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     53750764                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     27303829                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         4497                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2153                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2153                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            2028554                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25149235                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9235460                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     16001128                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2638618                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45748                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45759                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2096838                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2096838                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      16005202                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7123570                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1336841                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1230177                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48052512                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31550783                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       914007                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2494586                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              83011888                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2049706496                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1102812070                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3078592                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8396320                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3163993478                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2090247                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         30104268                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027207                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.162685                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               29285228     97.28%     97.28% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 819040      2.72%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           30104268                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        51537960463                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1443392                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24054534227                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14512097283                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         529644514                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1447978944                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16329                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------