path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.284902                       # Number of seconds simulated
sim_ticks                                51284901790000                       # Number of ticks simulated
final_tick                               51284901790000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 166610                       # Simulator instruction rate (inst/s)
host_op_rate                                   195762                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             9559915430                       # Simulator tick rate (ticks/s)
host_mem_usage                                 696216                       # Number of bytes of host memory used
host_seconds                                  5364.58                       # Real time elapsed on the host
sim_insts                                   893791087                       # Number of instructions simulated
sim_ops                                    1050181412                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       151616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       131392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3547392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         26803872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       164672                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       152640                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3783872                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         26210856                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        417152                       # Number of bytes read from this memory
system.physmem.bytes_read::total             61363464                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3547392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3783872                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7331264                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     79575360                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          79595940                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2369                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2053                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             55428                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            418819                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2573                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2385                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             59123                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            409549                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6518                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                958817                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1243365                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1245938                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2956                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2562                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               69170                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              522646                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3211                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2976                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               73781                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              511083                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1196521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          69170                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          73781                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             142952                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1551633                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1552035                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1551633                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2562                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              69170                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             522647                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3211                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2976                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              73781                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             511484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8134                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2748556                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        958817                       # Number of read requests accepted
system.physmem.writeReqs                      1245938                       # Number of write requests accepted
system.physmem.readBursts                      958817                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1245938                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 61319744                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     44544                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  79596352                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  61363464                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               79595940                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      696                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2241                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               56014                       # Per bank write bursts
system.physmem.perBankRdBursts::1               61765                       # Per bank write bursts
system.physmem.perBankRdBursts::2               56852                       # Per bank write bursts
system.physmem.perBankRdBursts::3               54266                       # Per bank write bursts
system.physmem.perBankRdBursts::4               57300                       # Per bank write bursts
system.physmem.perBankRdBursts::5               65586                       # Per bank write bursts
system.physmem.perBankRdBursts::6               58254                       # Per bank write bursts
system.physmem.perBankRdBursts::7               56988                       # Per bank write bursts
system.physmem.perBankRdBursts::8               55394                       # Per bank write bursts
system.physmem.perBankRdBursts::9               83577                       # Per bank write bursts
system.physmem.perBankRdBursts::10              57993                       # Per bank write bursts
system.physmem.perBankRdBursts::11              64464                       # Per bank write bursts
system.physmem.perBankRdBursts::12              57098                       # Per bank write bursts
system.physmem.perBankRdBursts::13              62288                       # Per bank write bursts
system.physmem.perBankRdBursts::14              55335                       # Per bank write bursts
system.physmem.perBankRdBursts::15              54947                       # Per bank write bursts
system.physmem.perBankWrBursts::0               75753                       # Per bank write bursts
system.physmem.perBankWrBursts::1               78600                       # Per bank write bursts
system.physmem.perBankWrBursts::2               75987                       # Per bank write bursts
system.physmem.perBankWrBursts::3               76409                       # Per bank write bursts
system.physmem.perBankWrBursts::4               77268                       # Per bank write bursts
system.physmem.perBankWrBursts::5               81844                       # Per bank write bursts
system.physmem.perBankWrBursts::6               76609                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77405                       # Per bank write bursts
system.physmem.perBankWrBursts::8               75535                       # Per bank write bursts
system.physmem.perBankWrBursts::9               81820                       # Per bank write bursts
system.physmem.perBankWrBursts::10              76863                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81595                       # Per bank write bursts
system.physmem.perBankWrBursts::12              75866                       # Per bank write bursts
system.physmem.perBankWrBursts::13              80975                       # Per bank write bursts
system.physmem.perBankWrBursts::14              75599                       # Per bank write bursts
system.physmem.perBankWrBursts::15              75565                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          53                       # Number of times write queue was full causing retry
system.physmem.totGap                    51284900546000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  958802                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1243365                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    542154                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    273293                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     94311                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     42898                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       714                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       582                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       526                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1098                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       760                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       325                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       75                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       784                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    28439                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    34441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    47858                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    53530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    66664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    70454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    71905                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    72565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    73989                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    82526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    89703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    76639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    77053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    82881                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    72033                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    70668                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    68023                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1012                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      876                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      707                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      489                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      296                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      267                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      139                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       555731                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      253.568320                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     151.645025                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     292.798773                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         244526     44.00%     44.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       138101     24.85%     68.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        53162      9.57%     78.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26648      4.80%     83.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        19957      3.59%     86.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11140      2.00%     88.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10224      1.84%     90.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6833      1.23%     91.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        45140      8.12%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         555731                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         64596                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.832281                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       53.413760                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           64590     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            2      0.00%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7680-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8704-9215            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           64596                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         64596                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.253406                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.362319                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.482686                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7               110      0.17%      0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15               65      0.10%      0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           55177     85.42%     85.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            6740     10.43%     96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39             705      1.09%     97.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             447      0.69%     97.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             541      0.84%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             101      0.16%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             328      0.51%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             148      0.23%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             164      0.25%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95               5      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103              2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111             3      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119             7      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127             4      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135            17      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            16      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::328-335             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           64596                       # Writes before turning the bus around for reads
system.physmem.totQLat                    25254361125                       # Total ticks spent queuing
system.physmem.totMemAccLat               43219129875                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4790605000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       26358.22                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  45108.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.20                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.55                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.55                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.83                       # Average write queue length when enqueuing
system.physmem.readRowHits                     736278                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    909804                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   76.85                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.15                       # Row buffer hit rate for writes
system.physmem.avgGap                     23261042.86                       # Average gap between requests
system.physmem.pageHitRate                      74.76                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2087694000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1139118750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3642795000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4016790000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3349680278880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1234735113780                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29687838385500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34283140175910                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.484113                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49388248138285                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1712515480000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    184135332965                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2113632360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1153271625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3830509800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4042340640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3349680278880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1240634967750                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29682663075000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34284118076055                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.503181                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49379589334828                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1712515480000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    192796355672                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1024                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2148                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst         1088                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1024                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           17                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              131701737                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         88290011                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5749928                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            88871773                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               60662484                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            68.258438                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16943081                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            189225                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4992924                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2589273                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         2403651                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       412581                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   895264                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               895264                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17123                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90441                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       554296                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       340968                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2750.470719                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 16351.798354                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       338087     99.16%     99.16% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1498      0.44%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          976      0.29%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          136      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679          169      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           22      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           39      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287           36      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       340968                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       416487                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22961.536615                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18398.217426                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19575.689133                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       407358     97.81%     97.81% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6820      1.64%     99.45% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1636      0.39%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          111      0.03%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          329      0.08%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          154      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           63      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       416487                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 342294024144                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.109470                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.721232                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 341240531644     99.69%     99.69% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    582822500      0.17%     99.86% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    199579000      0.06%     99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    117924500      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     46760000      0.01%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     24862000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     28899000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     44321000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      7892500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       388000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        22500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47        11000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51        10500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 342294024144                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        90442     84.08%     84.08% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        17123     15.92%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       107565                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       895264                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       895264                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107565                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107565                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total      1002829                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   104837372                       # DTB read hits
system.cpu0.dtb.read_misses                    616098                       # DTB read misses
system.cpu0.dtb.write_hits                   80671443                       # DTB write hits
system.cpu0.dtb.write_misses                   279166                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1102                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21868                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    546                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   55634                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      233                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9003                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    56722                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               105453470                       # DTB read accesses
system.cpu0.dtb.write_accesses               80950609                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        185508815                       # DTB hits
system.cpu0.dtb.misses                         895264                       # DTB misses
system.cpu0.dtb.accesses                    186404079                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   102402                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               102402                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3079                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69849                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14173                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        88229                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1559.917941                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 11109.318329                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        87313     98.96%     98.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          469      0.53%     99.49% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303           83      0.09%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          147      0.17%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839          141      0.16%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           43      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        88229                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        87101                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28953.462073                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24215.206372                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 22576.849397                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        85266     97.89%     97.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          483      0.55%     98.45% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1148      1.32%     99.77% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           69      0.08%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           97      0.11%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           24      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        87101                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 630054255476                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.901585                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.298241                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    62069607016      9.85%      9.85% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   567926877960     90.14%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       53229500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        3926000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         600500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          14500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 630054255476                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        69849     95.78%     95.78% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         3079      4.22%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72928                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102402                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102402                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72928                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72928                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       175330                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    93547159                       # ITB inst hits
system.cpu0.itb.inst_misses                    102402                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1102                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21868                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    546                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   41100                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   189115                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                93649561                       # ITB inst accesses
system.cpu0.itb.hits                         93547159                       # DTB hits
system.cpu0.itb.misses                         102402                       # DTB misses
system.cpu0.itb.accesses                     93649561                       # DTB accesses
system.cpu0.numCycles                       688011025                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         243601869                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     585571838                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  131701737                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          80194838                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    401370000                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13146214                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2578790                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               20091                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             3656                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      4829637                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       164032                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         3268                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 93342305                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3584098                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  39018                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         659144176                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.038197                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.295091                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               515420904     78.20%     78.20% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                17940395      2.72%     80.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                18023461      2.73%     83.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13220348      2.01%     85.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                27959766      4.24%     89.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 8806264      1.34%     91.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9588960      1.45%     92.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8203319      1.24%     93.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                39980759      6.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           659144176                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.191424                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.851108                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               197499187                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            338466010                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                104398182                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13546805                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5231982                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19379138                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1360316                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             638255296                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4185441                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5231982                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               205063449                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               27153307                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     262923483                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                110249317                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             48520379                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             622996110                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents               132355                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2247994                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1861879                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              28960972                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            3803                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          595426650                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            956549851                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       734166245                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           794435                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            500270864                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                95155781                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          15187791                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13237681                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 75403173                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           100496845                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           84720468                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13599194                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14388955                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 590484103                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           15298411                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                591681421                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           857551                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       80930976                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     50447616                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        351888                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    659144176                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.897651                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.636567                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          427475761     64.85%     64.85% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           97836885     14.84%     79.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           42770645      6.49%     86.18% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           30584958      4.64%     90.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           22743510      3.45%     94.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           15987914      2.43%     96.70% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10968411      1.66%     98.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6384440      0.97%     99.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4391652      0.67%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      659144176                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                2986555     25.26%     25.26% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 23747      0.20%     25.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2157      0.02%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4879643     41.27%     66.74% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3932744     33.26%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass              139      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            401347935     67.83%     67.83% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1444621      0.24%     68.08% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                64829      0.01%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                116      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.09% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         56174      0.01%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           107054227     18.09%     86.19% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           81713380     13.81%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             591681421                       # Type of FU issued
system.cpu0.iq.rate                          0.859988                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11824846                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019985                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1854198838                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        686917057                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    569115204                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads             990577                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            508872                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       439153                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             602977632                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 528496                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4632250                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     16643333                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        19794                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       724475                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      8465055                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3918685                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      8300346                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5231982                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               15925349                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              9030114                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          605926435                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1719706                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            100496845                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            84720468                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          12946615                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                222991                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              8727203                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        724475                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2456659                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2686981                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5143640                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            584799722                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            104827609                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5998636                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       143921                       # number of nop insts executed
system.cpu0.iew.exec_refs                   185499348                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               108059724                       # Number of branches executed
system.cpu0.iew.exec_stores                  80671739                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.849986                       # Inst execution rate
system.cpu0.iew.wb_sent                     570956210                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    569554357                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                281415896                       # num instructions producing a value
system.cpu0.iew.wb_consumers                488383708                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.827827                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.576219                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       80977867                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       14946523                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4408529                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    645374166                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.813252                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.811592                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    452622252     70.13%     70.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     95504432     14.80%     84.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     32341034      5.01%     89.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     15221107      2.36%     92.30% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10764054      1.67%     93.97% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6526900      1.01%     94.98% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6016149      0.93%     95.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3811802      0.59%     96.50% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22566436      3.50%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    645374166                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           446835848                       # Number of instructions committed
system.cpu0.commit.committedOps             524851533                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     160108924                       # Number of memory references committed
system.cpu0.commit.loads                     83853511                       # Number of loads committed
system.cpu0.commit.membars                    3685792                       # Number of memory barriers committed
system.cpu0.commit.branches                  99662639                       # Number of branches committed
system.cpu0.commit.fp_insts                    420768                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                481718978                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13112301                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       363528180     69.26%     69.26% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1118140      0.21%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           48609      0.01%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        47680      0.01%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       83853511     15.98%     85.47% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      76255413     14.53%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        524851533                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22566436                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1224636916                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1225450764                       # The number of ROB writes
system.cpu0.timesIdled                        4112135                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       28866849                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 54222947414                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  446835848                       # Number of Instructions Simulated
system.cpu0.committedOps                    524851533                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.539740                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.539740                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.649460                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.649460                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               688252111                       # number of integer regfile reads
system.cpu0.int_regfile_writes              407094655                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   800302                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  473448                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                125192637                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               126303504                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1203085849                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15043668                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10538852                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.973177                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          302937432                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10539364                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.743426                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2695088500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   218.644895                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   293.328283                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.427041                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.572907                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999948                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          327                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1336210971                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1336210971                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     79968247                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     80371614                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      160339861                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     67069375                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     67205589                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     134274964                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       199346                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       203477                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       402823                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       140986                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       183532                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       324518                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1741209                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1760714                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3501923                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2021774                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2019563                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4041337                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    147178608                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    147760735                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       294939343                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    147377954                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    147964212                       # number of overall hits
system.cpu0.dcache.overall_hits::total      295342166                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6393063                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6235592                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12628655                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6405631                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6317446                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12723077                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       674803                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       616721                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1291524                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       612571                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       626179                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1238750                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       334024                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       316429                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       650453                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           14                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     13411265                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     13179217                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      26590482                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     14086068                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     13795938                       # number of overall misses
system.cpu0.dcache.overall_misses::total     27882006                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112258104000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112113839000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 224371943000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 288348477097                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 285240354815                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 573588831912                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25994460850                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  27091662781                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  53086123631                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4580448500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4477345000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   9057793500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       368500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        96000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       464500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 426601041947                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 424445856596                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 851046898543                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 426601041947                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 424445856596                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 851046898543                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     86361310                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     86607206                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    172968516                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73475006                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73523035                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146998041                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       874149                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       820198                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1694347                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       753557                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       809711                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1563268                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2075233                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2077143                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4152376                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2021781                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2019570                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4041351                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    160589873                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    160939952                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    321529825                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    161464022                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    161760150                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    323224172                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074027                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071999                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.073011                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.087181                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.085925                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.086553                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771954                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.751917                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.762255                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.812906                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.773336                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792411                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.160957                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152339                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156646                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.083513                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.081889                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.082700                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.087240                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.085286                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.086262                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17559.361452                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17979.662396                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17766.891486                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45014.843518                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45151.213768                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45082.556045                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 42435.017084                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43265.045268                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42854.590217                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13712.932304                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14149.603861                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13925.362017                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 52642.857143                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13714.285714                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 33178.571429                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31809.157596                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32205.696029                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 32005.696570                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30285.317517                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30766.002036                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 30523.158862                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     71133587                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       117068                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3523085                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1178                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.190710                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    99.378608                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      8064911                       # number of writebacks
system.cpu0.dcache.writebacks::total          8064911                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3541728                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3397150                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6938878                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5324879                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5249115                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10573994                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3231                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3726                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         6957                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       207685                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       194963                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       402648                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8869838                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8649991                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17519829                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8869838                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8649991                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17519829                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2851335                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2838442                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5689777                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1080752                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1068331                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2149083                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       659293                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       608119                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1267412                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       609340                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       622453                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1231793                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       126339                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121466                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       247805                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           14                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4541427                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      4529226                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      9070653                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5200720                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      5137345                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total     10338065                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16852                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16826                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15677                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18019                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32529                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34845                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  49729929500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49824787000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  99554716500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  51055928904                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  51023445012                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 102079373916                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13986697500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11236562000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  25223259500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  25203665850                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  26199660281                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  51403326131                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1811818500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1809464500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3621283000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       361500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        89000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       450500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 125989524254                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 127047892293                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 253037416547                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139976221754                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 138284454293                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 278260676047                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3092079500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3139092000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231171500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3092079500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3139092000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6231171500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033016                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032774                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032895                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014709                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014531                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014620                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754211                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.741430                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.748024                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.808618                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.768735                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787960                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060879                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058477                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059678                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028280                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028142                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028211                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032210                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031759                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.031984                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17440.928372                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17553.568824                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17497.120977                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47241.114431                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47759.959237                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47499.037457                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21214.691344                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18477.571002                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19901.389209                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 41362.237585                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42090.985634                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41730.490538                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14340.927979                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14896.880609                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14613.437986                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 51642.857143                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 12714.285714                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32178.571429                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27742.276658                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28050.685104                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27896.273460                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26914.777522                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26917.494210                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26916.127539                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183484.423214                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186561.987400                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185022.017341                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95056.088413                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 90087.300904                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92486.292932                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.replacements         16323462                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.933155                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          169414196                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         16323974                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.378245                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      19400599500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   237.111231                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   274.821924                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.463108                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.536762                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           55                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        203303412                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       203303412                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     84627850                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     84786346                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      169414196                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     84627850                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     84786346                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       169414196                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     84627850                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     84786346                       # number of overall hits
system.cpu0.icache.overall_hits::total      169414196                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8701471                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8863420                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17564891                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8701471                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8863420                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17564891                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8701471                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8863420                       # number of overall misses
system.cpu0.icache.overall_misses::total     17564891                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116896379852                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 120352735337                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 237249115189                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 116896379852                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 120352735337                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 237249115189                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 116896379852                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 120352735337                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 237249115189                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     93329321                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     93649766                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    186979087                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     93329321                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     93649766                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    186979087                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     93329321                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     93649766                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    186979087                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093234                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.094644                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.093940                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093234                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.094644                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.093940                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093234                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.094644                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.093940                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13434.094057                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13578.588777                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13507.007541                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13434.094057                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13578.588777                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13507.007541                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13434.094057                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13578.588777                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13507.007541                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       128531                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             8539                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    15.052231                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     16323462                       # number of writebacks
system.cpu0.icache.writebacks::total         16323462                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       613191                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       627375                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1240566                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       613191                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       627375                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1240566                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       613191                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       627375                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1240566                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8088280                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8236045                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     16324325                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      8088280                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      8236045                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     16324325                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      8088280                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      8236045                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     16324325                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12957                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7688                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20645                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12957                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7688                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20645                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103270633406                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 106205385876                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 209476019282                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103270633406                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 106205385876                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 209476019282                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103270633406                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 106205385876                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 209476019282                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1654613000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    981709000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636322000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1654613000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    981709000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636322000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.087306                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.087306                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086664                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.087945                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.087306                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12832.139723                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12832.139723                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12767.935013                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12895.192520                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12832.139723                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127697.844514                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127700.316431                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127693.678460                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127697.844514                       # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups              132207984                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         88587172                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5826495                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            89257950                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               60608223                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            67.902325                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17136106                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            189382                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4973679                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2647071                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         2326608                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       405619                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   905143                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               905143                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17108                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91252                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       560527                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       344616                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2714.976960                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 16407.674532                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       341711     99.16%     99.16% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1475      0.43%     99.59% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607         1008      0.29%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          155      0.04%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679          168      0.05%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           28      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           24      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287           38      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       344616                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       422123                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23405.519244                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.136881                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 20434.088485                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       412646     97.75%     97.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6891      1.63%     99.39% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1818      0.43%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          156      0.04%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          358      0.08%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          124      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           77      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           40      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::786432-851967            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       422123                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 367737970920                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.152186                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.727251                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 366665366920     99.71%     99.71% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    581252000      0.16%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    209708000      0.06%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    124789500      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     48258000      0.01%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     27968500      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     30956000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     41073500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      7796500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       589000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43       122000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47        17500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51        21000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55         3000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::56-59         5000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::60-63        44500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 367737970920                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        91252     84.21%     84.21% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        17108     15.79%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       108360                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       905143                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       905143                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       108360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       108360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total      1013503                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   104254499                       # DTB read hits
system.cpu1.dtb.read_misses                    630275                       # DTB read misses
system.cpu1.dtb.write_hits                   80849259                       # DTB write hits
system.cpu1.dtb.write_misses                   274868                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1096                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              20902                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   53828                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      197                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  9278                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    53866                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               104884774                       # DTB read accesses
system.cpu1.dtb.write_accesses               81124127                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        185103758                       # DTB hits
system.cpu1.dtb.misses                         905143                       # DTB misses
system.cpu1.dtb.accesses                    186008901                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   101154                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               101154                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3005                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68686                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        14200                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        86954                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1608.292890                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 11331.097997                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        85986     98.89%     98.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          520      0.60%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303           66      0.08%     99.56% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          164      0.19%     99.75% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839          145      0.17%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           40      0.05%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375           11      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        86954                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        85891                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29748.012015                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24412.003991                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 25999.467191                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        83578     97.31%     97.31% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          495      0.58%     97.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1521      1.77%     99.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           97      0.11%     99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          134      0.16%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           37      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           24      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        85891                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 612540191292                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.893340                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.309134                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    65404482540     10.68%     10.68% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   547076306252     89.31%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       50127000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        7455500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4        1506000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          91500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6         196000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::7          26500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 612540191292                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        68686     95.81%     95.81% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         3005      4.19%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        71691                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       101154                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       101154                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71691                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71691                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       172845                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    93866720                       # ITB inst hits
system.cpu1.itb.inst_misses                    101154                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1096                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              20902                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   39904                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   187991                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                93967874                       # ITB inst accesses
system.cpu1.itb.hits                         93866720                       # DTB hits
system.cpu1.itb.misses                         101154                       # DTB misses
system.cpu1.itb.accesses                     93967874                       # DTB accesses
system.cpu1.numCycles                       688149644                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         246774526                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     586387121                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  132207984                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          80391400                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    398002232                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13247809                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2526813                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               23208                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             3339                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      4746787                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       172822                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         4142                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 93657492                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3619612                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  39280                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         658877500                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.040777                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.297556                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               514943270     78.15%     78.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                17992448      2.73%     80.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                17938734      2.72%     83.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13188969      2.00%     85.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                27941093      4.24%     89.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 8949077      1.36%     91.21% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9653002      1.47%     92.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8287474      1.26%     93.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                39983433      6.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           658877500                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.192121                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.852122                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               200321379                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            334897766                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                105062974                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13347316                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5245962                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19411078                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1397694                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             639286066                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4311897                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5245962                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               207822387                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               28109229                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     259552504                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                110777742                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             47367249                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             624073748                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents               113090                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               1957012                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1963484                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              28046902                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3748                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          596057640                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            957465344                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       735885626                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           888832                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            500042308                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                96015332                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14940728                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12988345                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 74317967                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           100818071                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           84975729                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13584844                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14513721                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 591824868                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15016632                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                591532545                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           864332                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       81511621                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     51286616                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        358770                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    658877500                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.897788                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.636922                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          427630752     64.90%     64.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           97159571     14.75%     79.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           42910564      6.51%     86.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           30776221      4.67%     90.83% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           22686133      3.44%     94.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           15935700      2.42%     96.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10990898      1.67%     98.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6446525      0.98%     99.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4341136      0.66%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      658877500                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2999770     25.98%     25.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 25009      0.22%     26.19% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   3249      0.03%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4684166     40.56%     66.79% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3835188     33.21%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                2      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            401605558     67.89%     67.89% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1412010      0.24%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                67658      0.01%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                191      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         72305      0.01%     68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.15% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           106483903     18.00%     86.16% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           81890872     13.84%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             591532545                       # Type of FU issued
system.cpu1.iq.rate                          0.859599                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11547382                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019521                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1853248239                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        688458824                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    569767413                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1106065                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            569050                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       490960                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             602490208                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 589717                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4719123                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     16759885                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        20137                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       685641                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      8616382                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3886436                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      7425204                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5245962                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               16637308                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              9398313                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          606988228                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1717377                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            100818071                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            84975729                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12705052                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                239734                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              9069380                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        685641                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2485685                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2694157                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             5179842                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            584642052                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            104243442                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5998727                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       146728                       # number of nop insts executed
system.cpu1.iew.exec_refs                   185095226                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               108396618                       # Number of branches executed
system.cpu1.iew.exec_stores                  80851784                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.849586                       # Inst execution rate
system.cpu1.iew.wb_sent                     571674985                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    570258373                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                281283764                       # num instructions producing a value
system.cpu1.iew.wb_consumers                489058083                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.828684                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.575154                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       81573069                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14657862                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4448279                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    645042111                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.814412                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.812297                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    452426770     70.14%     70.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     94787874     14.69%     84.83% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     32819397      5.09%     89.92% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15329214      2.38%     92.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10832611      1.68%     93.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6451723      1.00%     94.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5988175      0.93%     95.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3853316      0.60%     96.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     22553031      3.50%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    645042111                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           446955239                       # Number of instructions committed
system.cpu1.commit.committedOps             525329879                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     160417533                       # Number of memory references committed
system.cpu1.commit.loads                     84058186                       # Number of loads committed
system.cpu1.commit.membars                    3661350                       # Number of memory barriers committed
system.cpu1.commit.branches                  99963573                       # Number of branches committed
system.cpu1.commit.fp_insts                    470740                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                482339888                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13268232                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       363697714     69.23%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1101230      0.21%     69.44% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           50710      0.01%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        62650      0.01%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       84058186     16.00%     85.46% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      76359347     14.54%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        525329879                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             22553031                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1225507013                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1227667180                       # The number of ROB writes
system.cpu1.timesIdled                        4198522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       29272144                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 46970319294                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  446955239                       # Number of Instructions Simulated
system.cpu1.committedOps                    525329879                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.539639                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.539639                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.649503                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.649503                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               688608688                       # number of integer regfile reads
system.cpu1.int_regfile_writes              407764370                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   881042                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  529972                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                124702473                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               125859602                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1202737772                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14790646                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40305                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40305                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230968                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353752                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334304                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334304                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492224                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             47810500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               348000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25726500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            40136500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           566999378                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147728000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115465                       # number of replacements
system.iocache.tags.tagsinuse               10.419655                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13096612113000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.546608                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.873047                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221663                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.429565                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651228                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039713                       # Number of tag accesses
system.iocache.tags.data_accesses             1039713                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8820                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8857                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115484                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115524                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115484                       # number of overall misses
system.iocache.overall_misses::total           115524                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1649759369                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1654845369                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13415597009                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13415597009                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15065356378                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15070793378                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15065356378                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15070793378                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8820                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8857                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115484                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115524                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115484                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115524                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 187047.547506                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186840.393926                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125774.366319                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125774.366319                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 130454.057514                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 130455.951820                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 130454.057514                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 130455.951820                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         33085                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3398                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.736610                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8820                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8857                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115484                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115524                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115484                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115524                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1208759369                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1211995369                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8077336951                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8077336951                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9286096320                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9289533320                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9286096320                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9289533320                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137047.547506                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136840.393926                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75726.927089                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75726.927089                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 80410.241419                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 80412.150895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 80410.241419                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 80412.150895                       # average overall mshr miss latency
system.l2c.tags.replacements                  1347841                       # number of replacements
system.l2c.tags.tagsinuse                65324.740261                       # Cycle average of tags in use
system.l2c.tags.total_refs                   50311393                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1410817                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    35.661176                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               4298396500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35245.257795                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   161.370291                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   265.309574                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3415.837838                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    12035.721839                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   188.618634                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   273.886836                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3763.840034                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9974.897420                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.537800                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002462                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004048                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052122                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.183651                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002878                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004179                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.057432                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.152205                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996776                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          377                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62599                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          377                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          537                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2787                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5038                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54135                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005753                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.955185                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                445845701                       # Number of tag accesses
system.l2c.tags.data_accesses               445845701                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       522213                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       182395                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       532310                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       179240                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1416158                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      8064911                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         8064911                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     16319354                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        16319354                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            5211                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4888                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10099                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             7                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           801611                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           788325                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1589936                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       8045447                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       8184125                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          16229572                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3472745                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3415235                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6887980                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       361895                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       361612                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           723507                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        522213                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        182395                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             8045447                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4274356                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        532310                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        179240                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             8184125                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4203560                       # number of demand (read+write) hits
system.l2c.demand_hits::total                26123646                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       522213                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       182395                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            8045447                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4274356                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       532310                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       179240                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            8184125                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4203560                       # number of overall hits
system.l2c.overall_hits::total               26123646                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2376                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2075                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2579                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2408                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 9438                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         18580                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17819                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             36399                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            4                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         261621                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         263338                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             524959                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        42503                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        51451                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           93954                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       157952                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       146755                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         304707                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       247445                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       260841                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         508286                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2376                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2075                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             42503                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            419573                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2579                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2408                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             51451                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            410093                       # number of demand (read+write) misses
system.l2c.demand_misses::total                933058                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2376                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2075                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            42503                       # number of overall misses
system.l2c.overall_misses::cpu0.data           419573                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2579                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2408                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            51451                       # number of overall misses
system.l2c.overall_misses::cpu1.data           410093                       # number of overall misses
system.l2c.overall_misses::total               933058                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    326039500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    282390500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    356127000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    334129500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1298686500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    729950500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    701197000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1431147500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       316500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       316500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  39471432500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  39659455000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  79130887500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   5746264000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   6990391000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total  12736655000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  22406709500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  20494783500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  42901493000                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data      5002500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data      4832000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total      9834500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    326039500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    282390500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5746264000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  61878142000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    356127000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    334129500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6990391000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  60154238500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    136067722000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    326039500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    282390500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5746264000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  61878142000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    356127000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    334129500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6990391000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  60154238500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   136067722000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       524589                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       184470                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       534889                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       181648                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1425596                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      8064911                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      8064911                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     16319354                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     16319354                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23791                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22707                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           46498                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            14                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1063232                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1051663                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2114895                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      8087950                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      8235576                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      16323526                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3630697                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3561990                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7192687                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       609340                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       622453                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1231793                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       524589                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       184470                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         8087950                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4693929                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       534889                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       181648                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         8235576                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4613653                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            27056704                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       524589                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       184470                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        8087950                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4693929                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       534889                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       181648                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        8235576                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4613653                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           27056704                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006620                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.780968                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784736                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782808                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.571429                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.246062                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.250402                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.248220                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005255                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006247                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005756                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.043505                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.041200                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.042363                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.406087                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.419053                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.412639                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005255                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.089386                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.006247                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.088887                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.034485                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004529                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011248                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005255                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.089386                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004822                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.013256                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.006247                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.088887                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.034485                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 137601.875397                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39286.894510                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39351.085920                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 39318.319185                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79125                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79125                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150872.569480                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 150602.856405                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 150737.271863                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135196.668470                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135865.017201                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135562.668966                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141857.713103                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139653.051003                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140795.889166                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    20.216614                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data    18.524695                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total    19.348359                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135196.668470                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 147478.846351                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135865.017201                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146684.382567                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145829.864810                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137222.011785                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136091.807229                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135196.668470                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 147478.846351                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138087.243117                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138758.098007                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135865.017201                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146684.382567                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145829.864810                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1136735                       # number of writebacks
system.l2c.writebacks::total                  1136735                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           22                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           23                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                58                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           11                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           11                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker            7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           22                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 81                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker            7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           22                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                81                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2369                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2053                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2573                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2385                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            9380                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            3                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            3                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        18580                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17819                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        36399                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            4                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       261621                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       263338                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        524959                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        42502                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        51451                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        93953                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       157941                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       146744                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       304685                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       247445                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       260841                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       508286                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2369                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2053                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        42502                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       419562                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2573                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2385                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        51451                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       410082                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           932977                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2369                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2053                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        42502                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       419562                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2573                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2385                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        51451                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       410082                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          932977                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        12957                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16852                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         7688                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16826                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54323                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15677                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18019                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        12957                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32529                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         7688                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        34845                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88019                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    301340001                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    259502000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    329367513                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    307643002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1197852516                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1263315500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1211712500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2475028000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       276500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       276500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36854821986                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  37025414103                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  73880236089                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   5321175594                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6475806664                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total  11796982258                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  20825962360                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19025744377                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  39851706737                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  17343311500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  18172131000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  35515442500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    301340001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    259502000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5321175594                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  57680784346                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    329367513                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    307643002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6475806664                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  56051158480                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 126726777600                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    301340001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    259502000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5321175594                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  57680784346                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    329367513                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    307643002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6475806664                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  56051158480                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 126726777600                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1453779500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2881358000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    862532000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2928681000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8126350500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1453779500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2881358000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    862532000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2928681000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8126350500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006580                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.780968                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784736                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.782808                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.246062                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.250402                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.248220                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005756                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.043502                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.041197                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042360                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.406087                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.419053                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.412639                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.089384                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.088884                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034482                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004516                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011129                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005255                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.089384                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004810                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013130                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006247                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.088884                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034482                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127702.826866                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67993.299247                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68001.150457                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67997.142779                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69125                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69125                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140871.038586                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140600.346714                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 140735.249970                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125562.592552                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131859.126889                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129652.622097                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130796.418389                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70089.561317                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69667.464087                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69872.950465                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137478.571334                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136682.806073                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135830.548449                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127201.351203                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126401.363858                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125198.239942                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137478.571334                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128009.138360                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128990.776520                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125863.572409                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136682.806073                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135830.548449                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170980.180394                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174056.876263                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149593.183366                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112200.316431                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 88578.130284                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112191.987513                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84048.816186                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 92324.958248                       # average overall mshr uncacheable latency
system.membus.trans_dist::ReadReq               54323                       # Transaction distribution
system.membus.trans_dist::ReadResp             471198                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1243365                       # Transaction distribution
system.membus.trans_dist::CleanEvict           218846                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            37171                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            524316                       # Transaction distribution
system.membus.trans_dist::ReadExResp           524316                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        416875                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        614824                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3802484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3932122                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237507                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237507                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4169629                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    133717932                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    133889630                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7241472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7241472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               141131102                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3009                       # Total snoops (count)
system.membus.snoop_fanout::samples           3143476                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3143476    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3143476                       # Request fanout histogram
system.membus.reqLayer0.occupancy           114116000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5372500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8328651016                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5128575160                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44638442                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     54578445                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     27714706                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         5543                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2124                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2124                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            2026220                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25543991                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9308329                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     16323462                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2693882                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           46501                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            14                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          46515                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2114895                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2114895                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      16324325                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7201544                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1338457                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1231793                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49012603                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31846136                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       876413                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2521080                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              84256232                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2090728512                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1112078430                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2928944                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8475824                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3214211710                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2126745                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         30549096                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.026641                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.161031                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               29735242     97.34%     97.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 813854      2.66%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           30549096                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        52321567856                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1445388                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24533352992                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14657364738                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         510704141                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1464609307                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16351                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------