path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.289328                       # Number of seconds simulated
sim_ticks                                51289327844000                       # Number of ticks simulated
final_tick                               51289327844000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 135228                       # Simulator instruction rate (inst/s)
host_op_rate                                   158909                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7809061274                       # Simulator tick rate (ticks/s)
host_mem_usage                                 694320                       # Number of bytes of host memory used
host_seconds                                  6567.93                       # Real time elapsed on the host
sim_insts                                   888164103                       # Number of instructions simulated
sim_ops                                    1043699308                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       136512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       126720                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3641344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         41468960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       150528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       137472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3597568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         42676392                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        428864                       # Number of bytes read from this memory
system.physmem.bytes_read::total             92364360                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3641344                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3597568                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7238912                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78441216                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78461796                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2133                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1980                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             56896                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            647961                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2352                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2148                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56212                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            666823                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6701                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1443206                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1225644                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1228217                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2662                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2471                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               70996                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              808530                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2935                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               70143                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              832072                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8362                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1800849                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          70996                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          70143                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             141139                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1529387                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1529788                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1529387                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2662                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2471                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              70996                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             808530                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2935                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2680                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              70143                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             832473                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8362                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3330637                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1443206                       # Number of read requests accepted
system.physmem.writeReqs                      1228217                       # Number of write requests accepted
system.physmem.readBursts                     1443206                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1228217                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 92312576                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     52608                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78461696                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  92364360                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78461796                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      822                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         356478                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               87850                       # Per bank write bursts
system.physmem.perBankRdBursts::1               89651                       # Per bank write bursts
system.physmem.perBankRdBursts::2               87083                       # Per bank write bursts
system.physmem.perBankRdBursts::3               86997                       # Per bank write bursts
system.physmem.perBankRdBursts::4               87338                       # Per bank write bursts
system.physmem.perBankRdBursts::5               97616                       # Per bank write bursts
system.physmem.perBankRdBursts::6               89147                       # Per bank write bursts
system.physmem.perBankRdBursts::7               87735                       # Per bank write bursts
system.physmem.perBankRdBursts::8               84823                       # Per bank write bursts
system.physmem.perBankRdBursts::9              114942                       # Per bank write bursts
system.physmem.perBankRdBursts::10              92351                       # Per bank write bursts
system.physmem.perBankRdBursts::11              95964                       # Per bank write bursts
system.physmem.perBankRdBursts::12              83458                       # Per bank write bursts
system.physmem.perBankRdBursts::13              87171                       # Per bank write bursts
system.physmem.perBankRdBursts::14              84360                       # Per bank write bursts
system.physmem.perBankRdBursts::15              85898                       # Per bank write bursts
system.physmem.perBankWrBursts::0               74977                       # Per bank write bursts
system.physmem.perBankWrBursts::1               75819                       # Per bank write bursts
system.physmem.perBankWrBursts::2               74752                       # Per bank write bursts
system.physmem.perBankWrBursts::3               76261                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75660                       # Per bank write bursts
system.physmem.perBankWrBursts::5               82258                       # Per bank write bursts
system.physmem.perBankWrBursts::6               76272                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77177                       # Per bank write bursts
system.physmem.perBankWrBursts::8               74263                       # Per bank write bursts
system.physmem.perBankWrBursts::9               81618                       # Per bank write bursts
system.physmem.perBankWrBursts::10              78101                       # Per bank write bursts
system.physmem.perBankWrBursts::11              81113                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72977                       # Per bank write bursts
system.physmem.perBankWrBursts::13              75983                       # Per bank write bursts
system.physmem.perBankWrBursts::14              73541                       # Per bank write bursts
system.physmem.perBankWrBursts::15              75192                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          18                       # Number of times write queue was full causing retry
system.physmem.totGap                    51289326709500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1443191                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1225644                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    662564                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    398514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    216343                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    159104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       873                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       598                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       577                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       787                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       375                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      385                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      191                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      169                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      103                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       81                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       63                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       787                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       749                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    15689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    30025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    60978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    73608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    74875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    75340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    78249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    77578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    77941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    84747                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    79458                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    91879                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    98217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    76400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    80241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    72208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      513                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      366                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       56                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       565463                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      302.007183                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.069104                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     331.382789                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         226805     40.11%     40.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       129321     22.87%     62.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        55220      9.77%     72.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26563      4.70%     77.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23290      4.12%     81.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13002      2.30%     83.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13617      2.41%     86.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9017      1.59%     87.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        68628     12.14%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         565463                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         70251                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.531565                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      230.543084                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          70246     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           70251                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         70251                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.451196                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.927151                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.708530                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                38      0.05%      0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                20      0.03%      0.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               12      0.02%      0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              64      0.09%      0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           66179     94.20%     94.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1570      2.23%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             250      0.36%     96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             470      0.67%     97.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              89      0.13%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             339      0.48%     98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             221      0.31%     98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              41      0.06%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              76      0.11%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             130      0.19%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              30      0.04%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              31      0.04%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             448      0.64%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              32      0.05%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              27      0.04%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             123      0.18%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              10      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            30      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             4      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           70251                       # Writes before turning the bus around for reads
system.physmem.totQLat                    41993928125                       # Total ticks spent queuing
system.physmem.totMemAccLat               69038628125                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7211920000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29114.25                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47864.25                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.53                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.53                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.19                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        10.56                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1183273                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    919611                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.04                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.01                       # Row buffer hit rate for writes
system.physmem.avgGap                     19199253.25                       # Average gap between requests
system.physmem.pageHitRate                      78.81                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2152490760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1174474125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5564652600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3973380480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3349969140960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1239658923690                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29686172799750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34288665862365                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.534207                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49385348498815                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1712663160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    191309868685                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2122409520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1158060750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5685895800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3970866240                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3349969140960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1241047287225                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29684954937000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34288908597495                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.538939                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49383290725827                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1712663160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    193373338673                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1024                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2148                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst         1088                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1024                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           17                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              128583219                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         87130706                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5608498                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            87627947                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               62974583                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.865866                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               16935709                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            187300                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   888652                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               888652                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16421                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        87809                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       549489                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       339163                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2672.191542                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 16085.449478                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       336454     99.20%     99.20% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1394      0.41%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          896      0.26%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          159      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679          148      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           38      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           39      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287           31      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       339163                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       409656                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22857.613461                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18421.045367                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19320.142266                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       401054     97.90%     97.90% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6459      1.58%     99.48% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1486      0.36%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           99      0.02%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          354      0.09%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          127      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           51      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           19      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       409656                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 372489857920                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.125711                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.685370                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 371484178920     99.73%     99.73% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    543967500      0.15%     99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    197972000      0.05%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    122397500      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     45621000      0.01%     99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     26772000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     27386500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     35231000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      5712500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       472000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        66500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47        35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51        45500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 372489857920                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        87810     84.25%     84.25% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        16421     15.75%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       104231                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       888652                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       888652                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       104231                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       104231                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       992883                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   102519767                       # DTB read hits
system.cpu0.dtb.read_misses                    608916                       # DTB read misses
system.cpu0.dtb.write_hits                   79730858                       # DTB write hits
system.cpu0.dtb.write_misses                   279736                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1105                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21393                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    535                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   55242                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      209                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9412                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    56039                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               103128683                       # DTB read accesses
system.cpu0.dtb.write_accesses               80010594                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        182250625                       # DTB hits
system.cpu0.dtb.misses                         888652                       # DTB misses
system.cpu0.dtb.accesses                    183139277                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   102152                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               102152                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3042                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68901                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14128                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        88024                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1905.912024                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 12139.697138                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535        87548     99.46%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071          189      0.21%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607          243      0.28%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143           22      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679           18      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        88024                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        86071                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29335.746070                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24303.412638                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 23702.116672                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        84000     97.59%     97.59% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          669      0.78%     98.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607         1177      1.37%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           63      0.07%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679          107      0.12%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           38      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        86071                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 290883014796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.826730                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -240403892944    -82.65%    -82.65% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   531218150240    182.62%     99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       61167000      0.02%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        6375000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4        1069000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5         146500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 290883014796                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        68901     95.77%     95.77% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         3042      4.23%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        71943                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102152                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102152                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        71943                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        71943                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       174095                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    92233828                       # ITB inst hits
system.cpu0.itb.inst_misses                    102152                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1105                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21393                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    535                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   40730                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   204444                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                92335980                       # ITB inst accesses
system.cpu0.itb.hits                         92233828                       # DTB hits
system.cpu0.itb.misses                         102152                       # DTB misses
system.cpu0.itb.accesses                     92335980                       # DTB accesses
system.cpu0.numCycles                       692838439                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         240908960                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     572231445                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  128583219                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          79910292                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    408388774                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               12834591                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2570044                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               24306                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             5220                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      5457264                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       161454                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         3138                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 92012846                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3478486                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  41135                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         663936181                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.010011                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.263466                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               522394328     78.68%     78.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                17725810      2.67%     81.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                17688411      2.66%     84.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13071873      1.97%     85.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                28203827      4.25%     90.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 8736087      1.32%     91.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9493633      1.43%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8170343      1.23%     94.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                38451869      5.79%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           663936181                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.185589                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.825923                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               195480668                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            347525883                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                102363007                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13531611                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5032846                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19144374                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1404061                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             624972262                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4324699                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5032846                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               202972273                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               31908208                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     264942356                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                108280793                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             50797146                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             610471334                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                95561                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2181622                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1833281                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              31100121                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            3748                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          584763041                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            944825531                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       722111361                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           774403                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            494202829                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                90560207                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          15441984                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13500490                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 76181815                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads            97914623                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           83796282                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13494788                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14509188                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 578969956                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           15549087                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                581387385                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           830768                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       76282364                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     48796155                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        362907                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    663936181                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.875668                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.614381                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          434128190     65.39%     65.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           98370789     14.82%     80.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           42377650      6.38%     86.59% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           30067622      4.53%     91.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           22403128      3.37%     94.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           15594972      2.35%     96.84% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10621983      1.60%     98.44% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6235616      0.94%     99.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4136231      0.62%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      663936181                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                2959786     25.50%     25.50% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 23278      0.20%     25.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2380      0.02%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.73% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4810604     41.45%     67.18% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3809012     32.82%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               11      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            394568235     67.87%     67.87% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1380833      0.24%     68.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                65255      0.01%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 66      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   2      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         59226      0.01%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           104545250     17.98%     86.11% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           80768506     13.89%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             581387385                       # Type of FU issued
system.cpu0.iq.rate                          0.839138                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11605060                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019961                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1838113951                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        670976650                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    559986003                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1032828                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            510697                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       459801                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             592439966                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 552468                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4598569                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     15443537                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        19687                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       696908                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      8570730                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3841968                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      8263079                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5032846                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               16244018                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles             13852341                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          594652790                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1703484                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts             97914623                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            83796282                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13208370                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                224559                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents             13543277                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        696908                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2523457                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2209016                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4732473                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            575002762                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            102511874                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5508716                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       133747                       # number of nop insts executed
system.cpu0.iew.exec_refs                   182243986                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               106498541                       # Number of branches executed
system.cpu0.iew.exec_stores                  79732112                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.829923                       # Inst execution rate
system.cpu0.iew.wb_sent                     561628821                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    560445804                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                276455484                       # num instructions producing a value
system.cpu0.iew.wb_consumers                480133798                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.808913                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.575788                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       76323092                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15186180                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4223774                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    650882635                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.796206                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.791535                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    459027992     70.52%     70.52% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     95977430     14.75%     85.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     32265262      4.96%     90.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     14738583      2.26%     92.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10675615      1.64%     94.13% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6384145      0.98%     95.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      5905756      0.91%     96.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3807566      0.58%     96.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22100286      3.40%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    650882635                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           440797694                       # Number of instructions committed
system.cpu0.commit.committedOps             518236674                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     157696637                       # Number of memory references committed
system.cpu0.commit.loads                     82471085                       # Number of loads committed
system.cpu0.commit.membars                    3674667                       # Number of memory barriers committed
system.cpu0.commit.branches                  98481561                       # Number of branches committed
system.cpu0.commit.fp_insts                    441323                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                475654398                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13113007                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       359364507     69.34%     69.34% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1076711      0.21%     69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           48368      0.01%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        50451      0.01%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.57% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       82471085     15.91%     85.48% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      75225552     14.52%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        518236674                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22100286                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1219379931                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1202193257                       # The number of ROB writes
system.cpu0.timesIdled                        4085117                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       28902258                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 52406782764                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  440797694                       # Number of Instructions Simulated
system.cpu0.committedOps                    518236674                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.571783                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.571783                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.636220                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.636220                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               678374188                       # number of integer regfile reads
system.cpu0.int_regfile_writes              399817042                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   838109                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  474946                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                123617139                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               124729221                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1203854145                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15290594                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10436084                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.972968                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          299959666                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10436596                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.741140                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   279.244386                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   232.728582                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.545399                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.454548                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1323106613                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1323106613                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77963580                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     80269235                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      158232815                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     65859782                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     67602913                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     133462695                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       205959                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       194953                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       400912                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       173450                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       151834                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       325284                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1750606                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1727963                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3478569                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2015132                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1995479                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4010611                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    143823362                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    147872148                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       291695510                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    144029321                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    148067101                       # number of overall hits
system.cpu0.dcache.overall_hits::total      292096422                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6244351                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6201364                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12445715                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6561247                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6087286                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12648533                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       674350                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604184                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1278534                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       611409                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       625543                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1236952                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       321165                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       325705                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       646870                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            5                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     12805598                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     12288650                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      25094248                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     13479948                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     12892834                       # number of overall misses
system.cpu0.dcache.overall_misses::total     26372782                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109268778000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112129743000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 221398521000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 284664585056                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 269956494563                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 554621079619                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43595846266                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  47989893688                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  91585739954                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4328541000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4603645500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   8932186500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       235000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       208500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       443500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 393933363056                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 382086237563                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 776019600619                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 393933363056                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 382086237563                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 776019600619                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     84207931                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     86470599                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    170678530                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     72421029                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73690199                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146111228                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       880309                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       799137                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1679446                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       784859                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       777377                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1562236                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2071771                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2053668                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4125439                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2015139                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1995484                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4010623                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    156628960                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    160160798                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    316789758                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    157509269                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    160959935                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    318469204                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.074154                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.071716                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.072919                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.090599                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.082606                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.086568                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.766038                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.756046                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.761283                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.779005                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.804684                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791783                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.155020                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158597                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156800                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.081758                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.076727                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.079214                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085582                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.080100                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.082811                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17498.820614                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18081.464497                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17789.136341                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43385.744365                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44347.595063                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43848.648663                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71303.900116                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76717.178017                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 74041.466406                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13477.623651                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14134.402297                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13808.317745                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33571.428571                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        41700                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 36958.333333                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30762.590162                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.612904                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30924.202256                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29223.655986                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29635.550847                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29425.018590                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     88195384                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       113546                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3493866                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1091                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.242921                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   104.075160                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8003169                       # number of writebacks
system.cpu0.dcache.writebacks::total          8003169                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3436866                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3393684                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6830550                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5461090                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5053042                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10514132                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3543                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3329                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         6872                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       197755                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       200626                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       398381                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8897956                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8446726                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17344682                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8897956                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8446726                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17344682                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2807485                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2807680                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5615165                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1100157                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1034244                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2134401                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       660963                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       593397                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1254360                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       607866                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       622214                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1230080                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       123410                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       125079                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       248489                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            5                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3907642                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3841924                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7749566                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4568605                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4435321                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      9003926                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16017                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17661                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14689                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19007                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        30706                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        36668                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  48229998000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  49964907000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98194905000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  50851143254                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  48166542964                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  99017686218                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  13581281500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11177477000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24758758500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42782526766                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47168374188                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89950900954                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1714638000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1879552500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3594190500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       228000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       203500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       431500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99081141254                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  98131449964                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 197212591218                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112662422754                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 109308926964                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 221971349718                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2884316000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3346437000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6230753000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2757806500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3449966491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207772991                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5642122500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6796403491                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12438525991                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033340                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032470                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032899                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015191                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014035                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014608                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.750831                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.742547                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746889                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.774491                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.800402                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787384                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059567                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060905                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060233                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024948                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023988                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024463                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029005                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027555                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028273                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17179.075935                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17795.798310                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17487.447831                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46221.714950                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46571.740290                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46391.323007                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20547.718254                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18836.423170                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19738.160098                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70381.509685                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75807.317399                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73126.057617                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13893.833563                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15026.922985                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14464.183525                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32571.428571                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        40700                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35958.333333                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25355.736594                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25542.267355                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25448.211063                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24660.136465                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24645.099411                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24652.729234                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180078.416682                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189481.739426                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185009.590831                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187746.374838                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181510.311517                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184228.780597                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183746.580473                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185349.718856                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184619.081411                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         15974128                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921242                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          168806839                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         15974640                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.567176                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      23708267500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   281.088545                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   230.832697                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.549001                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.450845                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        201986364                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       201986364                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     83405429                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     85401410                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      168806839                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     83405429                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     85401410                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       168806839                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     83405429                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     85401410                       # number of overall hits
system.cpu0.icache.overall_hits::total      168806839                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8594272                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8610485                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17204757                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8594272                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8610485                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17204757                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8594272                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8610485                       # number of overall misses
system.cpu0.icache.overall_misses::total     17204757                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115674670362                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116624708317                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 232299378679                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 115674670362                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 116624708317                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 232299378679                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 115674670362                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 116624708317                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 232299378679                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     91999701                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     94011895                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    186011596                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     91999701                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     94011895                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    186011596                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     91999701                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     94011895                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    186011596                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093416                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091589                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092493                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093416                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091589                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092493                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093416                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091589                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092493                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13459.507724                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13544.499330                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13502.043573                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13459.507724                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13544.499330                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13502.043573                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13459.507724                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13544.499330                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13502.043573                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       130388                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             8896                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.656924                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     15974128                       # number of writebacks
system.cpu0.icache.writebacks::total         15974128                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       611973                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       618016                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1229989                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       611973                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       618016                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1229989                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       611973                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       618016                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1229989                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7982299                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      7992469                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     15974768                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      7982299                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      7992469                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     15974768                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      7982299                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      7992469                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     15974768                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102168974407                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102903128872                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 205072103279                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102168974407                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102903128872                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 205072103279                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102168974407                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102903128872                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 205072103279                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085880                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.085880                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086764                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.085016                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.085880                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12837.250799                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12837.250799                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12799.442167                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12875.011323                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12837.250799                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups              130968102                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         88970124                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5750252                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            89023495                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               63858591                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            71.732289                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16978119                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            186369                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   886500                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               886500                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16614                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        90854                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       546971                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       339529                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2635.682077                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15582.194898                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-32767       331369     97.60%     97.60% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-65535         5485      1.62%     99.21% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-98303          837      0.25%     99.46% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-131071          574      0.17%     99.63% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-163839          696      0.20%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::163840-196607          183      0.05%     99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-229375           92      0.03%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::229376-262143           51      0.02%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-294911          111      0.03%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::294912-327679           44      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-360447           21      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::360448-393215            9      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-425983            6      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::425984-458751           19      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-491519           24      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::491520-524287            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       339529                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       415382                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23662.319263                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 19025.805885                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 20147.084285                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       405553     97.63%     97.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7307      1.76%     99.39% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1720      0.41%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          155      0.04%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          425      0.10%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          150      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           57      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287           14      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       415382                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 346321236644                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.073903                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.674380                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 345291497644     99.70%     99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    564895000      0.16%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    201129000      0.06%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    122101500      0.04%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     48136500      0.01%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     26097000      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     27118000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     32649000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      7117000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       414500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43        28000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47        21500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51        30000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55         2000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 346321236644                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        90854     84.54%     84.54% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        16614     15.46%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       107468                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       886500                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       886500                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       107468                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       107468                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       993968                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   104053210                       # DTB read hits
system.cpu1.dtb.read_misses                    608792                       # DTB read misses
system.cpu1.dtb.write_hits                   81022913                       # DTB write hits
system.cpu1.dtb.write_misses                   277708                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1101                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21005                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   55258                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      175                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  8900                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    55921                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               104662002                       # DTB read accesses
system.cpu1.dtb.write_accesses               81300621                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        185076123                       # DTB hits
system.cpu1.dtb.misses                         886500                       # DTB misses
system.cpu1.dtb.accesses                    185962623                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   108383                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               108383                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3055                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        74203                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        15086                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        93297                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1942.152481                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 12371.477981                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        92174     98.80%     98.80% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          584      0.63%     99.42% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303          102      0.11%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071          130      0.14%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839          211      0.23%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           45      0.05%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375           16      0.02%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143           14      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            6      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        93297                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        92344                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29998.852118                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25024.825336                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23447.205445                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        47315     51.24%     51.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535        42742     46.29%     97.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          660      0.71%     98.24% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071           85      0.09%     98.33% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839          956      1.04%     99.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607          338      0.37%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           49      0.05%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           41      0.04%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           83      0.09%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679           32      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215           20      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        92344                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 303371540184                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     1.809423                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0   -245466797852    -80.91%    -80.91% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   548762837036    180.89%     99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       65136000      0.02%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        8157000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4        1504000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         507000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6         155000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::7          42000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 303371540184                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        74203     96.05%     96.05% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         3055      3.95%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        77258                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       108383                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       108383                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        77258                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        77258                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       185641                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    94245746                       # ITB inst hits
system.cpu1.itb.inst_misses                    108383                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1101                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21005                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    522                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   41537                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   202136                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                94354129                       # ITB inst accesses
system.cpu1.itb.hits                         94245746                       # DTB hits
system.cpu1.itb.misses                         108383                       # DTB misses
system.cpu1.itb.accesses                     94354129                       # DTB accesses
system.cpu1.numCycles                       688244310                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         242823548                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     582789507                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  130968102                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          80836710                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    401946219                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13110617                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2820679                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               23345                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             5607                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      5329468                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       177594                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         4339                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 94019463                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3524085                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  43192                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         659685833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.033819                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.287421                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               515917584     78.21%     78.21% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                18016869      2.73%     80.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                18269669      2.77%     83.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13353344      2.02%     85.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                27714525      4.20%     89.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 8994456      1.36%     91.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9703502      1.47%     92.77% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8398741      1.27%     94.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                39317143      5.96%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           659685833                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.190293                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.846777                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               197914756                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            338110902                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                105437320                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13046087                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5174542                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19519920                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1400536                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             636170059                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4304353                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5174542                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               205322358                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31076264                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     254971917                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                110916625                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             52221607                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             621253009                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents               123804                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               2084188                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1933644                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              33372173                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3863                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          594055023                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            953160447                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       734477449                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           779699                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            499665654                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                94389369                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14450095                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      12489155                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 72603024                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           100339444                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           85180632                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13386925                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14275413                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 590006738                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           14504084                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                589818158                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           830847                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       79048188                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     50610611                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        352346                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    659685833                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.894089                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.635498                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          430142670     65.20%     65.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           95209085     14.43%     79.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           43103455      6.53%     86.17% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           30774369      4.67%     90.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           22787863      3.45%     94.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           16081687      2.44%     96.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10870686      1.65%     98.38% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6433091      0.98%     99.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4282927      0.65%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      659685833                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2991282     25.77%     25.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 24682      0.21%     25.98% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   3126      0.03%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     26.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4685148     40.36%     66.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3902762     33.62%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            399989408     67.82%     67.82% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1473233      0.25%     68.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                67059      0.01%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                153      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   4      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         70210      0.01%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           106137364     17.99%     86.08% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           82080680     13.92%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             589818158                       # Type of FU issued
system.cpu1.iq.rate                          0.856990                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11607000                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019679                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1850695958                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        683728270                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    568714201                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1064038                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            529691                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       473676                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             600857355                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 567803                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4685307                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     15994035                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        20483                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       710355                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      8709901                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3868542                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      7450104                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5174542                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               16661499                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             12204142                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          604643269                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1738208                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            100339444                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            85180632                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12202242                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                236266                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents             11879435                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        710355                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2616920                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2284300                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4901220                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            583187166                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            104040866                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5756605                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       132447                       # number of nop insts executed
system.cpu1.iew.exec_refs                   185065127                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               108200674                       # Number of branches executed
system.cpu1.iew.exec_stores                  81024261                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.847355                       # Inst execution rate
system.cpu1.iew.wb_sent                     570418733                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    569187877                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                281309683                       # num instructions producing a value
system.cpu1.iew.wb_consumers                488305636                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.827014                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.576093                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       79095788                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14151738                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4369211                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    646199938                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.813158                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.817106                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    455330275     70.46%     70.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     92773758     14.36%     84.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     32833911      5.08%     89.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15287498      2.37%     92.27% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10781023      1.67%     93.93% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6487132      1.00%     94.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      6078607      0.94%     95.88% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3894706      0.60%     96.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     22733028      3.52%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    646199938                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           447366409                       # Number of instructions committed
system.cpu1.commit.committedOps             525462634                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     160816140                       # Number of memory references committed
system.cpu1.commit.loads                     84345409                       # Number of loads committed
system.cpu1.commit.membars                    3627931                       # Number of memory barriers committed
system.cpu1.commit.branches                  99847042                       # Number of branches committed
system.cpu1.commit.fp_insts                    454333                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                482598910                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13134163                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       363400914     69.16%     69.16% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1135062      0.22%     69.37% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           50467      0.01%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.38% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        60009      0.01%     69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.40% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       84345409     16.05%     85.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      76470731     14.55%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        525462634                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             22733028                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1224126418                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1222625233                       # The number of ROB writes
system.cpu1.timesIdled                        4106530                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       28558477                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 48790405544                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  447366409                       # Number of Instructions Simulated
system.cpu1.committedOps                    525462634                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.538435                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.538435                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.650011                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.650011                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               687757037                       # number of integer regfile reads
system.cpu1.int_regfile_writes              406838676                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   842941                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  528902                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                124631004                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               125817612                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1199807572                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14264439                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             47828500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               344500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25445500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            40141500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           565650665                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115458                       # number of replacements
system.iocache.tags.tagsinuse               10.418706                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13100979262000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.907316                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.511389                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.369207                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.281962                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651169                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1684461016                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1689547016                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13867464649                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13867464649                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1684461016                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1689898016                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1684461016                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1689898016                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 191133.667990                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190909.267345                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130010.731353                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130010.731353                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 191133.667990                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190884.221846                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 191133.667990                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190884.221846                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         36071                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3608                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.997506                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1243811016                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1247047016                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8534264649                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8534264649                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1243811016                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1247248016                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1243811016                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1247248016                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141133.667990                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140909.267345                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80010.731353                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80010.731353                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 141133.667990                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140884.221846                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 141133.667990                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140884.221846                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1326476                       # number of replacements
system.l2c.tags.tagsinuse                65296.669801                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49454623                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1388892                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    35.607249                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              22398666000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35546.103483                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   178.339981                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   269.475913                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3715.302647                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    10815.708045                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   174.213795                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   257.428239                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3587.286900                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10752.810798                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.542390                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002721                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004112                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.056691                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.165035                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002658                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003928                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.054738                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.164075                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996348                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          319                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62097                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          318                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          533                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2767                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53561                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004868                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.947525                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                439122291                       # Number of tag accesses
system.l2c.tags.data_accesses               439122291                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       514243                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       181851                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       527161                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       198547                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1421802                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      8003169                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         8003169                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     15970717                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        15970717                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            5001                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4885                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9886                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             3                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           822179                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           770643                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1592822                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       7938357                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       7943580                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15881937                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3437833                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3369062                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6806895                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       367734                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       352789                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           720523                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        514243                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        181851                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             7938357                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4260012                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        527161                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        198547                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             7943580                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4139705                       # number of demand (read+write) hits
system.l2c.demand_hits::total                25703456                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       514243                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       181851                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            7938357                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4260012                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       527161                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       198547                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            7943580                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4139705                       # number of overall hits
system.l2c.overall_hits::total               25703456                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2145                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2004                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2360                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2181                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8690                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         18258                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17747                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             36005                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         260277                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         247111                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             507388                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        43808                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        48703                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           92511                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       148467                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       150955                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         299422                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       240132                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       269423                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         509555                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2145                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2004                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             43808                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            408744                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2360                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2181                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             48703                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            398066                       # number of demand (read+write) misses
system.l2c.demand_misses::total                908011                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2145                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2004                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            43808                       # number of overall misses
system.l2c.overall_misses::cpu0.data           408744                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2360                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2181                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            48703                       # number of overall misses
system.l2c.overall_misses::cpu1.data           398066                       # number of overall misses
system.l2c.overall_misses::total               908011                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    293614000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    277549000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    323397500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    301955500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1196516000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    743529500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    730917000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1474446500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       162000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       242500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  38883503000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  37010921500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  75894424500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   5934536000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   6603261498                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total  12537797498                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  20945380000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  21208112000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  42153492000                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  37279503000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  41775388000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  79054891000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    293614000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    277549000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5934536000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  59828883000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    323397500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    301955500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6603261498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  58219033500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    131782229998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    293614000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    277549000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5934536000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  59828883000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    323397500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    301955500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6603261498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  58219033500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   131782229998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       516388                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       183855                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       529521                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       200728                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1430492                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      8003169                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      8003169                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     15970717                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     15970717                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23259                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22632                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45891                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            12                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1082456                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1017754                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2100210                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      7982165                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      7992283                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      15974448                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3586300                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3520017                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7106317                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       607866                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       622212                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1230078                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       516388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       183855                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         7982165                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4668756                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       529521                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       200728                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         7992283                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4537771                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            26611467                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       516388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       183855                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        7982165                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4668756                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       529521                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       200728                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        7992283                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4537771                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           26611467                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004154                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.010900                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004457                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.010865                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006075                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.784986                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784155                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.784576                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.400000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.333333                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.240450                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.242800                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.241589                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005488                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006094                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005791                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041398                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042885                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.042135                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.395041                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.433008                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.414246                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004154                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.010900                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005488                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.087549                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004457                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.010865                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.006094                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.087723                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.034121                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004154                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.010900                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005488                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.087549                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004457                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.010865                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.006094                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.087723                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.034121                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 136882.983683                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138497.504990                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137032.838983                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138448.188904                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 137688.837745                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 40723.491072                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41185.383445                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 40951.159561                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        81000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        40250                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        60625                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149392.773852                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149774.479890                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 149578.674506                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135466.946676                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135582.233086                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135527.639935                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141077.680562                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140492.941605                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140782.881685                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155245.877268                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155055.017575                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 155144.961780                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136882.983683                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138497.504990                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135466.946676                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 146372.504551                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137032.838983                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138448.188904                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135582.233086                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146254.725347                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145132.856318                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136882.983683                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138497.504990                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135466.946676                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 146372.504551                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137032.838983                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138448.188904                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135582.233086                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146254.725347                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145132.856318                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1119014                       # number of writebacks
system.l2c.writebacks::total                  1119014                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           12                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           33                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                77                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           13                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data            8                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker           12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           33                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data              8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                100                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker           12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           33                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data             8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               100                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2133                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1980                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2352                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2148                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8613                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        18258                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17747                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        36005                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       260277                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       247111                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        507388                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        43807                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        48702                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        92509                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       148454                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       150947                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       299401                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       240132                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       269423                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       509555                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2133                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1980                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        43807                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       408731                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2352                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2148                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        48702                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       398058                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           907911                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2133                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1980                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        43807                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       408731                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2352                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2148                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        48702                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       398058                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          907911                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16017                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17661                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54324                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        14689                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19007                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        30706                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        36668                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88020                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    270686000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    254940500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    298834000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    276536500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1100997000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1291996000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1255623500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2547619500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       142000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       142500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       284500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36280733000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  34539811500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  70820544500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   5496440000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6116229998                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total  11612669998                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  19459483000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  19697560000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  39157043000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  34878183000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  39081158000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  73959341000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    270686000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    254940500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5496440000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  55740216000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    298834000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    276536500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6116229998                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  54237371500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 122691254498                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    270686000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    254940500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5496440000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  55740216000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    298834000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    276536500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6116229998                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  54237371500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 122691254498                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2684009000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3125579500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8125838998                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2588818000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3229788498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5818606498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5272827000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6355367998                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13944445496                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004131                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010769                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.010701                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006021                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.784986                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784155                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.784576                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.240450                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.242800                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.241589                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005791                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041395                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.042882                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042132                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.395041                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.433008                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.414246                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004131                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.010769                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.087546                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.010701                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.087721                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034117                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004131                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.010769                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005488                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.087546                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004442                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.010701                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006094                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.087721                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034117                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127829.676071                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70763.281849                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70751.310081                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70757.380919                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        71000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        71250                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71125                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139392.773852                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139774.479890                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 139578.674506                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125530.164611                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131080.893745                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130493.219474                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130784.609938                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.877268                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145055.017575                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145144.961780                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136373.840007                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136254.946515                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135135.772667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125469.445522                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136373.840007                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125584.780871                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136254.946515                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135135.772667                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167572.516701                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176976.360342                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149581.013880                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176241.949758                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169926.263903                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172679.442604                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171719.761610                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173321.915512                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 158423.602545                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54324                       # Transaction distribution
system.membus.trans_dist::ReadResp             463697                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1225644                       # Transaction distribution
system.membus.trans_dist::CleanEvict           212879                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36939                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36943                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1016012                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1016012                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        409373                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4278076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4407714                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342018                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342018                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4749732                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    163572972                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    163744670                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7253184                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7253184                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               170997854                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2815                       # Total snoops (count)
system.membus.snoop_fanout::samples           3097878                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3097878    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3097878                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113853500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5460502                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8296545910                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7735775396                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          227455723                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     53686542                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     27275171                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         4479                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2151                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2151                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            2028951                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25110801                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33696                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33696                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9228831                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     15970717                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2648270                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45894                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45906                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2100210                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2100210                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      15974768                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7115167                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1336742                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1230078                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47961225                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31535681                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       914731                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2490388                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              82902025                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2045811904                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1101659806                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3076664                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8367272                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3158915646                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2102692                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         30077408                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027456                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.163407                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               29251611     97.25%     97.25% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 825797      2.75%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           30077408                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        51459246454                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1450396                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24008829328                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14504682071                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         530598551                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1447405469                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16329                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------