path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.408461                       # Number of seconds simulated
sim_ticks                                51408461373000                       # Number of ticks simulated
final_tick                               51408461373000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 195616                       # Simulator instruction rate (inst/s)
host_op_rate                                   229875                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11322692573                       # Simulator tick rate (ticks/s)
host_mem_usage                                 696388                       # Number of bytes of host memory used
host_seconds                                  4540.30                       # Real time elapsed on the host
sim_insts                                   888155433                       # Number of instructions simulated
sim_ops                                    1043703833                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       142656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       137152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          3491584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         41406368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       143936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       139584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3767424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         42881448                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        438400                       # Number of bytes read from this memory
system.physmem.bytes_read::total             92548552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      3491584                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3767424                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7259008                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78363136                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78383716                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2229                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2143                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             54556                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            646983                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2249                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2181                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             58866                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            670027                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6850                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1446084                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1224424                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1226997                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2775                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2668                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               67918                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              805439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2800                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2715                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               73284                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              834132                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8528                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1800259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          67918                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          73284                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             141203                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1524324                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                400                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1524724                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1524324                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2775                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2668                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              67918                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             805439                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2800                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2715                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              73284                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             834532                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8528                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3324983                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1446084                       # Number of read requests accepted
system.physmem.writeReqs                      1226997                       # Number of write requests accepted
system.physmem.readBursts                     1446084                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1226997                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 92503744                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     45632                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78384064                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  92548552                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78383716                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      713                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               88572                       # Per bank write bursts
system.physmem.perBankRdBursts::1               91936                       # Per bank write bursts
system.physmem.perBankRdBursts::2               86142                       # Per bank write bursts
system.physmem.perBankRdBursts::3               85794                       # Per bank write bursts
system.physmem.perBankRdBursts::4               86883                       # Per bank write bursts
system.physmem.perBankRdBursts::5               96343                       # Per bank write bursts
system.physmem.perBankRdBursts::6               89494                       # Per bank write bursts
system.physmem.perBankRdBursts::7               87879                       # Per bank write bursts
system.physmem.perBankRdBursts::8               83471                       # Per bank write bursts
system.physmem.perBankRdBursts::9              112607                       # Per bank write bursts
system.physmem.perBankRdBursts::10              93875                       # Per bank write bursts
system.physmem.perBankRdBursts::11              93808                       # Per bank write bursts
system.physmem.perBankRdBursts::12              88268                       # Per bank write bursts
system.physmem.perBankRdBursts::13              91281                       # Per bank write bursts
system.physmem.perBankRdBursts::14              84984                       # Per bank write bursts
system.physmem.perBankRdBursts::15              84034                       # Per bank write bursts
system.physmem.perBankWrBursts::0               75348                       # Per bank write bursts
system.physmem.perBankWrBursts::1               77371                       # Per bank write bursts
system.physmem.perBankWrBursts::2               73838                       # Per bank write bursts
system.physmem.perBankWrBursts::3               75932                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75756                       # Per bank write bursts
system.physmem.perBankWrBursts::5               80933                       # Per bank write bursts
system.physmem.perBankWrBursts::6               75453                       # Per bank write bursts
system.physmem.perBankWrBursts::7               77252                       # Per bank write bursts
system.physmem.perBankWrBursts::8               72443                       # Per bank write bursts
system.physmem.perBankWrBursts::9               79503                       # Per bank write bursts
system.physmem.perBankWrBursts::10              78639                       # Per bank write bursts
system.physmem.perBankWrBursts::11              80056                       # Per bank write bursts
system.physmem.perBankWrBursts::12              76299                       # Per bank write bursts
system.physmem.perBankWrBursts::13              79068                       # Per bank write bursts
system.physmem.perBankWrBursts::14              73755                       # Per bank write bursts
system.physmem.perBankWrBursts::15              73105                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          38                       # Number of times write queue was full causing retry
system.physmem.totGap                    51408460130000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1446069                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1224424                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    664932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    398664                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    216465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    159288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       882                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       608                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       572                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1228                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       757                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       375                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      375                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      208                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      143                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      142                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      129                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      120                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       794                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       780                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       765                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       758                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      762                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      756                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    16854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    31810                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    61337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    72394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    72889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    73918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    75976                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    75696                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    81917                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    79068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    92468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   101068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    77598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    81385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    73598                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      573                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      336                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      259                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      111                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       92                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       563019                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      303.519817                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.962282                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     332.070466                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         224938     39.95%     39.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       128250     22.78%     62.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        55139      9.79%     72.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        26598      4.72%     77.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        23698      4.21%     81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13004      2.31%     83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13485      2.40%     86.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9030      1.60%     87.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        68877     12.23%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         563019                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         69941                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.665075                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      231.098088                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          69936     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           69941                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         69941                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.511202                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.923338                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.360496                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                37      0.05%      0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                29      0.04%      0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               15      0.02%      0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              59      0.08%      0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           66137     94.56%     94.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1542      2.20%     96.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             224      0.32%     97.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             273      0.39%     97.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              66      0.09%     97.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              90      0.13%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             208      0.30%     98.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              42      0.06%     98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             345      0.49%     98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              68      0.10%     98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              33      0.05%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              68      0.10%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             312      0.45%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              25      0.04%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              24      0.03%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             113      0.16%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             171      0.24%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             4      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            25      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             7      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           69941                       # Writes before turning the bus around for reads
system.physmem.totQLat                    42029385276                       # Total ticks spent queuing
system.physmem.totMemAccLat               69130091526                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7226855000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29078.61                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47828.61                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.80                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.15                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.08                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1187061                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    920040                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.13                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.12                       # Row buffer hit rate for writes
system.physmem.avgGap                     19231912.59                       # Average gap between requests
system.physmem.pageHitRate                      78.91                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2145112200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1170448125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5561735400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3965001840                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3357750617520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1242334329840                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29755308399000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34368235643925                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.532696                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49500352455310                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1716641420000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    191465063440                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2111311440                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1152005250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5712111600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3971384640                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3357750617520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1241846921700                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29755735950000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34368280302150                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.533565                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49501052297586                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1716641420000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    190767036414                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst         1088                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1024                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2148                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst         1088                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1024                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2112                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           17                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           21                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           20                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               42                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           21                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           20                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           41                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           21                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           20                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              42                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              131317234                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         89033308                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5711784                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            89061890                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               64034993                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.899432                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17159386                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            186222                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   882165                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               882165                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16962                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        90283                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       541135                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       341030                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2470.671202                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14842.312664                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       338635     99.30%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         1231      0.36%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          836      0.25%     99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          125      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679          123      0.04%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           27      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751           22      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287           27      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       341030                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       406695                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23181.687751                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18594.894940                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 20266.186322                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       397583     97.76%     97.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         6749      1.66%     99.42% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607         1620      0.40%     99.82% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          124      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          348      0.09%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          158      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           81      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           17      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       406695                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 362445074540                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.202763                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.718091                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 361444437540     99.72%     99.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    559911000      0.15%     99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    188863000      0.05%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    117378000      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     44663000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     25341500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     26888500      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     30794500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      6481000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       299000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        11000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47         3000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51         3500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 362445074540                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        90283     84.18%     84.18% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        16962     15.82%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       107245                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       882165                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       882165                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       107245                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       107245                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       989410                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   104764153                       # DTB read hits
system.cpu0.dtb.read_misses                    607812                       # DTB read misses
system.cpu0.dtb.write_hits                   82241693                       # DTB write hits
system.cpu0.dtb.write_misses                   274353                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1109                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21084                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    563                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   55854                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      162                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9058                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    56832                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               105371965                       # DTB read accesses
system.cpu0.dtb.write_accesses               82516046                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        187005846                       # DTB hits
system.cpu0.dtb.misses                         882165                       # DTB misses
system.cpu0.dtb.accesses                    187888011                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   108290                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               108290                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         3192                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        74908                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14795                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        93495                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1790.395208                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 11668.511629                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        92494     98.93%     98.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          513      0.55%     99.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303           98      0.10%     99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071          116      0.12%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839          207      0.22%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           24      0.03%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375           17      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143           10      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            8      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::425984-458751            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        93495                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        92895                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29889.315894                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24974.829894                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 23485.865012                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        49009     52.76%     52.76% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535        41574     44.75%     97.51% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          612      0.66%     98.17% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071           79      0.09%     98.26% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839         1038      1.12%     99.37% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607          333      0.36%     99.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           46      0.05%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143           56      0.06%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911           94      0.10%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679           13      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447           15      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            9      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983           12      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        92895                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 289428770008                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.837978                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -242453514464    -83.77%    -83.77% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   531809766472    183.74%     99.97% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       64887000      0.02%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        6499500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         871000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5         248000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6          12500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 289428770008                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        74908     95.91%     95.91% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         3192      4.09%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        78100                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       108290                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       108290                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        78100                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        78100                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       186390                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    94461785                       # ITB inst hits
system.cpu0.itb.inst_misses                    108290                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1109                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21084                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    563                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   41856                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   202434                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                94570075                       # ITB inst accesses
system.cpu0.itb.hits                         94461785                       # DTB hits
system.cpu0.itb.misses                         108290                       # DTB misses
system.cpu0.itb.accesses                     94570075                       # DTB accesses
system.cpu0.numCycles                       692991159                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         244811791                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     585398201                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  131317234                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          81194379                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    404384012                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13047908                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2817091                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               21621                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             5789                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      5286158                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       175205                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         3136                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 94240840                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3527611                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  42921                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         664028482                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.032942                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.287290                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               519576745     78.25%     78.25% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                18052759      2.72%     80.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                18229592      2.75%     83.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13406945      2.02%     85.73% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                28061689      4.23%     89.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 8964232      1.35%     91.31% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9738895      1.47%     92.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8312010      1.25%     94.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                39685615      5.98%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           664028482                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.189493                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.844741                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               199609312                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            340272761                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                105735491                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13276963                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5131471                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19616175                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1412684                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             640319872                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4351333                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5131471                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               207083748                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               31652470                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     258696093                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                111398501                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             50063478                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             625547022                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                86953                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               2120320                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1651060                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              31054223                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            4011                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          597792979                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            961356441                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       739385367                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           793267                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            505102127                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                92690852                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          14931756                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      12960965                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 74096600                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           100382456                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           86370742                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13395217                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14366752                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 594049171                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           14966536                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                595443977                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           833379                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       77816816                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     49417916                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        356669                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    664028482                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.896715                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.636729                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          431629347     65.00%     65.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           97195183     14.64%     79.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           43390380      6.53%     86.17% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           30835149      4.64%     90.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           23006785      3.46%     94.28% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           16163925      2.43%     96.72% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10905989      1.64%     98.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6533904      0.98%     99.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4367820      0.66%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      664028482                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                3037620     25.70%     25.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 25191      0.21%     25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2899      0.02%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.93% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4781762     40.45%     66.39% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3973331     33.61%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               44      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            403794947     67.81%     67.81% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1402722      0.24%     68.05% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                64715      0.01%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 26      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               1      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         70887      0.01%     68.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           106816149     17.94%     86.01% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           83294486     13.99%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             595443977                       # Type of FU issued
system.cpu0.iq.rate                          0.859237                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11820804                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019852                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1866487578                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        687019560                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    573922610                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1083041                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            536746                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       483014                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             606686496                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 578241                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4705214                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     15648573                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        20037                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       735656                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      8693789                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3938518                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      7949396                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5131471                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               16124670                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles             13736061                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          609148290                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1755735                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            100382456                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            86370742                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          12679523                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                224965                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents             13426906                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        735656                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2579656                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2261003                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             4840659                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            588863732                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            104752148                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5709737                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       132583                       # number of nop insts executed
system.cpu0.iew.exec_refs                   186992207                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               108909859                       # Number of branches executed
system.cpu0.iew.exec_stores                  82240059                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.849742                       # Inst execution rate
system.cpu0.iew.wb_sent                     575604648                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    574405624                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                283543762                       # num instructions producing a value
system.cpu0.iew.wb_consumers                491943015                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.828879                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.576375                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       77856968                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       14609867                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4319026                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    650724527                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.816319                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.818422                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    457095790     70.24%     70.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     94826206     14.57%     84.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     32956684      5.06%     89.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     15335469      2.36%     92.24% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10858481      1.67%     93.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6641395      1.02%     94.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6158141      0.95%     95.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3955723      0.61%     96.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22896638      3.52%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    650724527                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           451838462                       # Number of instructions committed
system.cpu0.commit.committedOps             531198891                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     162410836                       # Number of memory references committed
system.cpu0.commit.loads                     84733883                       # Number of loads committed
system.cpu0.commit.membars                    3641724                       # Number of memory barriers committed
system.cpu0.commit.branches                 100706106                       # Number of branches committed
system.cpu0.commit.fp_insts                    463962                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                487973755                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13314640                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       367585865     69.20%     69.20% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1092900      0.21%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           48363      0.01%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        60927      0.01%     69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.43% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       84733883     15.95%     85.38% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      77676953     14.62%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        531198891                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22896638                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1233051269                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1231435060                       # The number of ROB writes
system.cpu0.timesIdled                        4157054                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       28962677                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 49016383217                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  451838462                       # Number of Instructions Simulated
system.cpu0.committedOps                    531198891                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.533714                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.533714                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.652012                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.652012                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               694247819                       # number of integer regfile reads
system.cpu0.int_regfile_writes              410288637                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   858111                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  534016                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                125553876                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               126720582                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1210004868                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              14749855                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10444529                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.973029                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          299923189                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10445041                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.714410                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2716190500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   311.726470                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   200.246559                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.608841                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.391107                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          160                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1323036221                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1323036221                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80376534                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     77850212                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      158226746                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     68530103                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     64898072                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     133428175                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204436                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       196967                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       401403                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       172773                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       151726                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       324499                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1729648                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1752691                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3482339                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2010788                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2000716                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4011504                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    148906637                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    142748284                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       291654921                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    149111073                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    142945251                       # number of overall hits
system.cpu0.dcache.overall_hits::total      292056324                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6171666                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6278457                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12450123                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6360667                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6298405                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12659072                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       645106                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       634374                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1279480                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       599720                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       638706                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1238426                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       340434                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       305579                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       646013                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            7                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            4                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     12532333                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     12576862                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      25109195                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     13177439                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     13211236                       # number of overall misses
system.cpu0.dcache.overall_misses::total     26388675                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106407110000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 114810221500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 221217331500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 285277450532                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 269428801874                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 554706252406                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  43269391250                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  48260807056                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  91530198306                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4661773000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4281307000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   8943080000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       231500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       191500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       423000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 391684560532                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 384239023374                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 775923583906                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 391684560532                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 384239023374                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 775923583906                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     86548200                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     84128669                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    170676869                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74890770                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     71196477                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146087247                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       849542                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       831341                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1680883                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       772493                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       790432                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1562925                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2070082                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2058270                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4128352                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2010795                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2000720                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4011515                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    161438970                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    155325146                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    316764116                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    162288512                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    156156487                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    318444999                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071309                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074629                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.072946                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.084933                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.088465                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.086654                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759357                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.763073                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.761195                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.776344                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.808047                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792377                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.164454                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148464                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.156482                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000002                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.077629                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.080971                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.079268                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.081198                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.084603                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.082867                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17241.229516                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18286.375379                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17768.284819                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44850.241418                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42777.306616                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43818.871747                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72149.321767                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 75560.284475                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73908.492155                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13693.617559                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14010.475196                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13843.498505                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33071.428571                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        47875                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 38454.545455                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31253.922197                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30551.263373                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30901.969733                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29723.875825                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29084.260048                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29403.658346                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     88263884                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       112957                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3497847                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1120                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    25.233775                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets   100.854464                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8006090                       # number of writebacks
system.cpu0.dcache.writebacks::total          8006090                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3375063                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3454629                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6829692                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5283356                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5238971                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10522327                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3446                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3675                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         7121                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       210975                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       187747                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       398722                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8658419                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8693600                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17352019                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8658419                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8693600                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17352019                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2796603                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2823828                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5620431                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1077311                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1059434                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2136745                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       632117                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       623037                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1255154                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       596274                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       635031                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1231305                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       129459                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       117832                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       247291                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            7                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3873914                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3883262                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7757176                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4506031                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4506299                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      9012330                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        15173                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        18510                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33683                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14392                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        19307                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33699                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        29565                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        37817                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67382                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  47767699000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  50570666500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  98338365500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  51048745765                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  47967542154                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  99016287919                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  12938219500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11970277000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  24908496500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  42479134250                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  47413708556                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  89892842806                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1851393500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1735514500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3586908000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       224500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       187500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       412000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  98816444765                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  98538208654                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 197354653419                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111754664265                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110508485654                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 222263149919                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2756867500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3474155500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6231023000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2706893000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3501005491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6207898491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5463760500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6975160991                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12438921491                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032313                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033566                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032930                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014385                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014880                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014626                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.744068                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.749436                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746723                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.771883                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.803397                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787821                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.062538                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.057248                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059901                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000002                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023996                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025001                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024489                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027766                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028858                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028301                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17080.614946                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17908.550556                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17496.587984                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47385.337906                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45276.574241                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46339.777521                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20468.077112                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19212.786721                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19844.972410                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71240.963466                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74663.612573                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73006.154288                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14301.002634                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14728.719703                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.806079                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32071.428571                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        46875                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37454.545455                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25508.166873                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25375.112123                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25441.559328                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24801.130810                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24523.114346                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24662.118444                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181695.610624                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187690.734738                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184990.143396                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188083.171206                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181333.479619                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184216.104068                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184805.022831                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184445.117037                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184603.031833                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         16002915                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.921323                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          168727471                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         16003427                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.543209                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      23708267500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   280.765706                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   231.155617                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.548371                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.451476                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999846                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        201964404                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       201964404                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     85532749                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     83194722                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      168727471                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     85532749                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     83194722                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       168727471                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     85532749                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     83194722                       # number of overall hits
system.cpu0.icache.overall_hits::total      168727471                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8694942                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8538418                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17233360                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8694942                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8538418                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17233360                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8694942                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8538418                       # number of overall misses
system.cpu0.icache.overall_misses::total     17233360                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116564920862                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116224713334                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 232789634196                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 116564920862                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 116224713334                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 232789634196                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 116564920862                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 116224713334                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 232789634196                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     94227691                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     91733140                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    185960831                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     94227691                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     91733140                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    185960831                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     94227691                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     91733140                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    185960831                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.092276                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.093079                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.092672                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.092276                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.093079                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.092672                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.092276                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.093079                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.092672                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13406.060772                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13611.972772                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13508.081662                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13406.060772                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13611.972772                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13508.081662                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13406.060772                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.972772                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13508.081662                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs       124982                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             8393                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.891219                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     16002915                       # number of writebacks
system.cpu0.icache.writebacks::total         16002915                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       618920                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       610867                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1229787                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       618920                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       610867                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1229787                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       618920                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       610867                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1229787                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8076022                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      7927551                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     16003573                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      8076022                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      7927551                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     16003573                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      8076022                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      7927551                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     16003573                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20646                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20646                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102996587403                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102473648883                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 205470236286                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102996587403                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102473648883                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 205470236286                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102996587403                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102473648883                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 205470236286                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2636383000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1675493000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    960890000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2636383000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.085708                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.086420                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086059                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.085708                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.086420                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.086059                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.085708                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.086420                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.086059                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12753.381232                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12926.268009                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12839.022654                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12753.381232                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12926.268009                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12839.022654                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12753.381232                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12926.268009                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12839.022654                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups              128216560                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         87052179                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5647036                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            87531901                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               62765206                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            71.705521                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               16746465                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            188086                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   886664                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               886664                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        16465                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        89324                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       548056                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       338608                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2680.249728                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15884.122714                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       335881     99.19%     99.19% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1416      0.42%     99.61% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          912      0.27%     99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          152      0.04%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679          149      0.04%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           41      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           27      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287           24      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::720896-786431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       338608                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       414311                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23113.131199                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18566.304673                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 20214.309005                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       405108     97.78%     97.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         6775      1.64%     99.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607         1700      0.41%     99.82% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          115      0.03%     99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679          357      0.09%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215          138      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           86      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823           23      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::655360-720895            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       414311                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 341299530060                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.159336                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.721695                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 340284229060     99.70%     99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    551479000      0.16%     99.86% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    203508500      0.06%     99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    121654000      0.04%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     47328500      0.01%     99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     25233500      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     25945000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     34128500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      5458500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       539500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43        14000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47         6000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51         6000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 341299530060                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        89325     84.44%     84.44% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        16465     15.56%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       105790                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       886664                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       886664                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       105790                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       105790                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       992454                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   101829672                       # DTB read hits
system.cpu1.dtb.read_misses                    610637                       # DTB read misses
system.cpu1.dtb.write_hits                   78493819                       # DTB write hits
system.cpu1.dtb.write_misses                   276027                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1099                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21345                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    494                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   53264                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      214                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  9173                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    54344                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               102440309                       # DTB read accesses
system.cpu1.dtb.write_accesses               78769846                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        180323491                       # DTB hits
system.cpu1.dtb.misses                         886664                       # DTB misses
system.cpu1.dtb.accesses                    181210155                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   102782                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               102782                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         2883                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68745                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        14394                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        88388                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1935.822736                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 12537.694172                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        87864     99.41%     99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          223      0.25%     99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607          254      0.29%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           26      0.03%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679           12      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215            6      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        88388                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        86022                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29627.804515                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24484.599023                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 24553.065811                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        83801     97.42%     97.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          633      0.74%     98.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607         1356      1.58%     99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           58      0.07%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679          124      0.14%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           30      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           13      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            5      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        86022                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 285462324712                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     1.863931                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0   -246539938456    -86.37%    -86.37% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   531932332168    186.34%     99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       61889000      0.02%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        6735500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         960500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5         221000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6         125000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 285462324712                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        68745     95.98%     95.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         2883      4.02%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        71628                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       102782                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       102782                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71628                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71628                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       174410                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    91967963                       # ITB inst hits
system.cpu1.itb.inst_misses                    102782                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1099                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21345                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    494                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   39701                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   205263                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                92070745                       # ITB inst accesses
system.cpu1.itb.hits                         91967963                       # DTB hits
system.cpu1.itb.misses                         102782                       # DTB misses
system.cpu1.itb.accesses                     92070745                       # DTB accesses
system.cpu1.numCycles                       688789566                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         239433402                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     569353182                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  128216560                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          79511671                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    405943168                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               12894098                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2616962                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               25257                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             5725                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      5490519                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       162267                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         4008                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 91740705                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3476633                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  41341                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         660128083                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.009568                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.262441                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               519338149     78.67%     78.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                17657421      2.67%     81.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                17720975      2.68%     84.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13023211      1.97%     86.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                27851950      4.22%     90.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 8753673      1.33%     91.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9450814      1.43%     92.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8261049      1.25%     94.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                38070841      5.77%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           660128083                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.186148                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.826600                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               194262443                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            345472686                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                102025852                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13293227                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5071579                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19043746                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1394530                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             620472933                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4297557                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5071579                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               201685746                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               31240093                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     261429717                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                107754222                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             52944105                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             605820743                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents               130951                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               2142931                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               2140614                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              33385135                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3753                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          580698698                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            936110112                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       716711881                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           767618                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            488837378                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                91861315                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          14967870                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      13038182                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 74719709                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            97839319                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           82555667                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13435403                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14269542                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 574617477                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15094560                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                575613551                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           822312                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       77207090                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     49700091                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        361677                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    660128083                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.871973                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.612023                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          433148093     65.62%     65.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           96441838     14.61%     80.23% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           42095455      6.38%     86.60% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           30017553      4.55%     91.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           22180461      3.36%     94.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           15486932      2.35%     96.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10578992      1.60%     98.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6132384      0.93%     99.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4046375      0.61%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      660128083                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                2899692     25.45%     25.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 23212      0.20%     25.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   2493      0.02%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               1      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.68% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4727772     41.50%     67.18% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3739545     32.82%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               87      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            390631647     67.86%     67.86% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1449252      0.25%     68.12% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                67728      0.01%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                 81      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                  18      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               4      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             25      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         58665      0.01%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.14% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           103885376     18.05%     86.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           79520645     13.81%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             575613551                       # Type of FU issued
system.cpu1.iq.rate                          0.835689                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11392715                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019792                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1822546817                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        667071123                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    554642407                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1023395                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            508279                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       454369                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             586459289                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 546890                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4569014                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     15724428                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        20010                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       670978                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      8558712                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3761249                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      7804669                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5071579                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               16680640                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             12329901                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          589846063                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1702837                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             97839319                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            82555667                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12741950                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                233925                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents             12007104                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        670978                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2558274                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2229598                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4787872                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            569204299                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            101821264                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5535672                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       134026                       # number of nop insts executed
system.cpu1.iew.exec_refs                   180319145                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               105773243                       # Number of branches executed
system.cpu1.iew.exec_stores                  78497881                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.826383                       # Inst execution rate
system.cpu1.iew.wb_sent                     556304876                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    555096776                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                274163162                       # num instructions producing a value
system.cpu1.iew.wb_consumers                476408431                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.805902                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.575479                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       77255744                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14732883                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4271292                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    646929445                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.792211                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.788945                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    457763793     70.76%     70.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     93973346     14.53%     85.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     32152826      4.97%     90.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     14713797      2.27%     92.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10604817      1.64%     94.17% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6244010      0.97%     95.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5818154      0.90%     96.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3733305      0.58%     96.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     21925397      3.39%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    646929445                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           436316971                       # Number of instructions committed
system.cpu1.commit.committedOps             512504942                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     156111845                       # Number of memory references committed
system.cpu1.commit.loads                     82114890                       # Number of loads committed
system.cpu1.commit.membars                    3660763                       # Number of memory barriers committed
system.cpu1.commit.branches                  97634182                       # Number of branches committed
system.cpu1.commit.fp_insts                    435169                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                470255893                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            12926033                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       355174724     69.30%     69.30% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1118155      0.22%     69.52% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           50641      0.01%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.53% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        49535      0.01%     69.54% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.54% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.54% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       82114890     16.02%     85.56% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      73996955     14.44%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        512504942                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             21925397                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1210740079                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1192741700                       # The number of ROB writes
system.cpu1.timesIdled                        4053845                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       28661483                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 52418384154                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  436316971                       # Number of Instructions Simulated
system.cpu1.committedOps                    512504942                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.578645                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.578645                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.633455                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.633455                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               671693836                       # number of integer regfile reads
system.cpu1.int_regfile_writes              396256302                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   829382                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  475398                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                122695419                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               123792123                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1193620211                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              14812328                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40298                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40298                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353738                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492168                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             47816000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               344500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25477500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            40153500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567153724                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147714000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115458                       # number of replacements
system.iocache.tags.tagsinuse               10.431703                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115474                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13100979259000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.538083                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.893621                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221130                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.430851                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651981                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
system.iocache.tags.data_accesses             1039650                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8813                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8853                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8813                       # number of overall misses
system.iocache.overall_misses::total             8853                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1703214286                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1708300286                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13410969438                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13410969438                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1703214286                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1708651286                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1703214286                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1708651286                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8813                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8853                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8813                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8853                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 193261.577896                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 193028.280904                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125730.981756                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125730.981756                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 193261.577896                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 193002.517339                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 193261.577896                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 193002.517339                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         35415                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3508                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.095496                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8813                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8850                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8813                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8853                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8813                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8853                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1262564286                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1265800286                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8072705642                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8072705642                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1262564286                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1266001286                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1262564286                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1266001286                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143261.577896                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 143028.280904                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75683.507481                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75683.507481                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 143261.577896                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 143002.517339                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 143261.577896                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 143002.517339                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1326374                       # number of replacements
system.l2c.tags.tagsinuse                65265.362084                       # Cycle average of tags in use
system.l2c.tags.total_refs                   49524083                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1389631                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    35.638298                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              22398666000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35423.869586                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   183.395025                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   263.757590                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3339.523943                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    11653.727077                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   182.196722                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   269.878356                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3963.200555                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9985.813228                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.540525                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002798                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.004025                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.050957                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.177822                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002780                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.004118                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.060474                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.152371                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995870                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          308                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62949                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          307                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          120                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          578                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2748                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5097                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54406                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004700                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.960526                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                439713882                       # Number of tag accesses
system.l2c.tags.data_accesses               439713882                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       520227                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       197797                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       519049                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       183181                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1420254                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      8006090                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         8006090                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     15999481                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        15999481                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            4949                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4988                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9937                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 7                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           795643                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           798642                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1594285                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       8034471                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       7876086                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          15910557                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3408054                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3401749                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6809803                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       357336                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       365120                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           722456                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        520227                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        197797                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             8034471                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4203697                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        519049                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        183181                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             7876086                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4200391                       # number of demand (read+write) hits
system.l2c.demand_hits::total                25734899                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       520227                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       197797                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            8034471                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4203697                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       519049                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       183181                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            7876086                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4200391                       # number of overall hits
system.l2c.overall_hits::total               25734899                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2237                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2174                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2264                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2211                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8886                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         18116                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17819                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35935                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         264137                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         244077                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             508214                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        41467                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        51358                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           92825                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       144591                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       156861                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         301452                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       238938                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       269909                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         508847                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2237                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2174                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             41467                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            408728                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2264                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2211                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             51358                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            400938                       # number of demand (read+write) misses
system.l2c.demand_misses::total                911377                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2237                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2174                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            41467                       # number of overall misses
system.l2c.overall_misses::cpu0.data           408728                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2264                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2211                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            51358                       # number of overall misses
system.l2c.overall_misses::cpu1.data           400938                       # number of overall misses
system.l2c.overall_misses::total               911377                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    313111500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    298352500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    315325500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    307098500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     1233888000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    722693000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    684141500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1406834500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       158500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        81000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       239500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  39472429000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  36507990000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  75980419000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   5607923500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   6982923498                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total  12590846998                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  20362337000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  22036669000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  42399006000                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  37115268500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  41857446500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  78972715000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    313111500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    298352500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   5607923500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  59834766000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    315325500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    307098500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6982923498                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  58544659000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    132204159998                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    313111500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    298352500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   5607923500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  59834766000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    315325500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    307098500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6982923498                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  58544659000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   132204159998                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       522464                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       199971                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       521313                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       185392                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1429140                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      8006090                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      8006090                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     15999481                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     15999481                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23065                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22807                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45872                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            7                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1059780                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1042719                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2102499                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      8075938                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      7927444                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      16003382                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3552645                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3558610                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7111255                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       596274                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       635029                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1231303                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       522464                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       199971                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         8075938                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4612425                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       521313                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       185392                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         7927444                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4601329                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            26646276                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       522464                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       199971                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        8075938                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4612425                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       521313                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       185392                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        7927444                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4601329                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           26646276                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004282                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.010872                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004343                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011926                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006218                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.785432                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781295                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.783375                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.285714                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.500000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.363636                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.249238                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.234077                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.241719                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005135                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.006479                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005800                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.040700                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.044079                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.042391                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.400718                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.425034                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.413259                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004282                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.010872                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005135                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.088615                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004343                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.011926                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.006479                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.087135                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.034203                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004282                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.010872                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005135                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.088615                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004343                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.011926                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.006479                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.087135                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.034203                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 139969.378632                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137236.660534                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 139278.047703                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138895.748530                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 138857.528697                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39892.525944                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38393.933442                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 39149.422569                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79250                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        40500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        59875                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 149439.226613                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149575.707666                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 149504.773580                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135238.225577                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135965.643094                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135640.689448                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140827.140002                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140485.327774                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140649.277497                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155334.306389                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155079.847282                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 155199.333002                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139969.378632                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137236.660534                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135238.225577                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 146392.627860                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139278.047703                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138895.748530                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135965.643094                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146019.232400                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145059.794133                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139969.378632                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137236.660534                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135238.225577                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 146392.627860                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139278.047703                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138895.748530                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135965.643094                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146019.232400                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145059.794133                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1117794                       # number of writebacks
system.l2c.writebacks::total                  1117794                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker            8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           31                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker           15                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           30                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                84                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           15                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           21                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker            8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           31                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data              6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           30                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst              2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                107                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker            8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           31                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data             6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker           15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           30                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst             2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               107                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2229                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2143                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2249                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2181                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8802                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        18116                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17819                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35935                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       264137                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       244077                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        508214                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        41467                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        51356                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        92823                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       144585                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       156846                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       301431                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       238938                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       269909                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       508847                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2229                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2143                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        41467                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       408722                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2249                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2181                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        51356                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       400923                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           911270                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2229                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2143                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        41467                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       408722                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2249                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2181                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        51356                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       400923                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          911270                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        13120                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        15173                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         7526                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        18510                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54329                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        14392                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19307                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33699                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        13120                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        29565                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         7526                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        37817                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88028                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    289805500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    272929000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    291056002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    281669500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1135460002                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1231726000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1211533500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2443259500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       138500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       140500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       279000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  36831057004                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  34067216507                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  70898273511                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   5193253001                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   6469324002                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total  11662577003                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  18915611005                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  20466558002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  39382169007                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  34725887503                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  39158355006                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  73884242509                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    289805500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    272929000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   5193253001                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  55746668009                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    291056002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    281669500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   6469324002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  54533774509                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 123078479523                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    289805500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    272929000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   5193253001                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  55746668009                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    291056002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    281669500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   6469324002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  54533774509                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 123078479523                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2567133000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3242696000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8126079498                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2541338500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3277361498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5818699998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1472133000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5108471500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    844117498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   6520057498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13944779496                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004266                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.010717                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004314                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011764                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006159                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785432                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781295                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.783375                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.363636                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.249238                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.234077                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.241719                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005135                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.006478                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005800                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.040698                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.044075                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.042388                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.400718                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.425034                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.413259                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004266                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.010717                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005135                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.088613                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004314                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011764                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.006478                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.087132                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034199                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004266                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.010717                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005135                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.088613                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004314                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011764                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.006478                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.087132                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034199                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 129000.227448                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67991.057629                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67991.105000                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67991.081119                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69250                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70250                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69750                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139439.219057                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139575.693355                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 139504.762779                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125238.213543                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125970.169055                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125643.181140                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130826.925373                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130488.236882                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130650.692885                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145334.302216                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145079.841747                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145199.328106                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125238.213543                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136392.628753                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125970.169055                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136020.568810                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135062.582465                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125238.213543                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136392.628753                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125970.169055                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136020.568810                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135062.582465                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169190.865353                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175186.169638                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149571.674391                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176579.940245                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169749.909256                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172666.844654                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172787.806528                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172410.754370                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 158412.999228                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54329                       # Transaction distribution
system.membus.trans_dist::ReadResp             466235                       # Transaction distribution
system.membus.trans_dist::WriteReq              33699                       # Transaction distribution
system.membus.trans_dist::WriteResp             33699                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1224424                       # Transaction distribution
system.membus.trans_dist::CleanEvict           216307                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36790                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1016209                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1016209                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        411906                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6874                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4246337                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4375991                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237825                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237825                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4613816                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2148                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13748                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    163669548                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    163841278                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7262720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7262720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               171103998                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2667                       # Total snoops (count)
system.membus.snoop_fanout::samples           3100373                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3100373    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3100373                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113885000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               50156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5470002                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8294790249                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7676329675                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44628309                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             150                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              150                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     53748943                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     27300315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         4554                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2137                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2137                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            2032183                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25147760                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33699                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33699                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9230552                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     16002915                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2655847                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45875                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45886                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2102499                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2102499                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      16003573                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7120105                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1337967                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1231303                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48051162                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     31561925                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       916568                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2490426                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              83020081                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2049724352                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1102308286                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3082904                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8350216                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             3163465758                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2107044                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         30117798                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.027021                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.162144                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               29303991     97.30%     97.30% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 813807      2.70%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           30117798                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        51529807954                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1428891                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24051879645                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14516066687                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         531626613                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1449630863                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16333                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------