path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.321386                       # Number of seconds simulated
sim_ticks                                51321386217000                       # Number of ticks simulated
final_tick                               51321386217000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 134164                       # Simulator instruction rate (inst/s)
host_op_rate                                   157647                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7630777532                       # Simulator tick rate (ticks/s)
host_mem_usage                                 687808                       # Number of bytes of host memory used
host_seconds                                  6725.58                       # Real time elapsed on the host
sim_insts                                   902332774                       # Number of instructions simulated
sim_ops                                    1060266688                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       154240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       142464                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4107136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         45245848                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       165376                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       158016                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3334400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         43223216                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        435264                       # Number of bytes read from this memory
system.physmem.bytes_read::total             96965960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4107136                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3334400                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7441536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     82289920                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          82310500                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2410                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2226                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             64174                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            706974                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2584                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2469                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             52100                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            675368                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6801                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1515106                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1285780                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1288353                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3005                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2776                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               80028                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              881618                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          3222                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          3079                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               64971                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              842207                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8481                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1889387                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          80028                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          64971                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             144999                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1603424                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1603825                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1603424                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3005                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2776                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              80028                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             882019                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         3222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         3079                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              64971                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             842207                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8481                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3493212                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1515106                       # Number of read requests accepted
system.physmem.writeReqs                      1288353                       # Number of write requests accepted
system.physmem.readBursts                     1515106                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1288353                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 96901440                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     65344                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  82309952                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  96965960                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               82310500                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     1021                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         144011                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               91435                       # Per bank write bursts
system.physmem.perBankRdBursts::1               93225                       # Per bank write bursts
system.physmem.perBankRdBursts::2               89718                       # Per bank write bursts
system.physmem.perBankRdBursts::3               87919                       # Per bank write bursts
system.physmem.perBankRdBursts::4               92611                       # Per bank write bursts
system.physmem.perBankRdBursts::5              102433                       # Per bank write bursts
system.physmem.perBankRdBursts::6               93232                       # Per bank write bursts
system.physmem.perBankRdBursts::7               90056                       # Per bank write bursts
system.physmem.perBankRdBursts::8               87362                       # Per bank write bursts
system.physmem.perBankRdBursts::9              117909                       # Per bank write bursts
system.physmem.perBankRdBursts::10              95229                       # Per bank write bursts
system.physmem.perBankRdBursts::11              97284                       # Per bank write bursts
system.physmem.perBankRdBursts::12              90073                       # Per bank write bursts
system.physmem.perBankRdBursts::13             103730                       # Per bank write bursts
system.physmem.perBankRdBursts::14              91691                       # Per bank write bursts
system.physmem.perBankRdBursts::15              90178                       # Per bank write bursts
system.physmem.perBankWrBursts::0               77827                       # Per bank write bursts
system.physmem.perBankWrBursts::1               79309                       # Per bank write bursts
system.physmem.perBankWrBursts::2               76608                       # Per bank write bursts
system.physmem.perBankWrBursts::3               77829                       # Per bank write bursts
system.physmem.perBankWrBursts::4               80050                       # Per bank write bursts
system.physmem.perBankWrBursts::5               85847                       # Per bank write bursts
system.physmem.perBankWrBursts::6               79718                       # Per bank write bursts
system.physmem.perBankWrBursts::7               79449                       # Per bank write bursts
system.physmem.perBankWrBursts::8               76360                       # Per bank write bursts
system.physmem.perBankWrBursts::9               83802                       # Per bank write bursts
system.physmem.perBankWrBursts::10              81643                       # Per bank write bursts
system.physmem.perBankWrBursts::11              83145                       # Per bank write bursts
system.physmem.perBankWrBursts::12              78123                       # Per bank write bursts
system.physmem.perBankWrBursts::13              87627                       # Per bank write bursts
system.physmem.perBankWrBursts::14              79500                       # Per bank write bursts
system.physmem.perBankWrBursts::15              79256                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
system.physmem.totGap                    51321385112000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1515091                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1285780                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    688629                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    426852                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    228074                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    164413                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       987                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       543                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       541                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       875                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       956                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      461                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      194                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      156                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      128                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      109                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                       769                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                       755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                       746                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                       745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                       744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                       739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                       736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                       737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                       737                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                       735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                      736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                      734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                      728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                      722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                      723                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13812                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    16283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    29465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    62844                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    76168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    76695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    80163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    82135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    85619                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    84213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    87116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    83567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    96056                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   103672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    81346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    84582                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    77173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      316                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      255                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      248                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       37                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       590002                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      303.746442                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.840046                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     333.017877                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         235290     39.88%     39.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       136180     23.08%     62.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        56828      9.63%     72.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27605      4.68%     77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        24232      4.11%     81.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        13797      2.34%     83.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        13359      2.26%     85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9785      1.66%     87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        72926     12.36%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         590002                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         74241                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.393489                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      234.888851                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          74237     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::61440-63487            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           74241                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         74241                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.323218                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.863934                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.335765                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                39      0.05%      0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                11      0.01%      0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               20      0.03%      0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              65      0.09%      0.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           70112     94.44%     94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            1316      1.77%     96.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             568      0.77%     97.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             346      0.47%     97.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             342      0.46%     98.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             528      0.71%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             134      0.18%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              37      0.05%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              41      0.06%     99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              27      0.04%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              42      0.06%     99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              26      0.04%     99.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             396      0.53%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              32      0.04%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              46      0.06%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              38      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               9      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               5      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            24      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             4      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           74241                       # Writes before turning the bus around for reads
system.physmem.totQLat                    44116098728                       # Total ticks spent queuing
system.physmem.totMemAccLat               72505192478                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7570425000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       29137.13                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  47887.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.60                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.60                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.13                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1245847                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    964327                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.28                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.98                       # Row buffer hit rate for writes
system.physmem.avgGap                     18306451.11                       # Average gap between requests
system.physmem.pageHitRate                      78.93                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2222337600                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1212585000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5776859400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4125407760                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1232605432755                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29711598339000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34309604352555                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.524518                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49427675587817                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1713733840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    179976420183                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2238077520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1221173250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                6032956800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               4208474880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352063391040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1237235987925                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29707536448500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34310536509915                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.542681                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49420862619804                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1713733840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    186788845196                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst         1408                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total          2212                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst         1408                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total         2176                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           22                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           27                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               43                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           27                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           42                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           27                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              43                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              132571032                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         90050105                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          5878539                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            90490581                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               64975080                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            71.803142                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               17318147                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            190057                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   913008                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               913008                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        16692                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        92976                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       560771                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       352237                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2376.777567                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 13703.858808                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-32767       344408     97.78%     97.78% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-65535         5384      1.53%     99.31% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-98303          983      0.28%     99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::98304-131071          725      0.21%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-163839          276      0.08%     99.87% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::163840-196607          169      0.05%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-229375           94      0.03%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::229376-262143           47      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-294911           59      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::294912-327679           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-360447           14      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::360448-393215           25      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-425983           25      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::425984-458751            8      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-491519            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::491520-524287            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       352237                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       421207                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22517.986406                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18384.767938                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16267.103719                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       412281     97.88%     97.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8071      1.92%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          392      0.09%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          363      0.09%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           55      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           22      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            7      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       421207                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 353008884868                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.117411                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.682149                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 352021835868     99.72%     99.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7    541843500      0.15%     99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11    193463500      0.05%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15    118741500      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19     46634500      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23     24285000      0.01%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27     23543000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31     31748500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35      6046000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39       436000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43        56500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47        38500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51        27500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::52-55       185000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 353008884868                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        92977     84.78%     84.78% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        16692     15.22%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       109669                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       913008                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       913008                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       109669                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       109669                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total      1022677                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   104802286                       # DTB read hits
system.cpu0.dtb.read_misses                    628192                       # DTB read misses
system.cpu0.dtb.write_hits                   81730320                       # DTB write hits
system.cpu0.dtb.write_misses                   284816                       # DTB write misses
system.cpu0.dtb.flush_tlb                        1079                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   54383                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      188                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  9307                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    56122                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               105430478                       # DTB read accesses
system.cpu0.dtb.write_accesses               82015136                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        186532606                       # DTB hits
system.cpu0.dtb.misses                         913008                       # DTB misses
system.cpu0.dtb.accesses                    187445614                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                   102934                       # Table walker walks requested
system.cpu0.itb.walker.walksLong               102934                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2830                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69670                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        14211                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        88723                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1670.198257                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev  9993.098637                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767        87793     98.95%     98.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535          509      0.57%     99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303          243      0.27%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071           94      0.11%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839           34      0.04%     99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607           21      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143            1      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        88723                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        86711                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27827.271050                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23655.790569                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18399.370737                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        84751     97.74%     97.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1686      1.94%     99.68% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          179      0.21%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           53      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           20      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        86711                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 499035191932                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     1.085193                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0   -42443239012     -8.51%     -8.51% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   541415505444    108.49%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       55393500      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        6761000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         722500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5          48000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6            500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 499035191932                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        69670     96.10%     96.10% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         2830      3.90%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72500                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102934                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102934                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72500                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72500                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       175434                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    95094277                       # ITB inst hits
system.cpu0.itb.inst_misses                    102934                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                        1079                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              22185                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    501                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   40091                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   207907                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                95197211                       # ITB inst accesses
system.cpu0.itb.hits                         95094277                       # DTB hits
system.cpu0.itb.misses                         102934                       # DTB misses
system.cpu0.itb.accesses                     95197211                       # DTB accesses
system.cpu0.numCycles                       675702202                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles         244757501                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     589419880                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  132571032                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          82293227                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    391738714                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               13356245                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   2509355                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles               22606                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles             4900                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles      5469917                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       167540                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles         2725                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                 94868898                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              3621980                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  41300                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         651351111                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             1.059349                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.306953                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               505677761     77.64%     77.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                18279909      2.81%     80.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                18243298      2.80%     83.24% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                13516535      2.08%     85.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                28852465      4.43%     89.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                 8999693      1.38%     91.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                 9719421      1.49%     92.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                 8528805      1.31%     93.93% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                39533224      6.07%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           651351111                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.196197                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.872307                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               198764731                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            327769223                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                105831567                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             13682981                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5300378                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            19660361                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              1397395                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             643175990                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts              4312729                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5300378                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               206434504                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               26397501                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     257870314                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                111703786                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             43642083                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             627780362                       # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents                81911                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents               1880696                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents               1582827                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              24120192                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents            3699                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          601307944                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            969598831                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       742471294                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           750947                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            504947564                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                96360375                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          15500464                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      13524428                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 76866665                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           101145902                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           86060501                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads         13628383                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores        14576675                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 595266457                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           15567772                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                595602490                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued           860155                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       81220997                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     52302062                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        356361                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    651351111                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.914411                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.641831                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          416907124     64.01%     64.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1           99553383     15.28%     79.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2           43434757      6.67%     85.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           30928180      4.75%     90.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4           22872426      3.51%     94.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5           16003542      2.46%     96.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6           10950121      1.68%     98.36% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7            6425711      0.99%     99.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8            4275867      0.66%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      651351111                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu                2977313     25.58%     25.58% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 21726      0.19%     25.77% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                   2146      0.02%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc               1      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead               4737742     40.71%     66.50% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite              3899084     33.50%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               69      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            404218599     67.87%     67.87% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1425375      0.24%     68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                67506      0.01%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                 50      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         58410      0.01%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           106977397     17.96%     86.09% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           82855084     13.91%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             595602490                       # Type of FU issued
system.cpu0.iq.rate                          0.881457                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                   11638012                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.019540                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        1854047614                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        692214073                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    573874162                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1006644                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            498985                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       447097                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             606702343                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 538090                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         4757420                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     16585910                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        22662                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       668240                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      9092320                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      3863731                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      7820378                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5300378                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles               15293530                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              9669423                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          610970772                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts          1799898                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            101145902                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            86060501                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13228626                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                242900                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              9335617                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        668240                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       2719159                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      2323934                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5043093                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            588743474                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            104791307                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          5960112                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       136543                       # number of nop insts executed
system.cpu0.iew.exec_refs                   186525171                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               109265890                       # Number of branches executed
system.cpu0.iew.exec_stores                  81733864                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.871306                       # Inst execution rate
system.cpu0.iew.wb_sent                     575597633                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    574321259                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                283300170                       # num instructions producing a value
system.cpu0.iew.wb_consumers                492230600                       # num instructions consuming a value
system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate                      0.849962                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.575544                       # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts       81268346                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       15211411                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4500525                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    637573218                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.830670                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.824266                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    442173264     69.35%     69.35% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1     97173464     15.24%     84.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     33154077      5.20%     89.79% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     15182673      2.38%     92.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     10793922      1.69%     93.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      6469162      1.01%     94.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6019139      0.94%     95.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3912878      0.61%     96.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     22694639      3.56%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    637573218                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           450633299                       # Number of instructions committed
system.cpu0.commit.committedOps             529613227                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     161528172                       # Number of memory references committed
system.cpu0.commit.loads                     84559991                       # Number of loads committed
system.cpu0.commit.membars                    3687184                       # Number of memory barriers committed
system.cpu0.commit.branches                 100678778                       # Number of branches committed
system.cpu0.commit.fp_insts                    428537                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                486019598                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            13276351                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       366882155     69.27%     69.27% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1103700      0.21%     69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           50072      0.01%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        49128      0.01%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       84559991     15.97%     85.47% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      76968181     14.53%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        529613227                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             22694639                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1221719500                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1235563732                       # The number of ROB writes
system.cpu0.timesIdled                        4062222                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       24351091                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 46889510422                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  450633299                       # Number of Instructions Simulated
system.cpu0.committedOps                    529613227                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.499450                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.499450                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.666911                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.666911                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               694532138                       # number of integer regfile reads
system.cpu0.int_regfile_writes              409756453                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   813886                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  470480                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                126655644                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               127915254                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1202729248                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              15348526                       # number of misc regfile writes
system.cpu0.dcache.tags.replacements         10661519                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.983500                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          305118964                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10662031                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            28.617340                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       1659069500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   285.071495                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   226.912005                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.556780                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.443188                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          316                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1346452186                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1346452186                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     80589927                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     80681589                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      161271516                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     67520868                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     67884168                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     135405036                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       204627                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       201539                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       406166                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       174874                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       149966                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       324840                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1793684                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1773233                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3566917                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2041252                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2056052                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      4097304                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    148110795                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    148565757                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       296676552                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    148315422                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    148767296                       # number of overall hits
system.cpu0.dcache.overall_hits::total      297082718                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      6173656                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      6486433                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total     12660089                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      6585609                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      6413253                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total     12998862                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       647829                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       671589                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1319418                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       637368                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       603972                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1241340                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       307807                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       348230                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       656037                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            8                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            3                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           11                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     12759265                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data     12899686                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      25658951                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     13407094                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data     13571275                       # number of overall misses
system.cpu0.dcache.overall_misses::total     26978369                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  95102935500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  99484470500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 194587406000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227327993853                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 219936608514                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 447264602367                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  33983690404                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  32156071893                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  66139762297                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4002448500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4417133500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   8419582000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       243500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       108000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       351500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 322430929353                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 319421079014                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 641852008367                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 322430929353                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 319421079014                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 641852008367                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     86763583                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     87168022                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    173931605                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     74106477                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     74297421                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    148403898                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       852456                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       873128                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1725584                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       812242                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       753938                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1566180                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2101491                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2121463                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      4222954                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2041260                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2056055                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      4097315                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    160870060                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    161465443                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    322335503                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    161722516                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    162338571                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    324061087                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071155                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074413                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.072788                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.088867                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.086319                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.087591                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759956                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.769176                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.764621                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.784702                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.801090                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.792591                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.146471                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.164146                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.155350                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000004                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000003                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.079314                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079891                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.079603                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.082902                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.083599                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.083251                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15404.637949                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15337.315671                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15370.145186                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34518.902330                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34294.079543                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34407.981435                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53318.789779                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 53240.997750                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53280.940191                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13003.110715                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12684.528903                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12834.004789                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 30437.500000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        36000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 31954.545455                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25270.337230                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24761.926687                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25014.740796                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24049.277894                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23536.556367                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23791.357008                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs     66975280                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        45752                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs          3575735                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets           1017                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    18.730493                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    44.987217                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      8160945                       # number of writebacks
system.cpu0.dcache.writebacks::total          8160945                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3346545                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3573146                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      6919691                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5483385                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5330407                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total     10813792                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3566                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3327                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         6893                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       188282                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       213819                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       402101                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data      8829930                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data      8903553                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     17733483                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data      8829930                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data      8903553                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     17733483                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2827111                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2913287                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5740398                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1102224                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1082846                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2185070                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       638719                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       656171                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1294890                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       633802                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       600645                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234447                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       119525                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       134411                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253936                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            8                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           11                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3929335                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3996133                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7925468                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4568054                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4652304                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      9220358                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17396                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16284                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33680                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18911                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14786                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        36307                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        31070                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67377                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  43970285000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44965591500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  88935876500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39469232389                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  38108394120                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  77577626509                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10196891500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  11887921500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22084813000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  33197271404                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  31430048393                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  64627319797                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1640365500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1815773000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3456138500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       235500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       105000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       340500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83439517389                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83073985620                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 166513503009                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  93636408889                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  94961907120                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 188598316009                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3034885000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2806255000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5841140000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3049818991                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2643724500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5693543491                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6084703991                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5449979500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11534683491                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032584                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033422                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033004                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014874                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014574                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014724                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.749269                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.751518                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.750407                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.780312                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.796677                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.788190                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056876                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063358                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060132                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000004                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024426                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024749                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024588                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028246                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028658                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028453                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15553.080512                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15434.659029                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15492.980887                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35808.721629                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35192.810538                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35503.497146                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15964.597108                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18117.108955                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17055.358370                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52377.984613                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 52327.162289                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52353.255990                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13724.036812                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13509.110117                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13610.273849                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 29437.500000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        35000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30954.545455                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21235.022565                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20788.593778                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21009.926860                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20498.095883                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20411.801791                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20454.554586                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174458.783628                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172332.043724                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173430.522565                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161272.222040                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178799.168132                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168962.919281                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167590.381772                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175409.703894                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171196.157309                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         16142168                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.947517                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          172883065                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         16142680                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            10.709688                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      16340342500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   273.082606                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   238.864911                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.533364                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.466533                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999897                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           76                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        206401666                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       206401666                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     86191123                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     86691942                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      172883065                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     86191123                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     86691942                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       172883065                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     86191123                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     86691942                       # number of overall hits
system.cpu0.icache.overall_hits::total      172883065                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      8665288                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      8710490                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     17375778                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      8665288                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      8710490                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      17375778                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      8665288                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      8710490                       # number of overall misses
system.cpu0.icache.overall_misses::total     17375778                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 113689396380                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113502001896                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 227191398276                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 113689396380                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 113502001896                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 227191398276                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 113689396380                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 113502001896                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 227191398276                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     94856411                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     95402432                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    190258843                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     94856411                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     95402432                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    190258843                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     94856411                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     95402432                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    190258843                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.091352                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.091303                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.091327                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.091352                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.091303                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.091327                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.091352                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.091303                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.091327                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13120.094379                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13030.495632                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13075.178463                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13120.094379                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13030.495632                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13075.178463                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13120.094379                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13030.495632                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13075.178463                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs        86637                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs             7314                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.845365                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       615328                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       617627                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total      1232955                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       615328                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst       617627                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total      1232955                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       615328                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst       617627                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total      1232955                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8049960                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8092863                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     16142823                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      8049960                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      8092863                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     16142823                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      8049960                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      8092863                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     16142823                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12465                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         8175                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        20640                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12465                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         8175                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        20640                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 100646775925                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 100551252932                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 201198028857                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 100646775925                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 100551252932                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 201198028857                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 100646775925                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 100551252932                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 201198028857                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1598498000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    965827500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    632670500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   1598498000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.084847                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.084847                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.084865                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.084829                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.084847                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12463.621069                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12502.767209                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12424.682456                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12463.621069                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.branchPred.lookups              132830364                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         90187101                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          5886537                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            91288458                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               64898028                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            71.091165                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17334778                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            185732                       # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   905180                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               905180                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17142                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92306                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       553484                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       351696                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2321.493563                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13592.585679                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       349244     99.30%     99.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1804      0.51%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          390      0.11%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          114      0.03%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           67      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           32      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751           30      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            6      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       351696                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       414217                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22492.792425                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18361.243775                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16253.124731                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767       322417     77.84%     77.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        82857     20.00%     97.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303         6808      1.64%     99.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071         1275      0.31%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839          173      0.04%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607          198      0.05%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375          298      0.07%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           83      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           62      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679           12      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447           13      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       414217                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 326963093592                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.083701                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.672512                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 325992368092     99.70%     99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7    539476500      0.16%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11    187726500      0.06%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15    115407500      0.04%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19     46500000      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23     23809500      0.01%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27     21473500      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31     29946500      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35      5666000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39       571000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43        55000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47        32500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51        25000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55         4000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::56-59        32000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 326963093592                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        92306     84.34%     84.34% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        17142     15.66%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       109448                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       905180                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       905180                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109448                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109448                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total      1014628                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                   105776812                       # DTB read hits
system.cpu1.dtb.read_misses                    627964                       # DTB read misses
system.cpu1.dtb.write_hits                   81868125                       # DTB write hits
system.cpu1.dtb.write_misses                   277216                       # DTB write misses
system.cpu1.dtb.flush_tlb                        1087                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   55232                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      212                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  8920                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    54701                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses               106404776                       # DTB read accesses
system.cpu1.dtb.write_accesses               82145341                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        187644937                       # DTB hits
system.cpu1.dtb.misses                         905180                       # DTB misses
system.cpu1.dtb.accesses                    188550117                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                   106266                       # Table walker walks requested
system.cpu1.itb.walker.walksLong               106266                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3111                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        73302                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        14293                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        91973                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1630.543747                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  9941.577304                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767        90961     98.90%     98.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535          588      0.64%     99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303          258      0.28%     99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071           90      0.10%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839           38      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607           13      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375            7      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215            5      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::458752-491519            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::491520-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        91973                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        90706                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28271.216899                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24128.368541                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18525.575548                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        88461     97.52%     97.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1926      2.12%     99.65% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          212      0.23%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           62      0.07%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           21      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        90706                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 610372252128                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.878972                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.326581                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    73947141376     12.12%     12.12% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   536358552252     87.87%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       59179000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        6640000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4         645500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5          94000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 610372252128                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        73302     95.93%     95.93% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         3111      4.07%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        76413                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       106266                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total       106266                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        76413                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        76413                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       182679                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    95636263                       # ITB inst hits
system.cpu1.itb.inst_misses                    106266                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                        1087                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21316                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    568                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   41371                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   202868                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                95742529                       # ITB inst accesses
system.cpu1.itb.hits                         95636263                       # DTB hits
system.cpu1.itb.misses                         106266                       # DTB misses
system.cpu1.itb.accesses                     95742529                       # DTB accesses
system.cpu1.numCycles                       670348620                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles         245802953                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     590871754                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  132830364                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          82232806                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    386445016                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               13431293                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   2639306                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles               21635                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles             4572                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles      5276880                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       167481                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles         2239                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                 95410634                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              3652057                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  41964                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         647075459                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             1.068807                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.316374                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               501080801     77.44%     77.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                18371493      2.84%     80.28% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                18561867      2.87%     83.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                13401625      2.07%     85.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                28513625      4.41%     89.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                 9105805      1.41%     91.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                 9777924      1.51%     92.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                 8450851      1.31%     93.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                39811468      6.15%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           647075459                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.198151                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.881440                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               199983147                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            321798427                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                106352633                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             13609650                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5329449                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            19773591                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              1406143                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             644884461                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts              4323616                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5329449                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               207655640                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               26665473                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     252746187                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                112130376                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             42545968                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             629384575                       # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents                84102                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents               2156884                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents               1598140                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              23186474                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents            3948                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          602389573                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            968798649                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       744085505                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           803060                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            505488932                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                96900641                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          15182115                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      13209558                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 75938042                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads           101507501                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           86179777                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads         13679637                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores        14662477                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 596915130                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           15279603                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                597602438                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued           863336                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       81541272                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     52071117                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        356106                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    647075459                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.923544                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.649381                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          412751344     63.79%     63.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1           98711881     15.26%     79.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2           43578879      6.73%     85.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           31028755      4.80%     90.57% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4           23162473      3.58%     94.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5           16109238      2.49%     96.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6           10961200      1.69%     98.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7            6490260      1.00%     99.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8            4281429      0.66%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      647075459                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu                3038725     25.54%     25.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 25345      0.21%     25.76% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                   3128      0.03%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc               3      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.78% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead               4885830     41.07%     66.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite              3943683     33.15%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               46      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            405061818     67.78%     67.78% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1472658      0.25%     68.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                66179      0.01%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                 56      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             16      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             23      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         71237      0.01%     68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           107954973     18.06%     86.12% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           82975408     13.88%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             597602438                       # Type of FU issued
system.cpu1.iq.rate                          0.891480                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                   11896714                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.019907                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        1853948472                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        693931681                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    575193406                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1091913                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            542260                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       485773                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             608916098                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 583008                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         4685337                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     16615869                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        21909                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       749717                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      9068365                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      3952894                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      8300380                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5329449                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles               14829127                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles             10212979                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          612328593                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts          1790117                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts            101507501                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            86179777                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          12919930                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                237071                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              9891044                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        749717                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       2710919                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      2329182                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             5040101                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            590723670                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts            105766513                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          5987554                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       133860                       # number of nop insts executed
system.cpu1.iew.exec_refs                   187634979                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               109483047                       # Number of branches executed
system.cpu1.iew.exec_stores                  81868466                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.881219                       # Inst execution rate
system.cpu1.iew.wb_sent                     576950915                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    575679179                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                284156915                       # num instructions producing a value
system.cpu1.iew.wb_consumers                493402851                       # num instructions consuming a value
system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate                      0.858776                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.575913                       # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts       81583045                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       14923497                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4500070                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    633204147                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.838045                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.832186                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    438438352     69.24%     69.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1     96042056     15.17%     84.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     33088291      5.23%     89.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     15382536      2.43%     92.06% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     10958189      1.73%     93.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      6612249      1.04%     94.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      6082014      0.96%     95.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3902550      0.62%     96.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     22697910      3.58%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    633204147                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           451699475                       # Number of instructions committed
system.cpu1.commit.committedOps             530653461                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     162003044                       # Number of memory references committed
system.cpu1.commit.loads                     84891632                       # Number of loads committed
system.cpu1.commit.membars                    3738235                       # Number of memory barriers committed
system.cpu1.commit.branches                 100868221                       # Number of branches committed
system.cpu1.commit.fp_insts                    465542                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                487126697                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13297594                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       367411373     69.24%     69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1128741      0.21%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           49317      0.01%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        60944      0.01%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       84891632     16.00%     85.47% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      77111412     14.53%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        530653461                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             22697910                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1218827033                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1238367651                       # The number of ROB writes
system.cpu1.timesIdled                        4095381                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       23273161                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 54406850213                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  451699475                       # Number of Instructions Simulated
system.cpu1.committedOps                    530653461                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.484059                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.484059                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.673828                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.673828                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               696515100                       # number of integer regfile reads
system.cpu1.int_regfile_writes              411090108                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   864151                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  531144                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                126615327                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               127765048                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1196239956                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              15044847                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                40301                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40301                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230960                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353744                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334272                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492192                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           569059287                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147720000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115460                       # number of replacements
system.iocache.tags.tagsinuse               10.424672                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115476                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13093329887000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.544075                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.880598                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.221505                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.430037                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651542                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039677                       # Number of tag accesses
system.iocache.tags.data_accesses             1039677                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8816                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8853                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8816                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8856                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8816                       # number of overall misses
system.iocache.overall_misses::total             8856                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1614263059                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1619332059                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12613364228                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12613364228                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1614263059                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1619683059                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1614263059                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1619683059                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8816                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8853                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8816                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8856                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8816                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8856                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 183106.063861                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182913.369366                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118253.245969                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118253.245969                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 182891.040989                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 183106.063861                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 182891.040989                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         31017                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3459                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.967042                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106629                       # number of writebacks
system.iocache.writebacks::total               106629                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8816                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8853                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8816                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8856                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8816                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8856                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1173463059                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1176682059                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7280164228                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7280164228                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1173463059                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1176883059                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1173463059                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1176883059                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133106.063861                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132913.369366                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68253.245969                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68253.245969                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 133106.063861                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 132891.040989                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1395026                       # number of replacements
system.l2c.tags.tagsinuse                65295.492166                       # Cycle average of tags in use
system.l2c.tags.total_refs                   50144400                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1458293                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    34.385682                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              15281090500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   35597.818988                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   166.792374                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   227.419292                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3927.975659                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9604.860217                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   170.331373                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   255.084245                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3398.092398                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    11947.117619                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.543180                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002545                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003470                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.059936                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.146559                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002599                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003892                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.051851                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.182299                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996330                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          361                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62906                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          360                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          593                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2785                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5017                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54411                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.005508                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.959869                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                445809940                       # Number of tag accesses
system.l2c.tags.data_accesses               445809940                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       538533                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       183659                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       537301                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       193067                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1452560                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         8160945                       # number of Writeback hits
system.l2c.Writeback_hits::total              8160945                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            5106                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            5035                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10141                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data             2                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                 8                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           801127                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           795359                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1596486                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       7998143                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       8048835                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          16046978                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3426730                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3533561                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6960291                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       362301                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       359177                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           721478                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        538533                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        183659                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             7998143                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4227857                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        537301                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        193067                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             8048835                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4328920                       # number of demand (read+write) hits
system.l2c.demand_hits::total                26056315                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       538533                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       183659                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            7998143                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4227857                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       537301                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       193067                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            8048835                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4328920                       # number of overall hits
system.l2c.overall_hits::total               26056315                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2429                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2264                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2593                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2507                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 9793                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         18387                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         18174                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             36561                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         284361                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         270457                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             554818                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        51722                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        43961                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           95683                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       151868                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       164132                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         316000                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       271501                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       241468                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         512969                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2429                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2264                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             51722                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            436229                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2593                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2507                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             43961                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            434589                       # number of demand (read+write) misses
system.l2c.demand_misses::total                976294                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2429                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2264                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            51722                       # number of overall misses
system.l2c.overall_misses::cpu0.data           436229                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2593                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2507                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            43961                       # number of overall misses
system.l2c.overall_misses::cpu1.data           434589                       # number of overall misses
system.l2c.overall_misses::total               976294                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    212763500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    201130500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    229023500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    219290000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      862207500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    279221000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    285672000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    564893000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       160500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       240000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  28552328500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  27263762000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  55816090500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   4410990000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3717651000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   8128641000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  13488162000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  15070468500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  28558630500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  27681533000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  26039052000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  53720585000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    212763500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    201130500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   4410990000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  42040490500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    229023500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    219290000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3717651000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  42334230500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     93365569500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    212763500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    201130500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   4410990000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  42040490500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    229023500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    219290000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3717651000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  42334230500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    93365569500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       540962                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       185923                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       539894                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       195574                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1462353                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      8160945                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          8160945                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23493                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        23209                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           46702                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            8                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            11                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1085488                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1065816                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2151304                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      8049865                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      8092796                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      16142661                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3578598                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3697693                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      7276291                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       633802                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       600645                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1234447                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       540962                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       185923                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         8049865                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4664086                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       539894                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       195574                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         8092796                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4763509                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            27032609                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       540962                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       185923                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        8049865                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4664086                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       539894                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       195574                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        8092796                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4763509                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           27032609                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.006697                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782659                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783058                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782857                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.250000                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.333333                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.272727                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.261966                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.253756                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.257898                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006425                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005432                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005927                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042438                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.044388                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.043429                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.428369                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.402015                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.415546                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006425                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.093529                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005432                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.091233                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.036115                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.004490                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012177                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006425                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.093529                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004803                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.012819                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005432                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.091233                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.036115                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 88043.245175                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15185.783434                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15718.719049                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15450.698832                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        80250                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        80000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 100408.735727                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100806.272346                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 100602.522809                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85282.665017                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84567.025318                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 84953.868503                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88815.036742                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91819.197353                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 90375.412975                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 101957.388739                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107836.450379                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 104724.817679                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 96372.525669                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 95632.636788                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87593.042404                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88838.560071                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85282.665017                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 96372.525669                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88323.756267                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87471.080973                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84567.025318                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 97412.107762                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 95632.636788                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1179151                       # number of writebacks
system.l2c.writebacks::total                  1179151                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker           19                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           38                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker            9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           38                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               104                       # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           12                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker           19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker           38                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker            9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker           38                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                127                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker           19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker           38                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker            9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker           38                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               127                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2410                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2226                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2584                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2469                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            9689                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks         1116                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1116                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        18387                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        18174                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        36561                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       284361                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       270457                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        554818                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        51721                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        43961                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        95682                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       151858                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       164120                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       315978                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       271501                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       241468                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       512969                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2410                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2226                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        51721                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       436219                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2584                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2469                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        43961                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       434577                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           976167                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2410                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2226                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        51721                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       436219                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2584                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2469                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        43961                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       434577                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          976167                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        12465                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17396                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         8175                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16284                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        54320                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18911                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14786                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        12465                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        36307                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         8175                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        31070                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        88017                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    757696500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    381648500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    377184000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    758832500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       140500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       210000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  25708718500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  24559192000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  50267910500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   3893746000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   3278041000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   7171787000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  11968937500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13428627500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  25397565000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  24966523000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  23624372000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  48590895000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3893746000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  37677656000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   3278041000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  37987819500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  83594959000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    186939500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    176128500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3893746000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  37677656000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    202521000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    192107500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   3278041000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  37987819500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  83594959000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2817435000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2602704500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   6698691999                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2830764496                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2473673500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5304437996                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    772594499                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5648199496                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    505958000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5076378000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12003129995                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.006626                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.782659                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783058                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.782857                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.333333                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.272727                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.261966                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.253756                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.257898                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005927                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042435                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.044384                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043426                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.428369                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.402015                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.415546                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.036111                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.004455                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011973                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006425                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.093527                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004786                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012624                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005432                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.091230                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.036111                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 78201.723604                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20756.431174                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.044239                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.244660                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        70250                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        70000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90408.735727                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90806.272346                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 90602.522809                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74954.401037                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78816.641204                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81822.005240                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80377.637051                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 91957.388739                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97836.450379                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94724.817679                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77568.257261                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79123.315364                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75283.656542                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86373.257469                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        78375                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77807.816930                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74567.025318                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87413.322610                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 85635.919878                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 161958.783628                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159832.013019                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123319.072147                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149688.778806                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167298.356553                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157415.734220                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155567.782962                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 163385.194722                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 136372.859732                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54320                       # Transaction distribution
system.membus.trans_dist::ReadResp             484522                       # Transaction distribution
system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
system.membus.trans_dist::Writeback           1285780                       # Transaction distribution
system.membus.trans_dist::CleanEvict           222453                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            37353                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           37356                       # Transaction distribution
system.membus.trans_dist::ReadExReq           1066998                       # Transaction distribution
system.membus.trans_dist::ReadExResp          1066998                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        430202                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4492142                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4621788                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       342195                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       342195                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4963983                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    172016940                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    172188714                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7259520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7259520                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               179448234                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2724                       # Total snoops (count)
system.membus.snoop_fanout::samples           3239737                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 3239737    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             3239737                       # Request fanout histogram
system.membus.reqLayer0.occupancy           113920999                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               51156                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5444004                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8690318133                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         8114396828                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228917368                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.realview_io.osc_clcd.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_cpu.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_ddr.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock        25000                       # Clock period in ticks
system.realview.realview_io.osc_mcc.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.realview_io.osc_pxl.clock        42105                       # Clock period in ticks
system.realview.realview_io.osc_smb.clock        20000                       # Clock period in ticks
system.realview.realview_io.osc_sys.clock        16667                       # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.trans_dist::ReadReq            2074158                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          25494018                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          9446739                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict        18863436                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           46705                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            11                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          46716                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2151304                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2151304                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      16142823                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      7285144                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1341111                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1234447                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     48465856                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32213596                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       910891                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2571300                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              84161643                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1034451264                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1125904618                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3051976                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8646848                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2172054706                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         2184416                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         57389162                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.063529                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.243911                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               53743303     93.65%     93.65% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                3645859      6.35%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           57389162                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        36059386455                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1120500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       24257498228                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14835156686                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         529789657                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy        1493165292                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16399                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------