path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.824541                       # Number of seconds simulated
sim_ticks                                51824540977500                       # Number of ticks simulated
final_tick                               51824540977500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 636803                       # Simulator instruction rate (inst/s)
host_op_rate                                   748315                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            37012113234                       # Simulator tick rate (ticks/s)
host_mem_usage                                 715168                       # Number of bytes of host memory used
host_seconds                                  1400.21                       # Real time elapsed on the host
sim_insts                                   891654507                       # Number of instructions simulated
sim_ops                                    1047794539                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       127104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       129344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2579072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         24306544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       138752                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       130240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2657396                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         26223832                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        397184                       # Number of bytes read from this memory
system.physmem.bytes_read::total             56689468                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2579072                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2657396                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5236468                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     77843520                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          77864100                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1986                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2021                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             64583                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            379793                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2035                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             57644                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            409757                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6206                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                926193                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1216305                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1218878                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2453                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2496                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               49765                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              469016                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2677                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2513                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               51277                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              506012                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7664                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1093873                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          49765                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          51277                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             101042                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1502059                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1502456                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1502059                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2453                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2496                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              49765                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             469016                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2677                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2513                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              51277                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             506409                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7664                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2596329                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        926193                       # Number of read requests accepted
system.physmem.writeReqs                      1833424                       # Number of write requests accepted
system.physmem.readBursts                      926193                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1833424                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59238720                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     37632                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 114125056                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  56689468                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              117195044                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      588                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   50220                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          36075                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               58169                       # Per bank write bursts
system.physmem.perBankRdBursts::1               57047                       # Per bank write bursts
system.physmem.perBankRdBursts::2               56978                       # Per bank write bursts
system.physmem.perBankRdBursts::3               51307                       # Per bank write bursts
system.physmem.perBankRdBursts::4               56070                       # Per bank write bursts
system.physmem.perBankRdBursts::5               62899                       # Per bank write bursts
system.physmem.perBankRdBursts::6               54110                       # Per bank write bursts
system.physmem.perBankRdBursts::7               52791                       # Per bank write bursts
system.physmem.perBankRdBursts::8               52847                       # Per bank write bursts
system.physmem.perBankRdBursts::9              102886                       # Per bank write bursts
system.physmem.perBankRdBursts::10              57805                       # Per bank write bursts
system.physmem.perBankRdBursts::11              59371                       # Per bank write bursts
system.physmem.perBankRdBursts::12              53186                       # Per bank write bursts
system.physmem.perBankRdBursts::13              52009                       # Per bank write bursts
system.physmem.perBankRdBursts::14              46290                       # Per bank write bursts
system.physmem.perBankRdBursts::15              51840                       # Per bank write bursts
system.physmem.perBankWrBursts::0              107643                       # Per bank write bursts
system.physmem.perBankWrBursts::1              108842                       # Per bank write bursts
system.physmem.perBankWrBursts::2              112436                       # Per bank write bursts
system.physmem.perBankWrBursts::3              109534                       # Per bank write bursts
system.physmem.perBankWrBursts::4              114716                       # Per bank write bursts
system.physmem.perBankWrBursts::5              117944                       # Per bank write bursts
system.physmem.perBankWrBursts::6              106840                       # Per bank write bursts
system.physmem.perBankWrBursts::7              109826                       # Per bank write bursts
system.physmem.perBankWrBursts::8              110854                       # Per bank write bursts
system.physmem.perBankWrBursts::9              118905                       # Per bank write bursts
system.physmem.perBankWrBursts::10             115046                       # Per bank write bursts
system.physmem.perBankWrBursts::11             114249                       # Per bank write bursts
system.physmem.perBankWrBursts::12             112384                       # Per bank write bursts
system.physmem.perBankWrBursts::13             111972                       # Per bank write bursts
system.physmem.perBankWrBursts::14             104755                       # Per bank write bursts
system.physmem.perBankWrBursts::15             107258                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         141                       # Number of times write queue was full causing retry
system.physmem.totGap                    51824538352500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  883077                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1830851                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    891893                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     27772                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       277                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       434                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       548                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       466                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       744                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1849                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      101                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       48                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1570                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1527                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1502                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1457                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    57426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    60838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    91061                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                   116478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                   105808                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    96280                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    97400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    91891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    93113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    91599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    92000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    96823                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    95841                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    93430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                   103137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    95750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    92354                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    90761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     5397                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     5548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     7290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     7464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     6868                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     7069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     7549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     5718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     5353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     5228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     5156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     4122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     3748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     3811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     2828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     2228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     1124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      235                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       605479                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      286.324474                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     164.442500                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.472553                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         252649     41.73%     41.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       150060     24.78%     66.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        52055      8.60%     75.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27939      4.61%     79.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        19251      3.18%     82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12886      2.13%     85.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         9838      1.62%     86.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         9006      1.49%     88.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        71795     11.86%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         605479                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         88964                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        10.404208                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       91.787630                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          88960    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::21504-22527            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           88964                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         88964                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.044108                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.711925                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       17.727362                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15              349      0.39%      0.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31           86750     97.51%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47             775      0.87%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              22      0.02%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              52      0.06%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95             153      0.17%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111            193      0.22%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127           316      0.36%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143           104      0.12%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            25      0.03%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175            21      0.02%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            53      0.06%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            28      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            13      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             3      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             1      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271             4      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             7      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303            10      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             6      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             6      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351            10      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            22      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             6      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             2      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::432-447             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-463             4      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::464-479             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511             4      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-687             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::848-863             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           88964                       # Writes before turning the bus around for reads
system.physmem.totQLat                    11987590194                       # Total ticks spent queuing
system.physmem.totMemAccLat               29342683944                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4628025000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12951.09                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31701.09                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.14                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.20                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.09                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.26                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.43                       # Average write queue length when enqueuing
system.physmem.readRowHits                     697250                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1406079                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.33                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.85                       # Row buffer hit rate for writes
system.physmem.avgGap                     18779612.66                       # Average gap between requests
system.physmem.pageHitRate                      77.65                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2300840640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1255419000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3505093800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               5752820880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384927046800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1312402504095                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29943494064750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34653637789965                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.672359                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49812972038958                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730535300000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    281033227292                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2276580600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1242181875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3714586200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               5802341040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384927046800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1307965107960                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29947386517500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34653314361975                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.666118                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49819438757970                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730535300000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    274566508280                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   132927                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               132927                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20422                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        96268                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           16                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       132911                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         132911    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       132911                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       116706                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23749.820061                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 20399.632740                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 13626.974720                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       115779     99.21%     99.21% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          796      0.68%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           50      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           35      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           34      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215            9      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       116706                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  17050777148                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.002177                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0      -37117796     -0.22%     -0.22% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    17087894944    100.22%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  17050777148                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96268     82.50%     82.50% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        20422     17.50%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       116690                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       132927                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       132927                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       116690                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       116690                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       249617                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83832092                       # DTB read hits
system.cpu0.dtb.read_misses                    101357                       # DTB read misses
system.cpu0.dtb.write_hits                   76051604                       # DTB write hits
system.cpu0.dtb.write_misses                    31570                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51833                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21426                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    523                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   72699                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4640                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9921                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83933449                       # DTB read accesses
system.cpu0.dtb.write_accesses               76083174                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        159883696                       # DTB hits
system.cpu0.dtb.misses                         132927                       # DTB misses
system.cpu0.dtb.accesses                    160016623                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    78456                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                78456                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4330                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        68323                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        78456                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          78456    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        78456                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72653                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26725.888828                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23461.567658                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 16011.465624                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        35910     49.43%     49.43% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535        35653     49.07%     98.50% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          362      0.50%     99.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071          571      0.79%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839           12      0.02%     99.80% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607           51      0.07%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           22      0.03%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143           28      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911           22      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72653                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -294752296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -294752296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -294752296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        68323     94.04%     94.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4330      5.96%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72653                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        78456                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        78456                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72653                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72653                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       151109                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   446243730                       # ITB inst hits
system.cpu0.itb.inst_misses                     78456                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51833                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21426                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    523                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   53592                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               446322186                       # ITB inst accesses
system.cpu0.itb.hits                        446243730                       # DTB hits
system.cpu0.itb.misses                          78456                       # DTB misses
system.cpu0.itb.accesses                    446322186                       # DTB accesses
system.cpu0.numCycles                     51824649281                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  445966277                       # Number of instructions committed
system.cpu0.committedOps                    524229812                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            481463261                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                467774                       # Number of float alu accesses
system.cpu0.num_func_calls                   26556698                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     68063516                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   481463261                       # number of integer instructions
system.cpu0.num_fp_insts                       467774                       # number of float instructions
system.cpu0.num_int_register_reads          701970788                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         382111523                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              750606                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             404844                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           116882787                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          116605188                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    159874579                       # number of memory refs
system.cpu0.num_load_insts                   83829017                       # Number of load instructions
system.cpu0.num_store_insts                  76045562                       # Number of store instructions
system.cpu0.num_idle_cycles              50231597014.033707                       # Number of idle cycles
system.cpu0.num_busy_cycles              1593052266.966292                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.030739                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.969261                       # Percentage of idle cycles
system.cpu0.Branches                         99615402                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                363413760     69.28%     69.28% # Class of executed instruction
system.cpu0.op_class::IntMult                 1135542      0.22%     69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49216      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             60094      0.01%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::MemRead                83829017     15.98%     85.50% # Class of executed instruction
system.cpu0.op_class::MemWrite               76045562     14.50%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 524533192                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16327                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements         10196087                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.965694                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          309323716                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10196599                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.335969                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3500850250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   229.651609                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   282.314085                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.448538                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.551395                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          398                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           60                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1288720346                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1288720346                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     78289930                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     78118799                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      156408729                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72116454                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     72389955                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     144506409                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       198225                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       194517                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       392742                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       165535                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       168546                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       334081                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1870803                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1796237                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3667040                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2023404                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1945934                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3969338                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    150406384                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    150508754                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       300915138                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    150604609                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    150703271                       # number of overall hits
system.cpu0.dcache.overall_hits::total      301307880                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2655491                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2654704                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5310195                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1102314                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1104773                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2207087                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       646482                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       651674                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1298156                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       617789                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       615381                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total      1233170                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       153457                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       150527                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       303984                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3757805                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      3759477                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       7517282                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4404287                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      4411151                       # number of overall misses
system.cpu0.dcache.overall_misses::total      8815438                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41854028250                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42227875003                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  84081903253                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  32373542448                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33874267614                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  66247810062                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  16528493005                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  16264164501                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  32792657506                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2255480492                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2210676726                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4466157218                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       164000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  74227570698                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  76102142617                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 150329713315                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  74227570698                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  76102142617                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 150329713315                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80945421                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     80773503                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    161718924                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73218768                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73494728                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    146713496                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       844707                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       846191                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1690898                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       783324                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       783927                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1567251                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2024260                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1946764                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3971024                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2023405                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1945935                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3969340                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    154164189                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    154268231                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    308432420                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    155008896                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    155114422                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    310123318                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032806                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032866                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032836                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015055                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015032                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015044                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.765333                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.770126                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767732                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.788676                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.784998                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786836                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075809                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077322                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.076551                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000000                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024375                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024370                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.024373                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028413                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028438                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.028426                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15761.314292                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15906.811081                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15834.051904                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29368.712044                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30661.744643                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30015.948652                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 26754.268860                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 26429.422587                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 26592.162886                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14697.801286                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14686.247158                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.079906                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19752.906470                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20242.747227                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19997.881324                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16853.481778                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17252.218892                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17053.005570                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7866652                       # number of writebacks
system.cpu0.dcache.writebacks::total          7866652                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         7707                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         8547                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        16254                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10563                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        10564                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21127                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35866                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35610                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71476                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        18270                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        19111                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        37381                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        18270                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        19111                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        37381                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2647784                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2646157                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5293941                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1091751                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1094209                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2185960                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       645721                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       650689                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1296410                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       617789                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       615381                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1233170                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       117591                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       114917                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       232508                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3739535                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3740366                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7479901                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4385256                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4391055                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      8776311                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17713                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15993                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16112                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        17598                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33825                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        33591                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  37598794000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  37923223247                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  75522017247                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30337029302                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31768716886                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62105746188                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   9761049258                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10401680524                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20162729782                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  15601809495                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  15341092999                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  30942902494                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1519625500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1476118000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2995743500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        80500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       161000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  67935823302                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69691940133                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 137627763435                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  77696872560                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  80093620657                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 157790493217                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2993163000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2758056250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5751219250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2831783000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2786803750                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5618586750                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5824946000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5544860000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11369806000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032711                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032760                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032735                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014911                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014888                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014900                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.764432                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.768962                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766699                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.788676                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.784998                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786836                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058091                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059030                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058551                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.024257                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024246                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024251                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028290                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028308                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028299                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14200.098649                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14331.433565                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14265.745925                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27787.498525                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29033.499894                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28411.199742                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15116.512020                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15985.640642                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15552.741634                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 25254.268844                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 24929.422584                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25092.162876                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12922.974547                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12845.079492                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12884.474943                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        80500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        80500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        80500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18166.917358                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18632.385209                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168981.143793                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172453.964234                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.945885                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175756.144489                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158359.117513                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.184218                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172208.307465                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165069.810366                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168651.447728                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         13976964                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.880033                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          878227495                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13977476                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            62.831622                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      35142475250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   257.003288                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   254.876744                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.501960                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.497806                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999766                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          213                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        906182457                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       906182457                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    439239656                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    438987839                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      878227495                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    439239656                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    438987839                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       878227495                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    439239656                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    438987839                       # number of overall hits
system.cpu0.icache.overall_hits::total      878227495                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      7004074                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6973407                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13977481                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      7004074                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6973407                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13977481                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      7004074                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6973407                       # number of overall misses
system.cpu0.icache.overall_misses::total     13977481                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93843146430                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93562942727                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 187406089157                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  93843146430                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  93562942727                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 187406089157                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  93843146430                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  93562942727                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 187406089157                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    446243730                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    445961246                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    892204976                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    446243730                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    445961246                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    892204976                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    446243730                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    445961246                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    892204976                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015696                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015637                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015666                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015696                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015637                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015666                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015696                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015637                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015666                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13398.365927                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.106262                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.715536                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13398.365927                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.106262                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13407.715536                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13398.365927                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.106262                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13407.715536                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      7004074                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6973407                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13977481                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      7004074                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6973407                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13977481                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      7004074                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6973407                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13977481                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25928                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17197                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25928                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17197                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  83323187568                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  83088246273                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  83323187568                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  83088246273                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 166411433841                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  83323187568                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  83088246273                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 166411433841                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1928508500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1282516750                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3211025250                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1928508500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1282516750                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3211025250                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015666                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015666                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015696                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015637                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015666                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.681277                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74458.556522                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74379.377507                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74577.935105                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74458.556522                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   130358                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               130358                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20442                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94115                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       130351                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.276177                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    74.962722                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       130349    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::22528-24575            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       130351                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       114564                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23894.842621                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 20601.133760                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13695.118153                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        72946     63.67%     63.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        40612     35.45%     99.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          507      0.44%     99.56% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          353      0.31%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839           19      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           47      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375           10      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           28      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           26      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       114564                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples     26318568                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean    31.814872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -811003296  -3081.49%  -3081.49% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1      837321864   3181.49%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total     26318568                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        94116     82.16%     82.16% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        20442     17.84%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       114558                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       130358                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       130358                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       114558                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       114558                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       244916                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    83582440                       # DTB read hits
system.cpu1.dtb.read_misses                     99281                       # DTB read misses
system.cpu1.dtb.write_hits                   76249670                       # DTB write hits
system.cpu1.dtb.write_misses                    31077                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51825                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21270                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   73142                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4747                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9967                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                83681721                       # DTB read accesses
system.cpu1.dtb.write_accesses               76280747                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        159832110                       # DTB hits
system.cpu1.dtb.misses                         130358                       # DTB misses
system.cpu1.dtb.accesses                    159962468                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    77021                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                77021                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4430                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        67244                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        77021                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          77021    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        77021                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71674                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27071.277590                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 23813.549051                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 16581.978010                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        34935     48.74%     48.74% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535        35570     49.63%     98.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          418      0.58%     98.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          591      0.82%     99.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839            6      0.01%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           60      0.08%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           17      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           30      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           20      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            6      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71674                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -853687296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -853687296    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -853687296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        67244     93.82%     93.82% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4430      6.18%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        71674                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77021                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77021                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71674                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71674                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       148695                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   445961246                       # ITB inst hits
system.cpu1.itb.inst_misses                     77021                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51825                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21270                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    540                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   52758                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               446038267                       # ITB inst accesses
system.cpu1.itb.hits                        445961246                       # DTB hits
system.cpu1.itb.misses                          77021                       # DTB misses
system.cpu1.itb.accesses                    446038267                       # DTB accesses
system.cpu1.numCycles                     51824432674                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  445688230                       # Number of instructions committed
system.cpu1.committedOps                    523564727                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            480567684                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                428483                       # Number of float alu accesses
system.cpu1.num_func_calls                   26273151                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68126466                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   480567684                       # number of integer instructions
system.cpu1.num_fp_insts                       428483                       # number of float instructions
system.cpu1.num_int_register_reads          701499135                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         381123451                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              693452                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             356440                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           117557193                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          117240637                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    159825990                       # number of memory refs
system.cpu1.num_load_insts                   83579816                       # Number of load instructions
system.cpu1.num_store_insts                  76246174                       # Number of store instructions
system.cpu1.num_idle_cycles              50239290608.732407                       # Number of idle cycles
system.cpu1.num_busy_cycles              1585142065.267594                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030587                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969413                       # Percentage of idle cycles
system.cpu1.Branches                         99529261                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                362846766     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                 1082718      0.21%     69.47% # Class of executed instruction
system.cpu1.op_class::IntDiv                    48965      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             50459      0.01%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::MemRead                83579816     15.95%     85.45% # Class of executed instruction
system.cpu1.op_class::MemWrite               76246174     14.55%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 523854940                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq                40327                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40327                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp              29907                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231012                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231012                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353796                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334480                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334480                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492400                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           606981976                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           148423298                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              174500                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115487                       # number of replacements
system.iocache.tags.tagsinuse               10.456623                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115503                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13157342382000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510546                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946077                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219409                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434130                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653539                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039911                       # Number of tag accesses
system.iocache.tags.data_accesses             1039911                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8842                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8879                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8842                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8882                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8842                       # number of overall misses
system.iocache.overall_misses::total             8882                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5072000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1565914828                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1570986828                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       352500                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       352500                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  19799416850                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  19799416850                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5424500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1565914828                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1571339328                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5424500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1565914828                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1571339328                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8842                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8879                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8842                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8882                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8842                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8882                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 177099.618638                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 176932.855952                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117500                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117500                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185624.173573                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 185624.173573                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 177099.618638                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 176912.781806                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 177099.618638                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 176912.781806                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        107527                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                16113                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.673307                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8842                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8879                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8842                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8882                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8842                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8882                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3142000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1105053392                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1108195392                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       193500                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  14252856882                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  14252856882                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3335500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1105053392                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1108388892                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3335500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1105053392                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1108388892                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 124977.764307                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 124810.833652                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        64500                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        64500                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133623.873866                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133623.873866                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 124977.764307                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 124790.462959                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 124977.764307                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 124790.462959                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1294928                       # number of replacements
system.l2c.tags.tagsinuse                65284.624377                       # Cycle average of tags in use
system.l2c.tags.total_refs                   28063625                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1358068                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    20.664374                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               7589253000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38468.321907                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   163.057226                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   246.703748                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3367.231509                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9600.385059                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   149.839093                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   239.160217                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3055.361096                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9994.564521                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.586980                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002488                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003764                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.051380                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.146490                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002286                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003649                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.046621                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.152505                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996164                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          237                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62903                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          236                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2457                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5430                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54571                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003616                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.959824                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                267604060                       # Number of tag accesses
system.l2c.tags.data_accesses               267604060                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       246478                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       166336                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst            6965395                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data            3278179                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       243308                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       165231                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst            6932947                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data            3267656                       # number of ReadReq hits
system.l2c.ReadReq_hits::total               21265530                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         7866652                       # number of Writeback hits
system.l2c.Writeback_hits::total              7866652                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       360316                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       364967                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       725283                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data            4896                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4962                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9858                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           821407                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           805470                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1626877                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker        246478                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        166336                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6965395                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4099586                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        243308                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        165231                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6932947                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4073126                       # number of demand (read+write) hits
system.l2c.demand_hits::total                22892407                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       246478                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       166336                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6965395                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4099586                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       243308                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       165231                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6932947                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4073126                       # number of overall hits
system.l2c.overall_hits::total               22892407                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1986                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2021                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            38679                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           132917                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2168                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2035                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            40460                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           144107                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               364373                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       257472                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       250414                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       507886                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17895                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17622                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35517                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         247554                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         266155                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             513709                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1986                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2021                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             38679                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            380471                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2035                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             40460                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            410262                       # number of demand (read+write) misses
system.l2c.demand_misses::total                878082                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1986                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2021                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            38679                       # number of overall misses
system.l2c.overall_misses::cpu0.data           380471                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2168                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2035                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            40460                       # number of overall misses
system.l2c.overall_misses::cpu1.data           410262                       # number of overall misses
system.l2c.overall_misses::total               878082                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    170354500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    177467000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   3182312556                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data  11047112258                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    186335000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    177844750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   3318730008                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data  12078497021                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    30338653093                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data       123996                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total       123996                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    276678088                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    272829710                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    549507798                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       159000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  20013735944                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  21618082257                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  41631818201                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    170354500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    177467000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3182312556                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  31060848202                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    186335000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    177844750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3318730008                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  33696579278                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     71970471294                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    170354500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    177467000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3182312556                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  31060848202                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    186335000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    177844750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3318730008                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  33696579278                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    71970471294                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       248464                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       168357                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst        7004074                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        3411096                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       245476                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       167266                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst        6973407                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data        3411763                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total           21629903                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      7866652                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          7866652                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       617788                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       615381                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total      1233169                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        22791                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22584                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45375                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1068961                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1071625                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2140586                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       248464                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       168357                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         7004074                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4480057                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       245476                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       167266                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6973407                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4483388                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            23770489                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       248464                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       168357                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        7004074                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4480057                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       245476                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       167266                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6973407                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4483388                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           23770489                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007993                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012004                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.005522                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.038966                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.008832                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012166                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.005802                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.042238                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016846                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.416764                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.406925                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.411854                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.785178                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.780287                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782744                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.231584                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.248366                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.239985                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007993                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012004                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005522                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.084925                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.008832                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.012166                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005802                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.091507                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.036940                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007993                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012004                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005522                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.084925                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.008832                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.012166                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005802                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.091507                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.036940                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85777.693857                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87811.479466                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82274.943923                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 83112.861846                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85947.878229                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87392.997543                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82024.963124                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 83816.171463                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 83262.626740                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data     0.481590                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total     0.244141                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15461.195194                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15482.335149                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15471.683926                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80845.940457                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81223.656354                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 81041.636804                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85777.693857                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87811.479466                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82274.943923                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 81637.886204                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85947.878229                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87392.997543                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82024.963124                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82134.292910                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 81963.269141                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85777.693857                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87811.479466                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82274.943923                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 81637.886204                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85947.878229                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87392.997543                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82024.963124                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82134.292910                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 81963.269141                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1109675                       # number of writebacks
system.l2c.writebacks::total                  1109675                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1986                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2021                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        38679                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       132917                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2168                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2035                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        40460                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       144107                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          364373                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       257472                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       250414                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       507886                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17895                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17622                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35517                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       247554                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       266155                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        513709                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1986                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2021                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        38679                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       380471                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2168                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2035                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        40460                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       410262                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           878082                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1986                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2021                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        38679                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       380471                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2168                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2035                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        40460                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       410262                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          878082                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        25928                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17713                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        17197                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        15993                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16112                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        17598                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        25928                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        33825                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        17197                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        33591                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    145388500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    152020000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2697284444                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   9381927242                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    159094500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    152239750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2811418492                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data  10272794479                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  25772167407                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data   8111001504                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   7888588001                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  15999589505                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    313790893                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    308995621                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    622786514                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        67500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        67500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       135000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  16917537056                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18290027743                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  35207564799                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    145388500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    152020000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2697284444                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  26299464298                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    159094500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    152239750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2811418492                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  28562822222                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  60979732206                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    145388500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    152020000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2697284444                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  26299464298                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    159094500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    152239750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2811418492                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  28562822222                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  60979732206                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1552554500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2745071250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1033159250                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2534045000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7864830000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2622187500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2557908500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5180096000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1552554500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5367258750                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1033159250                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5091953500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13044926000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007993                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012004                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005522                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.038966                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.008832                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012166                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005802                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.042238                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016846                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.416764                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.406925                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.411854                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.785178                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.780287                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.782744                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.231584                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.248366                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.239985                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007993                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012004                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005522                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.084925                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.008832                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012166                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005802                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.091507                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.036940                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007993                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012004                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005522                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.084925                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.008832                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012166                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005802                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.091507                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.036940                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70584.855526                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71285.881179                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 70730.178710                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31502.460477                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31502.184387                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 31502.324350                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17535.115563                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17534.651061                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17534.885097                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        67500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        67500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        67500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68338.774797                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68719.459499                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 68536.009295                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69123.439889                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69620.930581                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69446.512064                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69735.113214                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69123.439889                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69446.512064                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154974.947778                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158447.133121                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102365.321290                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162747.486346                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145352.227526                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              450083                       # Transaction distribution
system.membus.trans_dist::ReadResp             450083                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::Writeback           1216305                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       614546                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       614546                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36081                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           36083                       # Transaction distribution
system.membus.trans_dist::ReadExReq            513152                       # Transaction distribution
system.membus.trans_dist::ReadExResp           513152                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4043368                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4173072                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       335046                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       335046                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4508118                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    159836512                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    160006362                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14048000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14048000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               174054362                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3335                       # Total snoops (count)
system.membus.snoop_fanout::samples           2864020                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2864020    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2864020                       # Request fanout histogram
system.membus.reqLayer0.occupancy           107121000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5172000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         10421674858                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5445003775                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          151621202                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq           22091229                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          22083154                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          7866652                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq      1339933                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp      1233169                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45378                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45380                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2140586                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2140586                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     28041212                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     28486273                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       793018                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1241724                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              58562227                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    894731284                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1156290950                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2684984                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3951520                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2057658738                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          492069                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         33517490                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.039407                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.194561                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               32196665     96.06%     96.06% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                1320825      3.94%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           33517490                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        25817690750                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1207500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       21033645158                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14294630789                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         457872249                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         748277250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------