path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.821000                       # Number of seconds simulated
sim_ticks                                51820999867500                       # Number of ticks simulated
final_tick                               51820999867500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 622691                       # Simulator instruction rate (inst/s)
host_op_rate                                   731741                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            36089691928                       # Simulator tick rate (ticks/s)
host_mem_usage                                 680680                       # Number of bytes of host memory used
host_seconds                                  1435.89                       # Real time elapsed on the host
sim_insts                                   894119248                       # Number of instructions simulated
sim_ops                                    1050702892                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       122816                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       126336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2599472                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         26029680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       150208                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       131904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2604676                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         25292888                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        407488                       # Number of bytes read from this memory
system.physmem.bytes_read::total             57465468                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2599472                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2604676                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5204148                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78618432                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78639012                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1919                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1974                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             64898                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            406717                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2347                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2061                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56824                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            395211                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6367                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                938318                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1228413                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1230986                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2370                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               50163                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              502300                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2899                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2545                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               50263                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              488082                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7863                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1108922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          50163                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          50263                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             100425                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1517115                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1517512                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1517115                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2370                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              50163                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             502300                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2899                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2545                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              50263                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             488479                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7863                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2626435                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        938318                       # Number of read requests accepted
system.physmem.writeReqs                      1230986                       # Number of write requests accepted
system.physmem.readBursts                      938318                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1230986                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 60016640                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     35712                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78638272                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  57465468                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78639012                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      558                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               57802                       # Per bank write bursts
system.physmem.perBankRdBursts::1               61444                       # Per bank write bursts
system.physmem.perBankRdBursts::2               58618                       # Per bank write bursts
system.physmem.perBankRdBursts::3               56911                       # Per bank write bursts
system.physmem.perBankRdBursts::4               53280                       # Per bank write bursts
system.physmem.perBankRdBursts::5               57178                       # Per bank write bursts
system.physmem.perBankRdBursts::6               52016                       # Per bank write bursts
system.physmem.perBankRdBursts::7               52831                       # Per bank write bursts
system.physmem.perBankRdBursts::8               55081                       # Per bank write bursts
system.physmem.perBankRdBursts::9              100686                       # Per bank write bursts
system.physmem.perBankRdBursts::10              57898                       # Per bank write bursts
system.physmem.perBankRdBursts::11              58894                       # Per bank write bursts
system.physmem.perBankRdBursts::12              52465                       # Per bank write bursts
system.physmem.perBankRdBursts::13              56002                       # Per bank write bursts
system.physmem.perBankRdBursts::14              52925                       # Per bank write bursts
system.physmem.perBankRdBursts::15              53729                       # Per bank write bursts
system.physmem.perBankWrBursts::0               76591                       # Per bank write bursts
system.physmem.perBankWrBursts::1               80097                       # Per bank write bursts
system.physmem.perBankWrBursts::2               79619                       # Per bank write bursts
system.physmem.perBankWrBursts::3               80251                       # Per bank write bursts
system.physmem.perBankWrBursts::4               74804                       # Per bank write bursts
system.physmem.perBankWrBursts::5               78970                       # Per bank write bursts
system.physmem.perBankWrBursts::6               72699                       # Per bank write bursts
system.physmem.perBankWrBursts::7               74032                       # Per bank write bursts
system.physmem.perBankWrBursts::8               75192                       # Per bank write bursts
system.physmem.perBankWrBursts::9               79224                       # Per bank write bursts
system.physmem.perBankWrBursts::10              76715                       # Per bank write bursts
system.physmem.perBankWrBursts::11              78463                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72476                       # Per bank write bursts
system.physmem.perBankWrBursts::13              78380                       # Per bank write bursts
system.physmem.perBankWrBursts::14              75126                       # Per bank write bursts
system.physmem.perBankWrBursts::15              76084                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          41                       # Number of times write queue was full causing retry
system.physmem.totGap                    51820996946500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  895202                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1228413                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    903707                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     28267                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       428                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       483                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       651                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       492                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1166                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      175                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      126                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      116                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       76                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       52                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1576                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1393                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    33745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    66568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    69544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    72891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    70544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    68952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    71209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    73943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    70814                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    74490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    70684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    68944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    68807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    66563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    65153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      531                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      417                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      415                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      397                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      269                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      190                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      136                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       563401                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      246.102850                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     148.051526                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     287.279361                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         250361     44.44%     44.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       146586     26.02%     70.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        50209      8.91%     79.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27045      4.80%     84.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18004      3.20%     87.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12090      2.15%     89.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8995      1.60%     91.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7664      1.36%     92.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        42447      7.53%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         563401                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         65697                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.273848                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      106.818256                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          65693     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           65697                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         65697                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.702878                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.053855                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.999985                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3               137      0.21%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                78      0.12%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               60      0.09%      0.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15              99      0.15%      0.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           51857     78.93%     79.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9705     14.77%     94.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            1082      1.65%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             596      0.91%     96.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             852      1.30%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             335      0.51%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              83      0.13%     98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              33      0.05%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              55      0.08%     98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              34      0.05%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              40      0.06%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              30      0.05%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             421      0.64%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              37      0.06%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              32      0.05%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              35      0.05%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              21      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               5      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               2      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             4      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            14      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             2      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             8      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           65697                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12237400086                       # Total ticks spent queuing
system.physmem.totMemAccLat               29820400086                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4688800000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13049.61                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31799.61                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         7.91                       # Average write queue length when enqueuing
system.physmem.readRowHits                     705929                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    897152                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.28                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.01                       # Row buffer hit rate for writes
system.physmem.avgGap                     23888305.63                       # Average gap between requests
system.physmem.pageHitRate                      73.99                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2146397400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1171149375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3510585000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3998568240                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384695652000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1301998363920                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29950494857250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34648015573185                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.609580                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49824747021214                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730417000000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    265835434786                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2112914160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1152879750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3803904000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3963556800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384695652000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1301510416275                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29950922881500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34648162204485                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.612409                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49825423536265                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730417000000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    265157286235                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   133030                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               133030                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        21129                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        95696                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           11                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       133019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         133019    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       133019                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       116836                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       115888     99.19%     99.19% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          821      0.70%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           61      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           31      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           22      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215            8      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       116836                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   9230012852                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.024648                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -227501296     -2.46%     -2.46% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     9457514148    102.46%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   9230012852                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        95697     81.91%     81.91% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        21129     18.09%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       116826                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       133030                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       133030                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       116826                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       116826                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       249856                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83528271                       # DTB read hits
system.cpu0.dtb.read_misses                    101098                       # DTB read misses
system.cpu0.dtb.write_hits                   76299925                       # DTB write hits
system.cpu0.dtb.write_misses                    31932                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21506                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    536                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   73224                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4644                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9926                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83629369                       # DTB read accesses
system.cpu0.dtb.write_accesses               76331857                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        159828196                       # DTB hits
system.cpu0.dtb.misses                         133030                       # DTB misses
system.cpu0.dtb.accesses                    159961226                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    78025                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                78025                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4409                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67964                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        78025                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          78025    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        78025                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72373                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        71328     98.56%     98.56% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          906      1.25%     99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           58      0.08%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           43      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           19      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72373                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -294749296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        67964     93.91%     93.91% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4409      6.09%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72373                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        78025                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        78025                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72373                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72373                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       150398                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   446488504                       # ITB inst hits
system.cpu0.itb.inst_misses                     78025                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21506                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    536                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   53747                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               446566529                       # ITB inst accesses
system.cpu0.itb.hits                        446488504                       # DTB hits
system.cpu0.itb.misses                          78025                       # DTB misses
system.cpu0.itb.accesses                    446566529                       # DTB accesses
system.cpu0.numPwrStateTransitions              16564                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         8282                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    6000025981.117725                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   124621883322.639465                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3529     42.61%     42.61% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         4688     56.60%     99.22% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.23% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            5      0.06%     99.29% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.54%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 5700356796932                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           8282                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   2128784691883                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     51821574278                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16348                       # number of quiesce instructions executed
system.cpu0.committedInsts                  446216062                       # Number of instructions committed
system.cpu0.committedOps                    524400051                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            481388306                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                440832                       # Number of float alu accesses
system.cpu0.num_func_calls                   26357525                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     68205669                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   481388306                       # number of integer instructions
system.cpu0.num_fp_insts                       440832                       # number of float instructions
system.cpu0.num_int_register_reads          703333504                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         381971540                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              708271                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             380080                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           117540708                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          117236412                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    159819450                       # number of memory refs
system.cpu0.num_load_insts                   83525533                       # Number of load instructions
system.cpu0.num_store_insts                  76293917                       # Number of store instructions
system.cpu0.num_idle_cycles              50236144373.803871                       # Number of idle cycles
system.cpu0.num_busy_cycles              1585429904.196130                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.030594                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.969406                       # Percentage of idle cycles
system.cpu0.Branches                         99643757                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                363667031     69.31%     69.31% # Class of executed instruction
system.cpu0.op_class::IntMult                 1107197      0.21%     69.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49205      0.01%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             55532      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                83525533     15.92%     85.46% # Class of executed instruction
system.cpu0.op_class::MemWrite               76293917     14.54%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 524698416                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements         10234473                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.965653                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          310064662                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10234985                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.294589                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3504381500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   238.684462                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   273.281191                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.466181                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.533752                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          406                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1291899613                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1291899613                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     78014225                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     78760782                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      156775007                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72354151                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     72480719                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     144834870                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       196883                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       197851                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       394734                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165349                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       170410                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       335759                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1859357                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1826349                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3685706                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2010395                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1982201                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3992596                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    150533725                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    151411911                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       301945636                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    150730608                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    151609762                       # number of overall hits
system.cpu0.dcache.overall_hits::total      302340370                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2625385                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2694018                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5319403                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1122925                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1101435                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2224360                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       663805                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       649032                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1312837                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       621975                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       610318                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1232293                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       151866                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       156716                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       308582                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            3                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4370285                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      4405771                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       8776056                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5034090                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      5054803                       # number of overall misses
system.cpu0.dcache.overall_misses::total     10088893                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41885369000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42555624000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  84440993000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34281339500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33248400000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  67529739500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12795660500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12469449500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25265110000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2230451000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2307866000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4538317000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       146000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        83000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       229000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  88962369000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  88273473500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 177235842500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  88962369000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  88273473500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 177235842500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80639610                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     81454800                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    162094410                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73477076                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73582154                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    147059230                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       860688                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       846883                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1707571                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       787324                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       780728                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1568052                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2011223                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1983065                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3994288                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2010398                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1982202                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3992600                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    154904010                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    155817682                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    310721692                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    155764698                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    156664565                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    312429263                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032557                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033074                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032817                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015283                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014969                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015126                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771249                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.766377                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.768833                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.789986                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.781729                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785875                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075509                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079027                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077256                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028213                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028275                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028244                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032319                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032265                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032292                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15953.991129                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15796.339891                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15874.148471                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30528.610103                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30186.438601                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30359.177246                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20572.628321                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20431.069541                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20502.518476                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14686.967458                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14726.422318                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14707.004945                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 48666.666667                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        83000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        57250                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20356.193932                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20035.874198                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20195.386458                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17671.986198                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17463.286601                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17567.422164                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      7894898                       # number of writebacks
system.cpu0.dcache.writebacks::total          7894898                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         9495                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        12245                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        21740                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9899                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11338                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21237                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35923                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35789                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71712                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        19394                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        23583                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        42977                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        19394                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        23583                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        42977                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2615890                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2681773                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5297663                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1113026                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1090097                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2203123                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       662931                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       648115                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1311046                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       621975                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       610318                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232293                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115943                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       120927                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       236870                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4350891                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      4382188                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      8733079                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5013822                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      5030303                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total     10044125                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16759                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16947                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15119                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18591                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31878                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35538                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39006077000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39571050000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78577127000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32849881500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31814880500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  64664762000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10562457500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10483200000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21045657500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12173685500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11859131500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24032817000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1545963000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1623615500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3169578500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       143000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       225000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  84029644000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83245062000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 167274706000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94592101500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93728262000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 188320363500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3122320000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3110634500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232954500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3122320000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3110634500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232954500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032439                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032923                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032683                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015148                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014815                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014981                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.770234                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.765295                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767784                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.789986                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781729                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785875                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057648                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.060980                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059302                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028088                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028124                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028106                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032188                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032109                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032148                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14911.206893                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14755.555373                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14832.413274                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29514.028873                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29185.366532                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29351.407979                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15932.966629                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16174.907231                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.569856                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19572.628321                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19431.069541                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19502.518476                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13333.819204                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13426.410148                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.088783                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 47666.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        82000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        56250                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19313.203663                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18996.232476                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19154.150100                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18866.266393                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18632.726895                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18749.305042                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186307.058894                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183550.746445                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.215807                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97945.918815                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87529.813158                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92455.121930                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements         13785272                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.891071                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          880886027                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13785784                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            63.898145                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      31614405500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   232.219683                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   279.671389                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.453554                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.546233                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        908457605                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       908457605                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    439628868                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    441257159                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      880886027                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    439628868                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    441257159                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       880886027                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    439628868                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    441257159                       # number of overall hits
system.cpu0.icache.overall_hits::total      880886027                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6859636                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6926153                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13785789                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6859636                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6926153                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13785789                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6859636                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6926153                       # number of overall misses
system.cpu0.icache.overall_misses::total     13785789                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92139159000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93034749000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 185173908000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  92139159000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  93034749000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 185173908000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  92139159000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  93034749000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 185173908000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    446488504                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    448183312                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    894671816                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    446488504                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    448183312                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    894671816                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    446488504                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    448183312                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    894671816                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015364                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015454                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015409                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015364                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015454                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015409                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015364                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015454                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015409                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.077008                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13432.384326                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.231409                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.077008                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13432.384326                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13432.231409                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.077008                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13432.384326                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13432.231409                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     13785272                       # number of writebacks
system.cpu0.icache.writebacks::total         13785272                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6859636                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6926153                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13785789                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6859636                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6926153                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13785789                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6859636                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6926153                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13785789                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85279523000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86108596000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 171388119000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85279523000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86108596000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 171388119000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85279523000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86108596000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 171388119000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3263480000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3263480000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015364                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015454                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015409                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015364                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015454                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015409                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015364                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015454                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015409                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.077008                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12432.384326                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12432.231409                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.077008                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12432.384326                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12432.231409                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.077008                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12432.384326                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551                       # average overall mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   133445                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               133445                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20908                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        96452                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           13                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       133432                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.299778                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    83.395537                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       133430    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       133432                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       117373                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        74140     63.17%     63.17% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        42199     35.95%     99.12% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          555      0.47%     99.59% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          343      0.29%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839            6      0.01%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           48      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375           11      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           29      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           23      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       117373                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   6007861436                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.129422                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -777548296    -12.94%    -12.94% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     6785409732    112.94%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   6007861436                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        96452     82.18%     82.18% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        20908     17.82%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       117360                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       133445                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       133445                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       117360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       117360                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       250805                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    84301684                       # DTB read hits
system.cpu1.dtb.read_misses                    101780                       # DTB read misses
system.cpu1.dtb.write_hits                   76371214                       # DTB write hits
system.cpu1.dtb.write_misses                    31665                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21521                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   73965                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4498                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10027                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                84403464                       # DTB read accesses
system.cpu1.dtb.write_accesses               76402879                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        160672898                       # DTB hits
system.cpu1.dtb.misses                         133445                       # DTB misses
system.cpu1.dtb.accesses                    160806343                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    78111                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                78111                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4330                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68231                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        78111                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          78111    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        78111                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        72561                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        35934     49.52%     49.52% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535        35483     48.90%     98.42% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          386      0.53%     98.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          612      0.84%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839           10      0.01%     99.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           47      0.06%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           20      0.03%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           31      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679           11      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            7      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        72561                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -850152296    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        68231     94.03%     94.03% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4330      5.97%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        72561                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        78111                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        78111                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72561                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72561                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       150672                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   448183312                       # ITB inst hits
system.cpu1.itb.inst_misses                     78111                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21521                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    531                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   53921                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               448261423                       # ITB inst accesses
system.cpu1.itb.hits                        448183312                       # DTB hits
system.cpu1.itb.misses                          78111                       # DTB misses
system.cpu1.itb.accesses                    448261423                       # DTB accesses
system.cpu1.numPwrStateTransitions              16084                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         8042                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    6194937221.007833                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   118254200557.171326                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3517     43.73%     43.73% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         4458     55.43%     99.17% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.06%     99.23% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           13      0.16%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value            1                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 3977581677820                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           8042                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   2001314736155                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     51820425457                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  447903186                       # Number of instructions committed
system.cpu1.committedOps                    526302841                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            483164392                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                453837                       # Number of float alu accesses
system.cpu1.num_func_calls                   26485275                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68482317                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   483164392                       # number of integer instructions
system.cpu1.num_fp_insts                       453837                       # number of float instructions
system.cpu1.num_int_register_reads          704985819                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         383399771                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              733419                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             379508                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           118000089                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          117710485                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    160666503                       # number of memory refs
system.cpu1.num_load_insts                   84298667                       # Number of load instructions
system.cpu1.num_store_insts                  76367836                       # Number of store instructions
system.cpu1.num_idle_cycles              50233099437.419525                       # Number of idle cycles
system.cpu1.num_busy_cycles              1587326019.580469                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030631                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969369                       # Percentage of idle cycles
system.cpu1.Branches                        100046269                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                364713411     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                 1116791      0.21%     69.47% # Class of executed instruction
system.cpu1.op_class::IntDiv                    48530      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             54891      0.01%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::MemRead                84298667     16.01%     85.50% # Class of executed instruction
system.cpu1.op_class::MemWrite               76367836     14.50%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 526600168                       # Class of executed instruction
system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40318                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40318                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230994                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230994                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353778                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334408                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334408                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42147500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               323000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25749000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38609000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           568885533                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147754000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115478                       # number of replacements
system.iocache.tags.tagsinuse               10.457315                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115494                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13153888090000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.511180                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946135                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219449                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434133                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653582                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039830                       # Number of tag accesses
system.iocache.tags.data_accesses             1039830                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8833                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8870                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115497                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115537                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115497                       # number of overall misses
system.iocache.overall_misses::total           115537                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1609929768                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1615016268                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12771447265                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12771447265                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14381377033                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14386814533                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14381377033                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14386814533                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8833                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8870                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115497                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115537                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115497                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115537                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182263.078003                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182076.242165                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119735.311492                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 119735.311492                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124517.321082                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124521.274856                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124517.321082                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124521.274856                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         31700                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3352                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.457041                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8833                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8870                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115497                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115537                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115497                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115537                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1168279768                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1171516268                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7431457785                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7431457785                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8599737553                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8603175053                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8599737553                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8603175053                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132263.078003                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132076.242165                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69671.658526                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69671.658526                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74458.536178                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74462.510304                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74458.536178                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74462.510304                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1307385                       # number of replacements
system.l2c.tags.tagsinuse                65260.397522                       # Cycle average of tags in use
system.l2c.tags.total_refs                   44030779                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1370457                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    32.128537                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               6646395500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38500.682373                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   145.371302                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   226.787619                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3397.197981                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9485.761310                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   150.823098                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   211.566669                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2947.507944                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10194.699226                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.587474                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002218                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003461                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.051837                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.144741                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002301                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003228                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.044975                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.155559                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995795                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          284                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62788                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          283                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          410                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2444                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5467                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54432                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004333                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.958069                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                395683924                       # Number of tag accesses
system.l2c.tags.data_accesses               395683924                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker       246270                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       166121                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       249681                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       166863                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 828935                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7894898                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7894898                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     13783694                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        13783694                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            4999                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            5005                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10004                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           822661                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           809558                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1632219                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       6820625                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       6886530                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          13707155                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3255016                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3312365                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6567381                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       362783                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       360629                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           723412                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        246270                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        166121                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6820625                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4077677                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        249681                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        166863                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6886530                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4121923                       # number of demand (read+write) hits
system.l2c.demand_hits::total                22735690                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       246270                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       166121                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6820625                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4077677                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       249681                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       166863                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6886530                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4121923                       # number of overall hits
system.l2c.overall_hits::total               22735690                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1919                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1974                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2347                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2061                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8301                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17868                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         18114                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35982                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            3                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         267498                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         257420                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             524918                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        39011                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        39623                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           78634                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       139748                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       138450                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         278198                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       259192                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       249689                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         508881                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1919                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1974                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             39011                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            407246                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2347                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2061                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39623                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            395870                       # number of demand (read+write) misses
system.l2c.demand_misses::total                890051                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1919                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1974                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            39011                       # number of overall misses
system.l2c.overall_misses::cpu0.data           407246                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2347                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2061                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39623                       # number of overall misses
system.l2c.overall_misses::cpu1.data           395870                       # number of overall misses
system.l2c.overall_misses::total               890051                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    165360000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    173972500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    200913500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    181119000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      721365000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    254812500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    264932000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    519744500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       138500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       219000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  21948342500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  21077906500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  43026249000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3236344000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3273107500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   6509451500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  11805803000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11682188000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  23487991000                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data        57000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data       397500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total       454500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    165360000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    173972500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3236344000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  33754145500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    200913500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    181119000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3273107500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  32760094500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     73745056500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    165360000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    173972500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3236344000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  33754145500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    200913500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    181119000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3273107500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  32760094500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    73745056500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       248189                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       168095                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       252028                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       168924                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             837236                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7894898                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7894898                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     13783694                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     13783694                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        22867                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        23119                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45986                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1090159                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1066978                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2157137                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6859636                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      6926153                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      13785789                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3394764                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3450815                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6845579                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       621975                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       610318                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1232293                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       248189                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       168095                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6859636                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4484923                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       252028                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       168924                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6926153                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4517793                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            23625741                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       248189                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       168095                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6859636                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4484923                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       252028                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       168924                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6926153                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4517793                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           23625741                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007732                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011743                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009312                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012201                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.009915                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781388                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.783511                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.782456                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.245375                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.241261                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.243340                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005687                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005721                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005704                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041166                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.040121                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.040639                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.416724                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.409113                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.412955                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007732                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011743                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005687                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.090803                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.009312                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.012201                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005721                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.087625                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.037673                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007732                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011743                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005687                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.090803                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.009312                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.012201                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005721                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.087625                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.037673                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86169.880146                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88131.965552                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85604.388581                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87879.184862                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 86900.975786                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14260.829416                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14625.814287                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14444.569507                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 46166.666667                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        54750                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82050.491966                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81881.386450                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 81967.562553                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82959.780575                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82606.251420                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82781.640257                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84479.226894                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84378.389310                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 84429.043343                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     0.219914                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.591980                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total     0.893136                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86169.880146                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88131.965552                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82959.780575                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 82883.921512                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85604.388581                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87879.184862                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82606.251420                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82754.678303                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 82854.866182                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86169.880146                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88131.965552                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82959.780575                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 82883.921512                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85604.388581                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87879.184862                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82606.251420                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82754.678303                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 82854.866182                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1121783                       # number of writebacks
system.l2c.writebacks::total                  1121783                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1919                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1974                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2347                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2061                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8301                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17868                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        18114                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35982                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            3                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       267498                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       257420                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        524918                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        39011                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        39623                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        78634                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       139748                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       138450                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       278198                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       259192                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       249689                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       508881                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1919                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1974                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        39011                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       407246                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2347                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2061                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        39623                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       395870                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           890051                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1919                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1974                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        39011                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       407246                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2347                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2061                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        39623                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       395870                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          890051                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16759                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16947                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15119                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18591                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31878                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35538                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    146170000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    154232500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    177443500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    160509000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    638355000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    338146000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    342776500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    680922500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       108500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       179000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  19273362500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18503706500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  37777069000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   2846234000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2876877500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   5723111500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10408301543                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10297672531                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  20705974074                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   4839576500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   4660160000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total   9499736500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    146170000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    154232500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2846234000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  29681664043                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    177443500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    160509000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2876877500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  28801379031                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  64844509574                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    146170000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    154232500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2846234000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  29681664043                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    177443500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    160509000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2876877500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  28801379031                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  64844509574                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2912456500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2898400000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8535274000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2912456500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2898400000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8535274000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007732                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011743                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.009312                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012201                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.009915                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781388                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.783511                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.782456                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.245375                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.241261                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.243340                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005687                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005721                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005704                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041166                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040121                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040639                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.416724                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.409113                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.412955                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007732                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011743                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005687                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.090803                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009312                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012201                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005721                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.087625                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.037673                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007732                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011743                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005687                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.090803                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009312                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012201                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005721                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.087625                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.037673                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 76900.975786                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18924.669801                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18923.291377                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18923.975877                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 36166.666667                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        44750                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 72854.824694                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 72854.824694                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       2972233                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1487104                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3352                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
system.membus.trans_dist::ReadResp             450834                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1228413                       # Transaction distribution
system.membus.trans_dist::CleanEvict           193324                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36554                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              4                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            524356                       # Transaction distribution
system.membus.trans_dist::ReadExResp           524356                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        374003                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        615538                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3721390                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3851094                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237382                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237382                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4088476                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    128872672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    129042522                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7231808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7231808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               136274330                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3165                       # Total snoops (count)
system.membus.snoop_fanout::samples           1660996                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019349                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.137749                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1628857     98.07%     98.07% # Request fanout histogram
system.membus.snoop_fanout::1                   32139      1.93%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1660996                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106934500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5678000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8069625955                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4926078787                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44722660                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     48668708                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     24647917                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1743                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2076                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2076                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq            1292402                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          21924695                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9016681                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     13785272                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2525177                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45989                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45993                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2157137                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2157137                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      13785789                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6848293                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1261037                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1232293                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41443100                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30932231                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       796412                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1256395                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              74428138                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1764720404                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1081696966                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2696152                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      4001736                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2853115258                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1718109                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         26731746                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021922                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.146427                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               26145745     97.81%     97.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 586001      2.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           26731746                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        46403347500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1695386                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       20721808500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14193795462                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         459393000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         756178000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------