path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.832615                       # Number of seconds simulated
sim_ticks                                51832614542500                       # Number of ticks simulated
final_tick                               51832614542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 677235                       # Simulator instruction rate (inst/s)
host_op_rate                                   795801                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            39828045805                       # Simulator tick rate (ticks/s)
host_mem_usage                                 719272                       # Number of bytes of host memory used
host_seconds                                  1301.41                       # Real time elapsed on the host
sim_insts                                   881360160                       # Number of instructions simulated
sim_ops                                    1035663034                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       134080                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       130496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2944516                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         40297840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       118912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       116992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2475952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         40549336                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        378752                       # Number of bytes read from this memory
system.physmem.bytes_read::total             87146876                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2944516                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2475952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5420468                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75611328                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75631908                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2095                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2039                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             70534                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            629657                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1858                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1828                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             54568                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            633593                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           5918                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1402090                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1181427                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1184000                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2587                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2518                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               56808                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              777461                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2294                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2257                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               47768                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              782313                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7307                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1681314                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          56808                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          47768                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             104576                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1458760                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1459157                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1458760                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2587                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2518                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              56808                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             777461                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2294                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2257                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              47768                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             782710                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7307                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3140470                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1402090                       # Number of read requests accepted
system.physmem.writeReqs                      1184000                       # Number of write requests accepted
system.physmem.readBursts                     1402090                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1184000                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 89692096                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     41664                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  75632192                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  87146876                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               75631908                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      651                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         142152                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               86151                       # Per bank write bursts
system.physmem.perBankRdBursts::1               87375                       # Per bank write bursts
system.physmem.perBankRdBursts::2               80357                       # Per bank write bursts
system.physmem.perBankRdBursts::3               81721                       # Per bank write bursts
system.physmem.perBankRdBursts::4               87059                       # Per bank write bursts
system.physmem.perBankRdBursts::5               94652                       # Per bank write bursts
system.physmem.perBankRdBursts::6               87531                       # Per bank write bursts
system.physmem.perBankRdBursts::7               83073                       # Per bank write bursts
system.physmem.perBankRdBursts::8               80243                       # Per bank write bursts
system.physmem.perBankRdBursts::9              128909                       # Per bank write bursts
system.physmem.perBankRdBursts::10              86457                       # Per bank write bursts
system.physmem.perBankRdBursts::11              85414                       # Per bank write bursts
system.physmem.perBankRdBursts::12              83586                       # Per bank write bursts
system.physmem.perBankRdBursts::13              88109                       # Per bank write bursts
system.physmem.perBankRdBursts::14              80365                       # Per bank write bursts
system.physmem.perBankRdBursts::15              80437                       # Per bank write bursts
system.physmem.perBankWrBursts::0               72704                       # Per bank write bursts
system.physmem.perBankWrBursts::1               74469                       # Per bank write bursts
system.physmem.perBankWrBursts::2               70529                       # Per bank write bursts
system.physmem.perBankWrBursts::3               72860                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75808                       # Per bank write bursts
system.physmem.perBankWrBursts::5               80444                       # Per bank write bursts
system.physmem.perBankWrBursts::6               76110                       # Per bank write bursts
system.physmem.perBankWrBursts::7               73633                       # Per bank write bursts
system.physmem.perBankWrBursts::8               70562                       # Per bank write bursts
system.physmem.perBankWrBursts::9               76081                       # Per bank write bursts
system.physmem.perBankWrBursts::10              73660                       # Per bank write bursts
system.physmem.perBankWrBursts::11              73767                       # Per bank write bursts
system.physmem.perBankWrBursts::12              72713                       # Per bank write bursts
system.physmem.perBankWrBursts::13              77059                       # Per bank write bursts
system.physmem.perBankWrBursts::14              70231                       # Per bank write bursts
system.physmem.perBankWrBursts::15              71123                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          31                       # Number of times write queue was full causing retry
system.physmem.totGap                    51832611910500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1358974                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1181427                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1369118                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     26985                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       442                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       427                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       477                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       766                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       841                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      338                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      101                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       94                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       89                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       69                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       49                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1574                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1554                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1528                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1412                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    16205                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    18522                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    67973                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    68856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    68869                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    68651                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    68381                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    71263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    71520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    74085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    72568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    72467                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    69770                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    69647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    70062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    67493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    67216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    66673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      438                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      423                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      231                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      303                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      225                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      102                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       564759                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      292.733658                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     169.256086                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     326.085017                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         228658     40.49%     40.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       138332     24.49%     64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        49531      8.77%     73.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        28277      5.01%     78.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        20268      3.59%     82.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        14095      2.50%     84.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        11027      1.95%     86.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        10949      1.94%     88.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        63622     11.27%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         564759                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         67625                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.723608                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      277.022721                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095          67622    100.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::69632-73727            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           67625                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         67625                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.475091                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.957142                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.452813                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                76      0.11%      0.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                68      0.10%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               65      0.10%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15             131      0.19%      0.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           63823     94.38%     94.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             440      0.65%     95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             742      1.10%     96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             499      0.74%     97.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             390      0.58%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             489      0.72%     98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             119      0.18%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              25      0.04%     98.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              63      0.09%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              45      0.07%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              39      0.06%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              22      0.03%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             448      0.66%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              23      0.03%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              39      0.06%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              24      0.04%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               5      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            23      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             5      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           67625                       # Writes before turning the bus around for reads
system.physmem.totQLat                    16718468525                       # Total ticks spent queuing
system.physmem.totMemAccLat               42995449775                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   7007195000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11929.50                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30679.50                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.73                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.46                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.68                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.46                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        12.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1132210                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    886222                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.99                       # Row buffer hit rate for writes
system.physmem.avgGap                     20042849.21                       # Average gap between requests
system.physmem.pageHitRate                      78.14                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2158387560                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1177691625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                5365768200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3865689360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3385453914960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1313258572845                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29947583060250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34658863084800                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.669107                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49819671489024                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730804660000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    282130972226                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2111190480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1151939250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                5565417000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3792070080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3385453914960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1310153724135                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29950306611750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34658534867655                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.662774                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49824215805224                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730804660000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    277593670776                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   130428                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               130428                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20426                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94161                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       130414                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         130414    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       130414                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       114601                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 25025.623686                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.133741                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14193.681922                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       113576     99.11%     99.11% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          877      0.77%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           64      0.06%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           43      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           23      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           10      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       114601                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   -626546628                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.597966                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.490309                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -251893296     40.20%     40.20% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     -374653332     59.80%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   -626546628                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        94162     82.17%     82.17% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        20426     17.83%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       114588                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       130428                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       130428                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       114588                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       114588                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       245016                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    82615908                       # DTB read hits
system.cpu0.dtb.read_misses                     99897                       # DTB read misses
system.cpu0.dtb.write_hits                   75294881                       # DTB write hits
system.cpu0.dtb.write_misses                    30531                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51838                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21162                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    519                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   72657                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4653                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9875                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                82715805                       # DTB read accesses
system.cpu0.dtb.write_accesses               75325412                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        157910789                       # DTB hits
system.cpu0.dtb.misses                         130428                       # DTB misses
system.cpu0.dtb.accesses                    158041217                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    77694                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                77694                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4299                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67844                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        77694                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          77694    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        77694                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72143                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28108.645329                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 25072.463875                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 16528.773937                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        70985     98.39%     98.39% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          998      1.38%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           60      0.08%     99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           53      0.07%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           28      0.04%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           14      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72143                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -294780296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -294780296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -294780296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        67844     94.04%     94.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4299      5.96%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72143                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77694                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77694                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72143                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72143                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       149837                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   440762049                       # ITB inst hits
system.cpu0.itb.inst_misses                     77694                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51838                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21162                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    519                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   53801                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               440839743                       # ITB inst accesses
system.cpu0.itb.hits                        440762049                       # DTB hits
system.cpu0.itb.misses                          77694                       # DTB misses
system.cpu0.itb.accesses                    440839743                       # DTB accesses
system.cpu0.numCycles                     51832801454                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  440492275                       # Number of instructions committed
system.cpu0.committedOps                    517776891                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            475595742                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                442272                       # Number of float alu accesses
system.cpu0.num_func_calls                   26261796                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     67159010                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   475595742                       # number of integer instructions
system.cpu0.num_fp_insts                       442272                       # number of float instructions
system.cpu0.num_int_register_reads          692983656                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         377245689                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              706646                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             389336                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           115273932                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          114990138                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    157900832                       # number of memory refs
system.cpu0.num_load_insts                   82612008                       # Number of load instructions
system.cpu0.num_store_insts                  75288824                       # Number of store instructions
system.cpu0.num_idle_cycles              50243492062.967224                       # Number of idle cycles
system.cpu0.num_busy_cycles              1589309391.032773                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.030662                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.969338                       # Percentage of idle cycles
system.cpu0.Branches                         98397494                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                358993131     69.29%     69.29% # Class of executed instruction
system.cpu0.op_class::IntMult                 1071583      0.21%     69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv                    48336      0.01%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             58966      0.01%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.52% # Class of executed instruction
system.cpu0.op_class::MemRead                82612008     15.95%     85.47% # Class of executed instruction
system.cpu0.op_class::MemWrite               75288824     14.53%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 518072849                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16267                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements         10037940                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.966034                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          305864730                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10038452                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.469312                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3466781500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   221.416582                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   290.549452                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.432454                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.567479                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999934                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          394                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           66                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1274123450                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1274123450                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     77217599                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     77513026                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      154730625                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     71443407                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     71419351                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     142862758                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195522                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       192929                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       388451                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       168757                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       166793                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       335550                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1811257                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1789885                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3601142                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1962197                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1939338                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3901535                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    148661006                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    148932377                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       297593383                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    148856528                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    149125306                       # number of overall hits
system.cpu0.dcache.overall_hits::total      297981834                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2588533                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2647536                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5236069                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1081685                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1087089                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2168774                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       633947                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       631509                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1265456                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       612829                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       615985                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1228814                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       151773                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       150295                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       302068                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3670218                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      3734625                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       7404843                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4304165                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      4366134                       # number of overall misses
system.cpu0.dcache.overall_misses::total      8670299                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41004192000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41620421500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  82624613500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  31575309500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  31406770000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  62982079500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  25211350000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  25725023500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  50936373500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2229514000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2184997000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4414511000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        33000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       115000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  72579501500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  73027191500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 145606693000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  72579501500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  73027191500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 145606693000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     79806132                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     80160562                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    159966694                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     72525092                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     72506440                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    145031532                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       829469                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       824438                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1653907                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       781586                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       782778                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1564364                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1963030                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1940180                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3903210                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1962198                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1939339                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3901537                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    152331224                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    152667002                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    304998226                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    153160693                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    153491440                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    306652133                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032435                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033028                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032732                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014915                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014993                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.014954                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.764281                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.765987                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.765131                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.784084                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.786922                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785504                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.077316                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077464                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077390                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.024094                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024463                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.024278                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028102                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028445                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.028274                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15840.706686                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15720.436474                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15779.893943                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29190.854546                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28890.707201                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29040.406930                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 41139.290079                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41762.418728                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 41451.654604                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14689.793310                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14538.055158                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14614.295457                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        33000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        57500                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19775.256265                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19554.089500                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19663.711033                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16862.620624                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16725.824608                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16793.733757                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7725236                       # number of writebacks
system.cpu0.dcache.writebacks::total          7725236                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11311                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        11844                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        23155                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9967                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11283                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21250                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        36142                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35738                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71880                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        21278                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        23127                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        44405                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        21278                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        23127                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        44405                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2577222                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2635692                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5212914                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1071718                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1075806                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2147524                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       633158                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       630543                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1263701                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       612829                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       615985                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1228814                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115631                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       114557                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       230188                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3648940                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3711498                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7360438                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4282098                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4342041                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      8624139                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17286                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        16418                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33704                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16057                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        17652                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33709                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33343                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34070                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67413                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38167566000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38688442500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76856008500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  30213193500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  29970900500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  60184094000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10061362000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10320868500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20382230500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  24598521000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  25109038500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  49707559500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1553845500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1517429500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3071275000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        32000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       113000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  68380759500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  68659343000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 137040102500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  78442121500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  78980211500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 157422333000                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2977259000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2853920500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5831179500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2866948000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   2828284500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5695232500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5844207000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   5682205000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11526412000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032294                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032880                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032587                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014777                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014837                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014807                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.763329                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.764816                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.764070                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.784084                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.786922                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785504                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.058904                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059045                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.058974                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023954                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024311                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.024133                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027958                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028288                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.028124                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14809.576358                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14678.665982                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14743.387000                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28191.365173                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27859.019656                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28024.876090                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15890.760284                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16368.223103                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16128.997682                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 40139.290079                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40762.418728                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 40451.654604                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13437.966462                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13246.065278                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13342.463552                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        32000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        56500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18739.896929                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18499.092011                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18618.471143                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18318.618934                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18189.651249                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18253.686890                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172235.277103                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173828.755025                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173011.497152                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178548.172137                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160224.592114                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168952.876087                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 175275.380140                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166780.305254                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170982.036106                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         13866895                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.854828                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          868036851                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13867407                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            62.595469                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      43293883500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   253.434107                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   258.420721                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.494988                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.504728                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999716                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          185                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        895771675                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       895771675                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    433832015                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    434204836                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      868036851                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    433832015                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    434204836                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       868036851                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    433832015                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    434204836                       # number of overall hits
system.cpu0.icache.overall_hits::total      868036851                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6930034                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6937378                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13867412                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6930034                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6937378                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13867412                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6930034                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6937378                       # number of overall misses
system.cpu0.icache.overall_misses::total     13867412                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  93266994500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  92872882000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 186139876500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  93266994500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  92872882000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 186139876500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  93266994500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  92872882000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 186139876500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    440762049                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    441142214                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    881904263                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    440762049                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    441142214                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    881904263                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    440762049                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    441142214                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    881904263                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015723                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015726                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015724                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015723                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015726                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015724                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015723                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015726                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015724                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13458.374735                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.317514                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13422.827309                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13458.374735                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13387.317514                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13422.827309                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13458.374735                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13387.317514                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13422.827309                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6930034                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6937378                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13867412                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6930034                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6937378                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13867412                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6930034                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6937378                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13867412                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        26185                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        16940                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        26185                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        16940                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  86336960500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  85935504000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 172272464500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  86336960500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  85935504000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 172272464500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  86336960500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  85935504000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 172272464500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959231000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1269892000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3229123000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959231000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1269892000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3229123000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015724                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015724                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015723                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015726                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015724                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12422.827309                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12422.827309                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12458.374735                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12387.317514                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12422.827309                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 74878.214493                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 74822.646553                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 74964.108619                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 74878.214493                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   127806                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               127806                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20371                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        91874                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           17                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       127789                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.297365                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    80.104866                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       127787    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-26623            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       127789                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       112262                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24820.406727                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21828.616459                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13574.434559                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        72880     64.92%     64.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        38528     34.32%     99.24% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          428      0.38%     99.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          314      0.28%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839            5      0.00%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           36      0.03%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375            8      0.01%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           20      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           22      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       112262                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   8237382924                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.971809                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.165518                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0      232218204      2.82%      2.82% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     8005164720     97.18%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   8237382924                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        91874     81.85%     81.85% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        20371     18.15%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       112245                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       127806                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       127806                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       112245                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       112245                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       240051                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    82941587                       # DTB read hits
system.cpu1.dtb.read_misses                     97218                       # DTB read misses
system.cpu1.dtb.write_hits                   75253518                       # DTB write hits
system.cpu1.dtb.write_misses                    30588                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51836                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              20662                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   71746                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4678                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9800                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                83038805                       # DTB read accesses
system.cpu1.dtb.write_accesses               75284106                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        158195105                       # DTB hits
system.cpu1.dtb.misses                         127806                       # DTB misses
system.cpu1.dtb.accesses                    158322911                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    77092                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                77092                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4382                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        67241                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        77092                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          77092    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        77092                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71623                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28009.703587                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25156.150396                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 15232.175605                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        36121     50.43%     50.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535        34500     48.17%     98.60% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          359      0.50%     99.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          519      0.72%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           46      0.06%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           17      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           23      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71623                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -887431296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -887431296    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -887431296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        67241     93.88%     93.88% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4382      6.12%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        71623                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        77092                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        77092                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71623                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71623                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       148715                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   441142214                       # ITB inst hits
system.cpu1.itb.inst_misses                     77092                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51836                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              20662                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   52225                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               441219306                       # ITB inst accesses
system.cpu1.itb.hits                        441142214                       # DTB hits
system.cpu1.itb.misses                          77092                       # DTB misses
system.cpu1.itb.accesses                    441219306                       # DTB accesses
system.cpu1.numCycles                     51832427631                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  440867885                       # Number of instructions committed
system.cpu1.committedOps                    517886143                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            475513559                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                454227                       # Number of float alu accesses
system.cpu1.num_func_calls                   26111235                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     67284853                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   475513559                       # number of integer instructions
system.cpu1.num_fp_insts                       454227                       # number of float instructions
system.cpu1.num_int_register_reads          692532840                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         377153809                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              737892                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             372156                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           115804323                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          115491463                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    158189082                       # number of memory refs
system.cpu1.num_load_insts                   82939410                       # Number of load instructions
system.cpu1.num_store_insts                  75249672                       # Number of store instructions
system.cpu1.num_idle_cycles              50245805753.829796                       # Number of idle cycles
system.cpu1.num_busy_cycles              1586621877.170202                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030611                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969389                       # Percentage of idle cycles
system.cpu1.Branches                         98435537                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                358757749     69.23%     69.23% # Class of executed instruction
system.cpu1.op_class::IntMult                 1128666      0.22%     69.45% # Class of executed instruction
system.cpu1.op_class::IntDiv                    49961      0.01%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             51912      0.01%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::MemRead                82939410     16.01%     85.48% # Class of executed instruction
system.cpu1.op_class::MemWrite               75249672     14.52%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 518177412                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq                40326                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40326                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231010                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231010                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353794                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334472                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334472                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492392                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36301000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           568807378                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147770000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115487                       # number of replacements
system.iocache.tags.tagsinuse               10.455201                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115503                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13165365743000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510018                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.945183                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219376                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434074                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653450                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039902                       # Number of tag accesses
system.iocache.tags.data_accesses             1039902                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8841                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8878                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8841                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8881                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8841                       # number of overall misses
system.iocache.overall_misses::total             8881                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1579254237                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1584323237                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12612931141                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12612931141                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1579254237                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1584674237                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1579254237                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1584674237                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8841                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8878                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8841                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8881                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8841                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8881                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet       137000                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 178628.462504                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 178454.971503                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118249.185677                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118249.185677                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 178628.462504                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 178434.212026                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135500                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 178628.462504                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 178434.212026                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         30353                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3277                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.262435                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8841                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8878                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8841                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8881                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8841                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8881                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1137204237                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1140423237                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7279731141                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7279731141                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1137204237                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1140624237                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1137204237                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1140624237                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet        87000                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 128628.462504                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 128454.971503                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68249.185677                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68249.185677                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 128628.462504                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 128434.212026                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85500                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 128628.462504                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 128434.212026                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1260623                       # number of replacements
system.l2c.tags.tagsinuse                65280.532461                       # Cycle average of tags in use
system.l2c.tags.total_refs                   43887253                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1323818                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    33.152029                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              38344006500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38235.631490                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.327159                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   255.763508                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4002.247331                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    10061.721412                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   140.225182                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   222.893104                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2612.785728                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9555.937547                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.583429                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002950                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003903                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.061069                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.153530                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002140                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003401                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.039868                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.145812                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996102                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          327                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62868                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          327                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          408                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2451                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5488                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54479                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004990                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.959290                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                393981982                       # Number of tag accesses
system.l2c.tags.data_accesses               393981982                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       238329                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       162891                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       232955                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       163054                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 797229                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         7725236                       # number of Writeback hits
system.l2c.Writeback_hits::total              7725236                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data            4940                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4801                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9741                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           806406                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           815086                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1621492                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       6885661                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       6899737                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          13785398                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3189949                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3243555                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6433504                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       361245                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       357794                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           719039                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        238329                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        162891                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6885661                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3996355                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        232955                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        163054                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6899737                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4058641                       # number of demand (read+write) hits
system.l2c.demand_hits::total                22637623                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       238329                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       162891                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6885661                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3996355                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       232955                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       163054                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6899737                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4058641                       # number of overall hits
system.l2c.overall_hits::total               22637623                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         2095                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2039                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         1858                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         1828                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 7820                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17709                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17217                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             34926                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         242663                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         238702                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             481365                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        44373                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        37641                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           82014                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       136062                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       137237                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         273299                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       251584                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       258191                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         509775                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2095                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2039                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             44373                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            378725                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1858                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1828                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             37641                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            375939                       # number of demand (read+write) misses
system.l2c.demand_misses::total                844498                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2095                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2039                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            44373                       # number of overall misses
system.l2c.overall_misses::cpu0.data           378725                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1858                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1828                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            37641                       # number of overall misses
system.l2c.overall_misses::cpu1.data           375939                       # number of overall misses
system.l2c.overall_misses::total               844498                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    179866500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    180146000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    162156000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    158214500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      680383000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    276798500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    263076500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    539875000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        30500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       110000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  19543422000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  19220420500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  38763842500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3621036000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3060803500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   6681839500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  11298249500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11397176000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  22695425500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  19886204500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  20428221500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  40314426000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    179866500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    180146000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3621036000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  30841671500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    162156000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    158214500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3060803500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  30617596500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     68821490500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    179866500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    180146000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3621036000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  30841671500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    162156000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    158214500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3060803500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  30617596500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    68821490500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       240424                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       164930                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       234813                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       164882                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             805049                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      7725236                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          7725236                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        22649                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22018                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           44667                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1049069                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1053788                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2102857                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6930034                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      6937378                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      13867412                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3326011                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3380792                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6706803                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       612829                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       615985                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1228814                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       240424                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       164930                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6930034                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4375080                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       234813                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       164882                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6937378                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4434580                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            23482121                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       240424                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       164930                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6930034                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4375080                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       234813                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       164882                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6937378                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4434580                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           23482121                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008714                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012363                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.007913                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011087                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.009714                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781889                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781951                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.781920                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.231313                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.226518                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.228910                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006403                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005426                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005914                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.040908                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.040593                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.040750                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.410529                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.419151                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.414851                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.012363                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.006403                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.086564                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.007913                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.011087                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005426                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.084774                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.035963                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.012363                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.006403                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.086564                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.007913                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.011087                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005426                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.084774                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.035963                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85855.131265                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88350.171653                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87274.488698                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86550.601751                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 87005.498721                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15630.385680                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15280.042981                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15457.681956                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        30500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        55000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80537.296580                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80520.567486                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 80529.000862                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81604.489216                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81315.679711                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81471.937718                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 83037.508636                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83047.399754                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 83042.475457                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 79043.995246                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79120.579339                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 79082.783581                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85855.131265                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88350.171653                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 81604.489216                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 81435.531058                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87274.488698                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86550.601751                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81315.679711                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81442.990751                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 81493.965054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85855.131265                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88350.171653                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 81604.489216                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 81435.531058                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87274.488698                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86550.601751                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81315.679711                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81442.990751                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 81493.965054                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks             1074796                       # number of writebacks
system.l2c.writebacks::total                  1074796                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2095                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2039                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         1858                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1828                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            7820                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks         1119                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1119                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17709                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17217                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        34926                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       242663                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       238702                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        481365                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        44373                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        37641                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        82014                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       136062                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       137237                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       273299                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       251584                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       258191                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       509775                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         2095                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2039                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        44373                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       378725                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1858                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1828                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        37641                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       375939                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           844498                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         2095                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2039                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        44373                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       378725                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1858                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1828                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        37641                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       375939                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          844498                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        26185                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17286                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        16940                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        16418                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76829                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16057                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        17652                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33709                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        26185                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        33343                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        16940                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        34070                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110538                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    158916500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    159756000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    143576000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    139934500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    602183000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    365788000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    355619500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    721407500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        20500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        90000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  17116792000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  16833400500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  33950192500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   3177306000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2684393500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   5861699500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data   9937629500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10024806000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  19962435500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  17370364500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  17846311500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  35216676000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    158916500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    159756000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   3177306000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  27054421500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    143576000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    139934500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2684393500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  26858206500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  60376510500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    158916500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    159756000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   3177306000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  27054421500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    143576000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    139934500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2684393500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  26858206500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  60376510500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1631918500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2761184000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1058142000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2648695500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8099940000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2682292500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2625286500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5307579000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1631918500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5443476500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1058142000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5273982000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  13407519000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008714                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.012363                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.011087                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.009714                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781889                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781951                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.781920                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.231313                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.226518                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.228910                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005914                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.040908                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040593                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040750                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.410529                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.419151                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.414851                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.008714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.012363                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.086564                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.011087                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.084774                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.035963                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.008714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.012363                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.006403                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.086564                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.007913                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.011087                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005426                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.084774                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.035963                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77005.498721                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20655.485911                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.137364                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20655.314093                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        20500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        45000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70537.296580                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70520.567486                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70529.000862                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71471.937718                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 73037.508636                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73047.399754                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73042.475457                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69043.995246                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69120.579339                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69082.783581                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71435.531058                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71442.990751                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 71493.965054                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75855.131265                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78350.171653                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71604.489216                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71435.531058                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77274.488698                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76550.601751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71315.679711                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71442.990751                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 71493.965054                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159735.277103                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161328.755025                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105428.158638                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167048.172137                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 148724.592114                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157452.876087                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62322.646553                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163256.950484                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62464.108619                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154798.415028                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 121293.301851                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76829                       # Transaction distribution
system.membus.trans_dist::ReadResp             448840                       # Transaction distribution
system.membus.trans_dist::WriteReq              33709                       # Transaction distribution
system.membus.trans_dist::WriteResp             33709                       # Transaction distribution
system.membus.trans_dist::Writeback           1181427                       # Transaction distribution
system.membus.trans_dist::CleanEvict           191531                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            35493                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           35495                       # Transaction distribution
system.membus.trans_dist::ReadExReq            990576                       # Transaction distribution
system.membus.trans_dist::ReadExResp           990576                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        372011                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      4129743                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      4259441                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       340465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4599906                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    155575648                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    155745486                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7203136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7203136                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               162948622                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3620                       # Total snoops (count)
system.membus.snoop_fanout::samples           2991422                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2991422    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2991422                       # Request fanout histogram
system.membus.reqLayer0.occupancy           107341500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5250000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7710006309                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7440287022                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          228944719                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq            1264904                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          21840032                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33709                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33709                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          8906693                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict        16372534                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           44670                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          44672                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2102857                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2102857                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      13867412                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6715681                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1335478                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1228814                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41686402                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30339787                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       785213                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1207911                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              74019313                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    887686868                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1058482234                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2638496                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3801896                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             1952609494                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1875627                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         50645688                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.052912                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.223858                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1               47965928     94.71%     94.71% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                2679760      5.29%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           50645688                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        32319092000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1371000                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       20844243000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       13901838902                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         455401000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         732674000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------