path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.771755                       # Number of seconds simulated
sim_ticks                                51771755296500                       # Number of ticks simulated
final_tick                               51771755296500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 629134                       # Simulator instruction rate (inst/s)
host_op_rate                                   739361                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            39432920775                       # Simulator tick rate (ticks/s)
host_mem_usage                                 676920                       # Number of bytes of host memory used
host_seconds                                  1312.91                       # Real time elapsed on the host
sim_insts                                   825994487                       # Number of instructions simulated
sim_ops                                     970712321                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker        69120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker        72384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2314776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         32049840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        60480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        66688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2364572                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         32106392                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        391424                       # Number of bytes read from this memory
system.physmem.bytes_read::total             69495676                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2314776                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2364572                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         4679348                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     60509440                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         15860                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data          4720                       # Number of bytes written to this memory
system.physmem.bytes_written::total          60530020                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1080                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1131                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             56829                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            500782                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker          945                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1042                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56693                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            501672                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6116                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1126290                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          945460                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             1983                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data              590                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               948033                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          1335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1398                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               44711                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              619060                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1168                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          1288                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               45673                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              620153                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7561                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1342347                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          44711                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          45673                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              90384                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1168773                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                306                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 91                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1169171                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1168773                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         1335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1398                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              44711                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             619367                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1168                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         1288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              45673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             620244                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7561                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2511518                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1126290                       # Number of read requests accepted
system.physmem.writeReqs                       948033                       # Number of write requests accepted
system.physmem.readBursts                     1126290                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     948033                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 72036608                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     45952                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  60529408                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  69495676                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               60530020                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      718                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2260                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         294002                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               72701                       # Per bank write bursts
system.physmem.perBankRdBursts::1               69688                       # Per bank write bursts
system.physmem.perBankRdBursts::2               71671                       # Per bank write bursts
system.physmem.perBankRdBursts::3               65333                       # Per bank write bursts
system.physmem.perBankRdBursts::4               67150                       # Per bank write bursts
system.physmem.perBankRdBursts::5               75432                       # Per bank write bursts
system.physmem.perBankRdBursts::6               63718                       # Per bank write bursts
system.physmem.perBankRdBursts::7               62281                       # Per bank write bursts
system.physmem.perBankRdBursts::8               61723                       # Per bank write bursts
system.physmem.perBankRdBursts::9              108434                       # Per bank write bursts
system.physmem.perBankRdBursts::10              66581                       # Per bank write bursts
system.physmem.perBankRdBursts::11              66036                       # Per bank write bursts
system.physmem.perBankRdBursts::12              64933                       # Per bank write bursts
system.physmem.perBankRdBursts::13              72823                       # Per bank write bursts
system.physmem.perBankRdBursts::14              65732                       # Per bank write bursts
system.physmem.perBankRdBursts::15              71336                       # Per bank write bursts
system.physmem.perBankWrBursts::0               59678                       # Per bank write bursts
system.physmem.perBankWrBursts::1               59397                       # Per bank write bursts
system.physmem.perBankWrBursts::2               61038                       # Per bank write bursts
system.physmem.perBankWrBursts::3               58102                       # Per bank write bursts
system.physmem.perBankWrBursts::4               58442                       # Per bank write bursts
system.physmem.perBankWrBursts::5               63800                       # Per bank write bursts
system.physmem.perBankWrBursts::6               56091                       # Per bank write bursts
system.physmem.perBankWrBursts::7               56307                       # Per bank write bursts
system.physmem.perBankWrBursts::8               55145                       # Per bank write bursts
system.physmem.perBankWrBursts::9               60224                       # Per bank write bursts
system.physmem.perBankWrBursts::10              58756                       # Per bank write bursts
system.physmem.perBankWrBursts::11              59336                       # Per bank write bursts
system.physmem.perBankWrBursts::12              57263                       # Per bank write bursts
system.physmem.perBankWrBursts::13              62824                       # Per bank write bursts
system.physmem.perBankWrBursts::14              57899                       # Per bank write bursts
system.physmem.perBankWrBursts::15              61470                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          14                       # Number of times write queue was full causing retry
system.physmem.totGap                    51771752359500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1083174                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 945460                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                   1099993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     20089                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       406                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       349                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       456                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       525                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1098                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       632                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      330                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      115                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      105                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       65                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1523                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1456                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1436                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13923                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    16729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    52857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    53872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    55240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    55119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    56051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    56007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    57237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    56745                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    56988                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    61194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    56201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    54839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    55500                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    53521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    52708                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    51972                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      287                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      313                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      236                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      325                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      254                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      189                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      171                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       38                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       442229                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      299.767080                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     172.615293                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.948153                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         176550     39.92%     39.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       107641     24.34%     64.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        38242      8.65%     72.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        22044      4.98%     77.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15615      3.53%     81.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11547      2.61%     84.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10103      2.28%     86.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8633      1.95%     88.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        51854     11.73%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         442229                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         52882                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.284426                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      294.979543                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          52875     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            3      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           52882                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         52882                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.884573                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.137705                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.800600                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3               115      0.22%      0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                64      0.12%      0.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               68      0.13%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15             119      0.23%      0.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           49331     93.29%     93.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             541      1.02%     95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             348      0.66%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             615      1.16%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             130      0.25%     97.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             329      0.62%     97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             199      0.38%     98.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              29      0.05%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              82      0.16%     98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55             151      0.29%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              24      0.05%     98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              42      0.08%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             468      0.88%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              24      0.05%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              19      0.04%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             123      0.23%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               6      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               3      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            28      0.05%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             5      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             3      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           52882                       # Writes before turning the bus around for reads
system.physmem.totQLat                    13860867186                       # Total ticks spent queuing
system.physmem.totMemAccLat               34965342186                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5627860000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12314.51                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31064.51                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.39                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.34                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.22                       # Average write queue length when enqueuing
system.physmem.readRowHits                     909331                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    719783                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.79                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.11                       # Row buffer hit rate for writes
system.physmem.avgGap                     24958385.15                       # Average gap between requests
system.physmem.pageHitRate                      78.65                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1706473440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  931111500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4274158200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3064100400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3381479010000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1298516894550                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29923999959000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34613971707090                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.588021                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49780674651877                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1728772500000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    262307488123                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1636777800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  893083125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4505264400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3064502160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3381479010000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1291239562905                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29930383583250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34613201783640                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.573149                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49791285234291                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1728772500000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    251692056959                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                   115460                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               115460                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17717                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        83741                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           10                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       115450                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean     0.259853                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev    63.668442                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047       115448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       115450                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       101468                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 25057.924666                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21784.198284                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16152.265883                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       100874     99.41%     99.41% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071            1      0.00%     99.42% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          517      0.51%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143            5      0.00%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           33      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           13      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           19      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       101468                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples  -3983763676                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.449006                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     1788733704    -44.90%    -44.90% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    -5772497380    144.90%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total  -3983763676                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        83741     82.54%     82.54% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        17717     17.46%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       101458                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       115460                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       115460                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       101458                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       101458                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       216918                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    77974126                       # DTB read hits
system.cpu0.dtb.read_misses                     88549                       # DTB read misses
system.cpu0.dtb.write_hits                   70569009                       # DTB write hits
system.cpu0.dtb.write_misses                    26911                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51778                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              18628                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    500                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   67577                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  3961                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9183                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                78062675                       # DTB read accesses
system.cpu0.dtb.write_accesses               70595920                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        148543135                       # DTB hits
system.cpu0.dtb.misses                         115460                       # DTB misses
system.cpu0.dtb.accesses                    148658595                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                    74491                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                74491                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4184                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        65168                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        74491                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          74491    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        74491                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        69352                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28600.025955                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 25396.938168                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18997.799631                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        68658     99.00%     99.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071            2      0.00%     99.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          606      0.87%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           12      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           31      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           21      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        69352                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   1705681704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     1705681704    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   1705681704                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        65168     93.97%     93.97% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4184      6.03%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        69352                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        74491                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        74491                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        69352                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        69352                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       143843                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   413472692                       # ITB inst hits
system.cpu0.itb.inst_misses                     74491                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51778                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              18628                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    500                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   50115                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               413547183                       # ITB inst accesses
system.cpu0.itb.hits                        413472692                       # DTB hits
system.cpu0.itb.misses                          74491                       # DTB misses
system.cpu0.itb.accesses                    413547183                       # DTB accesses
system.cpu0.numCycles                     51772397578                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   15961                       # number of quiesce instructions executed
system.cpu0.committedInsts                  413219664                       # Number of instructions committed
system.cpu0.committedOps                    485565994                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            446433803                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                442229                       # Number of float alu accesses
system.cpu0.num_func_calls                   24786010                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     62671041                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   446433803                       # number of integer instructions
system.cpu0.num_fp_insts                       442229                       # number of float instructions
system.cpu0.num_int_register_reads          644929511                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         353812607                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              719009                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             362960                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           107066643                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          106758859                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    148533323                       # number of memory refs
system.cpu0.num_load_insts                   77969520                       # Number of load instructions
system.cpu0.num_store_insts                  70563803                       # Number of store instructions
system.cpu0.num_idle_cycles              50229359275.953438                       # Number of idle cycles
system.cpu0.num_busy_cycles              1543038302.046558                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.029804                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.970196                       # Percentage of idle cycles
system.cpu0.Branches                         92169862                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                336128174     69.18%     69.18% # Class of executed instruction
system.cpu0.op_class::IntMult                 1076007      0.22%     69.41% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49967      0.01%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  8      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                 13      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                 20      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.42% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             53572      0.01%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.43% # Class of executed instruction
system.cpu0.op_class::MemRead                77969520     16.05%     85.48% # Class of executed instruction
system.cpu0.op_class::MemWrite               70563803     14.52%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 485841084                       # Class of executed instruction
system.cpu0.dcache.tags.replacements          9212621                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.942746                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          287301900                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9213133                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            31.183952                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       5830459500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   301.496360                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   210.446385                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.588860                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.411028                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999888                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          414                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1195722346                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1195722346                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     73035245                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     72652643                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      145687888                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     67007378                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     67030482                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     134037860                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       184933                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       187057                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       371990                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165113                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       167764                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       332877                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1642151                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1632221                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3274372                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1781285                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1774075                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3555360                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    140042623                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    139683125                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       279725748                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    140227556                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    139870182                       # number of overall hits
system.cpu0.dcache.overall_hits::total      280097738                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2403483                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2400966                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      4804449                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       980962                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data       977666                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1958628                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       551880                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       550634                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1102514                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       610138                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       608619                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1218757                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       139928                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       142675                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       282603                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3384445                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      3378632                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       6763077                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      3936325                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      3929266                       # number of overall misses
system.cpu0.dcache.overall_misses::total      7865591                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41217416000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  41024037000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  82241453000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33031636500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  32712637000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  65744273500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  36135211500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  36878672000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  73013883500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2143987500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2178071000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4322058500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  74249052500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  73736674000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 147985726500                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  74249052500                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  73736674000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 147985726500                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     75438728                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     75053609                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    150492337                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     67988340                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     68008148                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    135996488                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       736813                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       737691                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1474504                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       775251                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       776383                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1551634                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1782079                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1774896                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3556975                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1781285                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1774076                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3555361                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    143427068                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    143061757                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    286488825                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    144163881                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    143799448                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    287963329                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031860                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031990                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.031925                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014428                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014376                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.014402                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.749010                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.746429                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747719                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.787020                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.783916                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.785467                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078520                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080385                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.079450                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023597                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.023617                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.023607                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027305                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.027325                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.027315                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17149.035795                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17086.471445                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17117.770009                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33672.697311                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33459.931101                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 33566.493229                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59224.653275                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60594.020233                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59908.483397                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15322.076354                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15265.961100                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15293.745997                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21938.324452                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21824.417101                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 21881.419730                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18862.531041                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18766.017368                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18814.317513                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7219847                       # number of writebacks
system.cpu0.dcache.writebacks::total          7219847                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        11900                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        10524                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        22424                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        11494                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         9715                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21209                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        33194                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        33628                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        66822                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        23394                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        20239                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        43633                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        23394                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        20239                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        43633                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2391583                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2390442                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      4782025                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       969468                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       967951                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1937419                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       550930                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       549790                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1100720                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       610138                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       608619                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1218757                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       106734                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       109047                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       215781                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3361051                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3358393                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      6719444                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      3911981                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      3908183                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      7820164                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16515                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17184                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33699                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        16888                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        16819                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        33403                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        34003                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67406                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38123459500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  38015008500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  76138468000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  31542881000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31287443500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  62830324500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10406081000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10129235000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  20535316000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  35525073500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  36270053000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  71795126500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1470813500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1497747500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2968561000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  69666340500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  69302452000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 138968792500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  80072421500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  79431687000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 159504108500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3017045500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3182297000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6199342500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   3020495500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3197083500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   6217579000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   6037541000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6379380500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  12416921500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031702                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031850                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.031776                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014259                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014233                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014246                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.747720                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.745285                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.746502                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.787020                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.783916                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.785467                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059893                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061439                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060664                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023434                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.023475                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023454                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027136                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.027178                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.027157                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15940.680085                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15902.920255                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15921.804675                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32536.278660                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32323.375357                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32429.910360                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18888.209028                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18423.825461                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18656.257722                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58224.653275                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59594.020233                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58908.483397                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13780.177825                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13734.880373                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13757.286323                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20727.546384                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20635.599229                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20681.590992                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20468.509816                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20324.454356                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20396.517068                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182685.165002                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185189.536778                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183962.209561                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178854.541686                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190087.609251                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.578129                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180748.465707                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187612.284210                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184210.923360                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         13370435                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.782255                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          813133937                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13370947                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            60.813489                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      61705740500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   285.320721                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   226.461534                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.557267                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.442308                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999575                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          202                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        839875841                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       839875841                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    406751315                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    406382622                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      813133937                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    406751315                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    406382622                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       813133937                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    406751315                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    406382622                       # number of overall hits
system.cpu0.icache.overall_hits::total      813133937                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6721377                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6649575                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13370952                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6721377                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6649575                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13370952                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6721377                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6649575                       # number of overall misses
system.cpu0.icache.overall_misses::total     13370952                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91746511500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90909260000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 182655771500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  91746511500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  90909260000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 182655771500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  91746511500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  90909260000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 182655771500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    413472692                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    413032197                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    826504889                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    413472692                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    413032197                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    826504889                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    413472692                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    413032197                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    826504889                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016256                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016099                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.016178                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016256                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016099                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.016178                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016256                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016099                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.016178                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13649.957665                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.439152                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.640731                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13649.957665                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13671.439152                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13660.640731                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13649.957665                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13671.439152                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13660.640731                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.writebacks::writebacks     13370435                       # number of writebacks
system.cpu0.icache.writebacks::total         13370435                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6721377                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6649575                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13370952                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6721377                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6649575                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13370952                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6721377                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6649575                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13370952                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        22062                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        21063                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        22062                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        21063                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85025134500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  84259685000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 169284819500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85025134500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  84259685000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 169284819500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85025134500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  84259685000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 169284819500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   5436799500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2780591500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   2656208000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   5436799500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016178                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.016178                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016256                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016099                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.016178                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12660.640731                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12660.640731                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12649.957665                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12671.439152                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.640731                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                   118174                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               118174                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17820                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        86207                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore            6                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       118168                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         118168    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       118168                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       104033                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25040.588083                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21749.548904                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15700.304805                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       103488     99.48%     99.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071            2      0.00%     99.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          470      0.45%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143            4      0.00%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           36      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215            6      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           22      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       104033                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -1363590484                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     2.149961                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean          inf                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1568075704   -115.00%   -115.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -2931666188    215.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1363590484                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        86208     82.87%     82.87% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        17820     17.13%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       104028                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       118174                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       118174                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       104028                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       104028                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       222202                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    77583369                       # DTB read hits
system.cpu1.dtb.read_misses                     91391                       # DTB read misses
system.cpu1.dtb.write_hits                   70584225                       # DTB write hits
system.cpu1.dtb.write_misses                    26783                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51774                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              19034                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    497                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   67777                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  3786                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9337                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                77674760                       # DTB read accesses
system.cpu1.dtb.write_accesses               70611008                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        148167594                       # DTB hits
system.cpu1.dtb.misses                         118174                       # DTB misses
system.cpu1.dtb.accesses                    148285768                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                    75448                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                75448                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4153                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66142                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        75448                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          75448    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        75448                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        70295                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28625.784195                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25406.753839                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18792.899470                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        69604     99.02%     99.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071            1      0.00%     99.02% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          599      0.85%     99.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           17      0.02%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           33      0.05%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           15      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751           19      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            4      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        70295                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1449734704                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1449734704    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1449734704                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        66142     94.09%     94.09% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4153      5.91%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        70295                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        75448                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        75448                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        70295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        70295                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       145743                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   413032197                       # ITB inst hits
system.cpu1.itb.inst_misses                     75448                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51774                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              19034                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    497                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   50656                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               413107645                       # ITB inst accesses
system.cpu1.itb.hits                        413032197                       # DTB hits
system.cpu1.itb.misses                          75448                       # DTB misses
system.cpu1.itb.accesses                    413107645                       # DTB accesses
system.cpu1.numCycles                     51771113015                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  412774823                       # Number of instructions committed
system.cpu1.committedOps                    485146327                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            446024475                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                456863                       # Number of float alu accesses
system.cpu1.num_func_calls                   24836924                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     62537039                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   446024475                       # number of integer instructions
system.cpu1.num_fp_insts                       456863                       # number of float instructions
system.cpu1.num_int_register_reads          646025772                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         353451520                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              733263                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             394304                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           106699743                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          106398156                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    148156265                       # number of memory refs
system.cpu1.num_load_insts                   77578568                       # Number of load instructions
system.cpu1.num_store_insts                  70577697                       # Number of store instructions
system.cpu1.num_idle_cycles              50233500723.542557                       # Number of idle cycles
system.cpu1.num_busy_cycles              1537612291.457444                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.029700                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.970300                       # Percentage of idle cycles
system.cpu1.Branches                         92112103                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                336122870     69.24%     69.24% # Class of executed instruction
system.cpu1.op_class::IntMult                 1039751      0.21%     69.46% # Class of executed instruction
system.cpu1.op_class::IntDiv                    47048      0.01%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  1      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             58827      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::MemRead                77578568     15.98%     85.46% # Class of executed instruction
system.cpu1.op_class::MemWrite               70577697     14.54%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 485424763                       # Class of executed instruction
system.iobus.trans_dist::ReadReq                40321                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40321                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231000                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231000                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353784                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334432                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334432                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492352                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42150500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               322500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               16500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25707000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38602500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           565399896                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147760000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115482                       # number of replacements
system.iocache.tags.tagsinuse               10.442874                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115498                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13183784929000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.514153                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.928721                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219635                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.433045                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.652680                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039857                       # Number of tag accesses
system.iocache.tags.data_accesses             1039857                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8836                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8873                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8836                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8876                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8836                       # number of overall misses
system.iocache.overall_misses::total             8876                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5087000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1609197370                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1614284370                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13863548526                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13863548526                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5438000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1609197370                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1614635370                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5438000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1609197370                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1614635370                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8836                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8873                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8836                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8876                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8836                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8876                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137486.486486                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182118.308058                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 181932.195424                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.016782                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129974.016782                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135950                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 182118.308058                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 181910.248986                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135950                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 182118.308058                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 181910.248986                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         32984                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3440                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.588372                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8836                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8873                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8836                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8876                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8836                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8876                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3237000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1167397370                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1170634370                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8530348526                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8530348526                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3438000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1167397370                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1170835370                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3438000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1167397370                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1170835370                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87486.486486                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132118.308058                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 131932.195424                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.016782                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.016782                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85950                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132118.308058                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131910.248986                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85950                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132118.308058                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131910.248986                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   987985                       # number of replacements
system.l2c.tags.tagsinuse                65209.498770                       # Cycle average of tags in use
system.l2c.tags.total_refs                   41654495                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1049725                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    39.681340                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle              56075802500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   37651.465010                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   109.956357                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   153.679221                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     4175.861855                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9735.363337                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker    92.633503                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   148.604603                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4437.462816                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     8704.472068                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.574516                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.001678                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.002345                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.063719                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.148550                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.001413                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.002268                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.067710                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.132820                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995018                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          271                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        61469                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          270                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2443                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5529                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53059                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004135                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.937943                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                371736931                       # Number of tag accesses
system.l2c.tags.data_accesses               371736931                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       204252                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       156439                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       209151                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       158768                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 728610                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7219847                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7219847                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     13368850                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        13368850                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            4381                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4519                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                8900                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           792721                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           793036                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1585757                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       6686573                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       6613945                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          13300518                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      2939731                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      2942858                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          5882589                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       374559                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       366598                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           741157                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        204252                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        156439                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6686573                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3732452                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        209151                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        158768                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6613945                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             3735894                       # number of demand (read+write) hits
system.l2c.demand_hits::total                21497474                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       204252                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       156439                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6686573                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3732452                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       209151                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       158768                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6613945                       # number of overall hits
system.l2c.overall_hits::cpu1.data            3735894                       # number of overall hits
system.l2c.overall_hits::total               21497474                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1080                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1131                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker          945                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         1042                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 4198                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         16117                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         16535                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             32652                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         156249                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         153861                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             310110                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        34804                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        35630                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           70434                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       109516                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       106421                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         215937                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       235579                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       242021                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         477600                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1080                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1131                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             34804                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            265765                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker          945                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1042                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             35630                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            260282                       # number of demand (read+write) misses
system.l2c.demand_misses::total                600679                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1080                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1131                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            34804                       # number of overall misses
system.l2c.overall_misses::cpu0.data           265765                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker          945                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1042                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            35630                       # number of overall misses
system.l2c.overall_misses::cpu1.data           260282                       # number of overall misses
system.l2c.overall_misses::total               600679                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    147426500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    155324000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    129822500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    143643500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      576216500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    665032000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    692059000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total   1357091000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        79500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        79500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  20394322000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  20102389000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  40496711000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   4601700500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   4707495500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   9309196000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  14521893000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  14130831500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  28652724500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data  30676991000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data  31507845000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total  62184836000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    147426500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    155324000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   4601700500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  34916215000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    129822500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    143643500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   4707495500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  34233220500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     79034848000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    147426500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    155324000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   4601700500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  34916215000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    129822500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    143643500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   4707495500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  34233220500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    79034848000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       205332                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       157570                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       210096                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       159810                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             732808                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7219847                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7219847                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     13368850                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     13368850                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        20498                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        21054                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           41552                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       948970                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       946897                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1895867                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6721377                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      6649575                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      13370952                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3049247                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3049279                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6098526                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       610138                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       608619                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1218757                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       205332                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       157570                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6721377                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         3998217                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       210096                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       159810                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6649575                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         3996176                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            22098153                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       205332                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       157570                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6721377                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        3998217                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       210096                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       159810                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6649575                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        3996176                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           22098153                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.005260                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.007178                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.004498                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.006520                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.005729                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.786272                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.785361                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.785811                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.164651                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.162490                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.163572                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005178                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005358                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005268                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.035916                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.034900                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.035408                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.386108                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.397656                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.391875                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.005260                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.007178                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005178                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.066471                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.004498                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.006520                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005358                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.065133                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.027182                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.005260                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.007178                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005178                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.066471                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.004498                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.006520                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005358                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.065133                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.027182                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 136506.018519                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137333.333333                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137378.306878                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137853.646833                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 137259.766556                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41262.766023                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 41854.188086                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 41562.262649                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        79500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        79500                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130524.496157                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130652.920493                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 130588.213860                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 132217.575566                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132121.681168                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 132169.066076                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132600.651960                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132782.359685                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 132690.203624                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 130219.548432                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130186.409444                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 130202.755444                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136506.018519                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137333.333333                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 132217.575566                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 131380.034993                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137378.306878                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137853.646833                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132121.681168                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131523.580194                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 131575.846667                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136506.018519                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137333.333333                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 132217.575566                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 131380.034993                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137378.306878                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137853.646833                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132121.681168                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131523.580194                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 131575.846667                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              838829                       # number of writebacks
system.l2c.writebacks::total                   838829                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1080                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1131                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          945                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1042                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            4198                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        16117                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        16535                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        32652                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       156249                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       153861                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        310110                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        34804                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        35630                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        70434                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       109516                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       106421                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       215937                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       235579                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       242021                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       477600                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1080                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1131                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        34804                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       265765                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker          945                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1042                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        35630                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       260282                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           600679                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1080                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1131                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        34804                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       265765                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker          945                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1042                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        35630                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       260282                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          600679                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        22062                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16515                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        21063                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17184                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76824                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        16888                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        16819                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33707                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        22062                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        33403                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        21063                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        34003                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110531                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    136626500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    144014000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    120372500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    133223500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    534236500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data   1139235500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data   1168732000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   2307967500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        69500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  18831832000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18563779000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  37395611000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   4253660500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   4351195500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   8604856000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  13426733000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13066621500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  26493354500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  28321201000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data  29087635000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  57408836000                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    136626500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    144014000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   4253660500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  32258565000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    120372500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    133223500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   4351195500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  31630400500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  73028058000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    136626500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    144014000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   4253660500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  32258565000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    120372500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    133223500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   4351195500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  31630400500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  73028058000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2810237000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   2392920500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2967094000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  10675068000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2826278000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   3003660000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5829938000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   2504816500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   5636515000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   2392920500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5970754000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  16505006000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005260                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.007178                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.004498                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.006520                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.005729                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.786272                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.785361                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.785811                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.164651                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.162490                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.163572                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005178                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005358                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005268                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.035916                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.034900                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.035408                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.386108                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.397656                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.391875                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.005260                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.007178                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005178                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.066471                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.004498                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.006520                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005358                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.065133                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.027182                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.005260                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.007178                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005178                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.066471                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.004498                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.006520                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005358                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.065133                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.027182                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127259.766556                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70685.332258                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.310251                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70683.801911                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        69500                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120524.496157                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120652.920493                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120588.213860                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122169.066076                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122600.651960                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122782.359685                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122690.203624                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120219.548432                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120186.409444                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120202.755444                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121380.034993                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121523.580194                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 121575.846667                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122217.575566                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121380.034993                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122121.681168                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121523.580194                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 121575.846667                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170162.700575                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172666.084730                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138954.857857                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167354.216011                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178587.311969                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168742.777595                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175594.918095                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 149324.678145                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               76824                       # Transaction distribution
system.membus.trans_dist::ReadResp             376266                       # Transaction distribution
system.membus.trans_dist::WriteReq              33707                       # Transaction distribution
system.membus.trans_dist::WriteResp             33707                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       945460                       # Transaction distribution
system.membus.trans_dist::CleanEvict           154121                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            33223                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           33224                       # Transaction distribution
system.membus.trans_dist::ReadExReq            787142                       # Transaction distribution
system.membus.trans_dist::ReadExResp           787142                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        299442                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       106664                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6922                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3299562                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3429246                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       340924                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       340924                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                3770170                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13844                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    122809888                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    122979698                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7215808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7215808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               130195506                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3417                       # Total snoops (count)
system.membus.snoop_fanout::samples           2439476                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2439476    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2439476                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106887500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5646000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          6220729239                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         5972547051                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          227475321                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests     45741552                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     23157457                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1749                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2207                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2207                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq            1182207                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          20652494                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33707                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33707                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      8165321                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     13368850                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2150617                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           41555                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          41556                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1895867                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1895867                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      13370952                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6107399                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1325421                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1218757                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     40197004                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27857487                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       758584                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1079607                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              69892682                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1711519828                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    973953566                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2539040                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3323424                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2691335858                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1592408                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         25060590                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021420                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.144781                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               24523786     97.86%     97.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 536804      2.14%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           25060590                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        43819448000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1523382                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       20099553000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       12672308976                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         441204000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         664179000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------