path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.820973                       # Number of seconds simulated
sim_ticks                                51820973246500                       # Number of ticks simulated
final_tick                               51820973246500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 758799                       # Simulator instruction rate (inst/s)
host_op_rate                                   891661                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            43998522404                       # Simulator tick rate (ticks/s)
host_mem_usage                                 681336                       # Number of bytes of host memory used
host_seconds                                  1177.79                       # Real time elapsed on the host
sim_insts                                   893704771                       # Number of instructions simulated
sim_ops                                    1050188306                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       125632                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       134272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2648688                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         26060912                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       150272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       137792                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2660612                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         25358744                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        379264                       # Number of bytes read from this memory
system.physmem.bytes_read::total             57656188                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2648688                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2660612                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5309300                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78776832                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78797412                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1963                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2098                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             65667                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            407205                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2348                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2153                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             57698                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            396240                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           5926                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                941298                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1230888                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1233461                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2424                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2591                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               51112                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              502903                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2900                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2659                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               51342                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              489353                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7319                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1112603                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          51112                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          51342                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             102455                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1520173                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1520570                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1520173                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2424                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2591                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              51112                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             502903                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2900                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2659                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              51342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             489750                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7319                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2633173                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        941298                       # Number of read requests accepted
system.physmem.writeReqs                      1233461                       # Number of write requests accepted
system.physmem.readBursts                      941298                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1233461                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 60206144                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     36928                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78797632                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  57656188                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78797412                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      577                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               57499                       # Per bank write bursts
system.physmem.perBankRdBursts::1               62142                       # Per bank write bursts
system.physmem.perBankRdBursts::2               57490                       # Per bank write bursts
system.physmem.perBankRdBursts::3               55825                       # Per bank write bursts
system.physmem.perBankRdBursts::4               53833                       # Per bank write bursts
system.physmem.perBankRdBursts::5               61722                       # Per bank write bursts
system.physmem.perBankRdBursts::6               53577                       # Per bank write bursts
system.physmem.perBankRdBursts::7               53386                       # Per bank write bursts
system.physmem.perBankRdBursts::8               55741                       # Per bank write bursts
system.physmem.perBankRdBursts::9              100411                       # Per bank write bursts
system.physmem.perBankRdBursts::10              55379                       # Per bank write bursts
system.physmem.perBankRdBursts::11              62273                       # Per bank write bursts
system.physmem.perBankRdBursts::12              51298                       # Per bank write bursts
system.physmem.perBankRdBursts::13              56710                       # Per bank write bursts
system.physmem.perBankRdBursts::14              52113                       # Per bank write bursts
system.physmem.perBankRdBursts::15              51322                       # Per bank write bursts
system.physmem.perBankWrBursts::0               75972                       # Per bank write bursts
system.physmem.perBankWrBursts::1               80204                       # Per bank write bursts
system.physmem.perBankWrBursts::2               78083                       # Per bank write bursts
system.physmem.perBankWrBursts::3               78701                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75891                       # Per bank write bursts
system.physmem.perBankWrBursts::5               81886                       # Per bank write bursts
system.physmem.perBankWrBursts::6               74948                       # Per bank write bursts
system.physmem.perBankWrBursts::7               74400                       # Per bank write bursts
system.physmem.perBankWrBursts::8               74844                       # Per bank write bursts
system.physmem.perBankWrBursts::9               78454                       # Per bank write bursts
system.physmem.perBankWrBursts::10              75419                       # Per bank write bursts
system.physmem.perBankWrBursts::11              80852                       # Per bank write bursts
system.physmem.perBankWrBursts::12              73391                       # Per bank write bursts
system.physmem.perBankWrBursts::13              78907                       # Per bank write bursts
system.physmem.perBankWrBursts::14              74453                       # Per bank write bursts
system.physmem.perBankWrBursts::15              74808                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
system.physmem.totGap                    51820970325500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  898182                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1230888                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    907166                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     28188                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       382                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       299                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       583                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       455                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1201                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      345                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      154                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      102                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       98                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       89                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       65                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       45                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1619                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1543                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1511                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1457                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1420                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    33965                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39434                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    66705                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    69572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    73099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    70516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    69275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    71602                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    74263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71156                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76473                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    74873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    70803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    68999                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    68901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    66607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    65182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      256                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      240                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      230                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      160                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       566411                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      245.410940                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     147.848960                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     286.502889                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         251457     44.39%     44.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       147984     26.13%     70.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        50578      8.93%     79.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27084      4.78%     84.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18527      3.27%     87.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12015      2.12%     89.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8676      1.53%     91.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7490      1.32%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        42600      7.52%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         566411                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         65859                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.283773                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      106.722670                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          65854     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           65859                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         65859                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.694681                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.068066                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.774692                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3               123      0.19%      0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                75      0.11%      0.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               55      0.08%      0.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15             134      0.20%      0.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           51847     78.72%     79.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9800     14.88%     94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            1125      1.71%     95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             552      0.84%     96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             892      1.35%     98.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             360      0.55%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              86      0.13%     98.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              48      0.07%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              56      0.09%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              44      0.07%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              24      0.04%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              39      0.06%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             432      0.66%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              30      0.05%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              32      0.05%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              26      0.04%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              20      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               6      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             7      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.03%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           65859                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12279482516                       # Total ticks spent queuing
system.physmem.totMemAccLat               29918001266                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4703605000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13053.27                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31803.27                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        11.56                       # Average write queue length when enqueuing
system.physmem.readRowHits                     706352                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    899170                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.09                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.03                       # Row buffer hit rate for writes
system.physmem.avgGap                     23828373.78                       # Average gap between requests
system.physmem.pageHitRate                      73.92                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2184439320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1191906375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3552658200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4018150800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1306740976245                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29946315984000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34648697732700                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.623145                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49817760765674                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730415960000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    272796109326                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2097627840                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1144539000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3784926600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3960109440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1304293519080                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29948462876250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34648437215970                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.618118                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49821299610951                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730415960000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    269251106549                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   131570                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               131570                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20583                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94968                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       131563                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         131563    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       131563                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       115558                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 24585.701552                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21339.790503                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 14301.317993                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       114596     99.17%     99.17% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          825      0.71%     99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           55      0.05%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           25      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       115558                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   4911919556                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.054990                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -270104796     -5.50%     -5.50% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     5182024352    105.50%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   4911919556                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        94969     82.19%     82.19% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        20583     17.81%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       115552                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       131570                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       131570                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       115552                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       115552                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       247122                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83870325                       # DTB read hits
system.cpu0.dtb.read_misses                    100143                       # DTB read misses
system.cpu0.dtb.write_hits                   76256860                       # DTB write hits
system.cpu0.dtb.write_misses                    31427                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   73309                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4917                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9888                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83970468                       # DTB read accesses
system.cpu0.dtb.write_accesses               76288287                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        160127185                       # DTB hits
system.cpu0.dtb.misses                         131570                       # DTB misses
system.cpu0.dtb.accesses                    160258755                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    77633                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                77633                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4406                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67615                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        77633                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          77633    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        77633                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        72021                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27701.552325                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24376.545883                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 16846.806682                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        70875     98.41%     98.41% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071          990      1.37%     99.78% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607           61      0.08%     99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143           51      0.07%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        72021                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -294749296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        67615     93.88%     93.88% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4406      6.12%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        72021                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77633                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77633                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72021                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72021                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       149654                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   447669719                       # ITB inst hits
system.cpu0.itb.inst_misses                     77633                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   53432                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               447747352                       # ITB inst accesses
system.cpu0.itb.hits                        447669719                       # DTB hits
system.cpu0.itb.misses                          77633                       # DTB misses
system.cpu0.itb.accesses                    447747352                       # DTB accesses
system.cpu0.numPwrStateTransitions              16472                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         8236                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    5647358953.626396                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   114048668982.955048                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3496     42.45%     42.45% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         4676     56.78%     99.22% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.24% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            4      0.05%     99.28% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.55%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 5700356989224                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           8236                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   5309324904433                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46511648342067                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     51821514544                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16340                       # number of quiesce instructions executed
system.cpu0.committedInsts                  447398457                       # Number of instructions committed
system.cpu0.committedOps                    525429864                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            482287917                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                434588                       # Number of float alu accesses
system.cpu0.num_func_calls                   26374142                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     68421724                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   482287917                       # number of integer instructions
system.cpu0.num_fp_insts                       434588                       # number of float instructions
system.cpu0.num_int_register_reads          704372154                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         382730581                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              702801                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             363748                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           117948117                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          117634638                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    160118732                       # number of memory refs
system.cpu0.num_load_insts                   83867967                       # Number of load instructions
system.cpu0.num_store_insts                  76250765                       # Number of store instructions
system.cpu0.num_idle_cycles              50235171233.913414                       # Number of idle cycles
system.cpu0.num_busy_cycles              1586343310.086583                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.030612                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.969388                       # Percentage of idle cycles
system.cpu0.Branches                         99895335                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                364386062     69.31%     69.31% # Class of executed instruction
system.cpu0.op_class::IntMult                 1119710      0.21%     69.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                    49931      0.01%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             52613      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                83867967     15.95%     85.50% # Class of executed instruction
system.cpu0.op_class::MemWrite               76250765     14.50%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 525727049                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements         10225430                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.965656                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          309996830                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10225942                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.314746                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3504381500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.556484                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   262.409172                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.487415                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.512518                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1291585318                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1291585318                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     78353332                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     78391099                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      156744431                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72326748                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     72506340                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     144833088                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195506                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       198980                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       394486                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165435                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       169679                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       335114                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1850088                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1826878                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3676966                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1999768                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1982892                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3982660                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    150845515                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    151067118                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       301912633                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    151041021                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    151266098                       # number of overall hits
system.cpu0.dcache.overall_hits::total      302307119                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2645926                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2677151                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5323077                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1113708                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1092396                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2206104                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       658322                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       645499                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1303821                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       625844                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       606859                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1232703                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       150530                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       156855                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       307385                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4385478                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      4376406                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       8761884                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5043800                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      5021905                       # number of overall misses
system.cpu0.dcache.overall_misses::total     10065705                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42239397500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42446646000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  84686043500                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33748047000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  32757348500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  66505395500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12855930500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12465111500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25321042000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2217899500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2302924000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4520823500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        84500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        83000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       167500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  88843375000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  87669106000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 176512481000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  88843375000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  87669106000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 176512481000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80999258                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     81068250                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    162067508                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73440456                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73598736                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    147039192                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853828                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       844479                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1698307                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       791279                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       776538                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1567817                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2000618                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1983733                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3984351                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1999769                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1982893                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3982662                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    155230993                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    155443524                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    310674517                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    156084821                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    156288003                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    312372824                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032666                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033023                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032845                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015165                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014843                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015004                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771024                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.764375                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767718                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.790927                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.781493                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786254                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075242                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079071                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077148                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028251                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028154                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028203                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032314                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032132                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032223                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15963.937578                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15855.155723                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15909.227595                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30302.419485                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29986.697590                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30146.083548                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20541.749222                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20540.375112                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20541.072748                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14733.936757                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14681.865417                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14707.365356                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        84500                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        83000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        83750                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20258.538522                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20032.215018                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20145.493937                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17614.373092                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17457.340591                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17536.027630                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      7886218                       # number of writebacks
system.cpu0.dcache.writebacks::total          7886218                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10945                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        12188                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        23133                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9895                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11343                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21238                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35225                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35643                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        70868                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        20840                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        23531                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        44371                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        20840                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        23531                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        44371                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2634981                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2664963                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5299944                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1103813                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1081053                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2184866                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       657436                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       644587                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1302023                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       625844                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       606859                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232703                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115305                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121212                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       236517                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4364638                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      4352875                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      8717513                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5022074                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4997462                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total     10019536                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16630                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17075                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33705                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15387                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18323                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32017                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35398                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67415                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39320815000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39467824000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78788639000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32324995500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31332558500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  63657554000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10585454000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10489503500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21074957500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12230086500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11858252500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24088339000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1546592000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1620640000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3167232000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        83500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       165500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83875897000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82658635000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 166534532000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94461351000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93148138500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 187609489500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232781500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232781500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032531                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032873                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032702                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015030                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014688                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014859                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.769986                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.763295                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766659                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.790927                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781493                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.786254                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057635                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061103                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059361                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028117                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028003                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028060                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032175                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031976                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032076                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14922.618038                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14809.895672                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14865.938017                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29284.847615                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28983.369456                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29135.678801                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16101.117067                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16273.216028                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16186.317369                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19541.749222                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19540.375112                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19541.072748                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13413.052339                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13370.293370                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13391.138903                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        83500                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        82000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        82750                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19217.148593                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18989.434569                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19103.445214                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18809.231206                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18639.088902                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18724.369023                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186648.226097                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183239.912152                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.569500                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96947.246775                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.781909                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92453.927168                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements         13794841                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.891071                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          880461329                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13795353                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            63.823037                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      31612122500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   239.271634                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   272.619438                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.467327                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.532460                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        908052045                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       908052045                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    440828036                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    439633293                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      880461329                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    440828036                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    439633293                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       880461329                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    440828036                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    439633293                       # number of overall hits
system.cpu0.icache.overall_hits::total      880461329                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6841683                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6953675                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13795358                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6841683                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6953675                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13795358                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6841683                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6953675                       # number of overall misses
system.cpu0.icache.overall_misses::total     13795358                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91946479500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93460380000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 185406859500                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  91946479500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  93460380000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 185406859500                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  91946479500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  93460380000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 185406859500                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    447669719                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    446586968                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    894256687                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    447669719                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    446586968                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    894256687                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    447669719                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    446586968                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    894256687                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015283                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015571                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015427                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015283                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015571                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015427                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015283                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015571                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015427                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13439.161022                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13440.429701                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13439.800511                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13439.800511                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13439.800511                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     13794841                       # number of writebacks
system.cpu0.icache.writebacks::total         13794841                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6841683                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6953675                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13795358                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6841683                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6953675                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13795358                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6841683                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6953675                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13795358                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85104796500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86506705000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 171611501500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85104796500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86506705000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 171611501500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85104796500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86506705000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 171611501500                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3263480000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3263480000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015427                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015427                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015427                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12439.800511                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551                       # average overall mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   132777                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               132777                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20416                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        96210                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       132763                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.225967                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    59.372165                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       132761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       132763                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       116640                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24809.139232                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21505.913100                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14394.407415                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767        77454     66.40%     66.40% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535        38152     32.71%     99.11% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303          546      0.47%     99.58% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071          345      0.30%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839            7      0.01%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607           46      0.04%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375            7      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143           32      0.03%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911           26      0.02%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       116640                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples  -4577799504                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.827535                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.377784                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -789509296     17.25%     17.25% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1    -3788290208     82.75%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -4577799504                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        96210     82.49%     82.49% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        20416     17.51%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       116626                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       132777                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       132777                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       116626                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       116626                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       249403                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    83913526                       # DTB read hits
system.cpu1.dtb.read_misses                    101272                       # DTB read misses
system.cpu1.dtb.write_hits                   76384029                       # DTB write hits
system.cpu1.dtb.write_misses                    31505                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   72847                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4726                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    10026                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                84014798                       # DTB read accesses
system.cpu1.dtb.write_accesses               76415534                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        160297555                       # DTB hits
system.cpu1.dtb.misses                         132777                       # DTB misses
system.cpu1.dtb.accesses                    160430332                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    78422                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                78422                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4294                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68564                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        78422                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          78422    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        78422                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        72858                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27889.977765                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24544.855352                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 16997.530464                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767        38730     53.16%     53.16% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535        32903     45.16%     98.32% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303          429      0.59%     98.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071          642      0.88%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607           58      0.08%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375           14      0.02%     99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143           33      0.05%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        72858                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -850152296    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        68564     94.11%     94.11% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4294      5.89%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        72858                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        78422                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        78422                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72858                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72858                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       151280                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   446586968                       # ITB inst hits
system.cpu1.itb.inst_misses                     78422                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   53690                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               446665390                       # ITB inst accesses
system.cpu1.itb.hits                        446586968                       # DTB hits
system.cpu1.itb.misses                          78422                       # DTB misses
system.cpu1.itb.accesses                    446665390                       # DTB accesses
system.cpu1.numPwrStateTransitions              16158                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         8079                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    6172474015.634856                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   126400173933.037643                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3542     43.84%     43.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         4472     55.35%     99.20% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.24% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           12      0.15%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 5966386038488                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           8079                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   1953555674186                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 49867417572314                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     51820431949                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  446306314                       # Number of instructions committed
system.cpu1.committedOps                    524758442                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            481884827                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                461371                       # Number of float alu accesses
system.cpu1.num_func_calls                   26537022                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68126137                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   481884827                       # number of integer instructions
system.cpu1.num_fp_insts                       461371                       # number of float instructions
system.cpu1.num_int_register_reads          702656955                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         382236658                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              740777                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             397264                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           117187848                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          116906080                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    160291234                       # number of memory refs
system.cpu1.num_load_insts                   83910548                       # Number of load instructions
system.cpu1.num_store_insts                  76380686                       # Number of store instructions
system.cpu1.num_idle_cycles              50237560488.814125                       # Number of idle cycles
system.cpu1.num_busy_cycles              1582871460.185875                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030545                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969455                       # Percentage of idle cycles
system.cpu1.Branches                         99714086                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                363557209     69.24%     69.24% # Class of executed instruction
system.cpu1.op_class::IntMult                 1101804      0.21%     69.45% # Class of executed instruction
system.cpu1.op_class::IntDiv                    48133      0.01%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             57875      0.01%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::MemRead                83910548     15.98%     85.45% # Class of executed instruction
system.cpu1.op_class::MemWrite               76380686     14.55%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 525056297                       # Class of executed instruction
system.iobus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40314                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40314                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230986                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230986                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353770                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334376                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492296                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42149000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25704500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38608500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           568719305                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147746000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115474                       # number of replacements
system.iocache.tags.tagsinuse               10.457313                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115490                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13153882422000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510792                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946521                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219424                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434158                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653582                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039794                       # Number of tag accesses
system.iocache.tags.data_accesses             1039794                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8829                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8866                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115493                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115533                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115493                       # number of overall misses
system.iocache.overall_misses::total           115533                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5103000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1592841262                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1597944262                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12773360043                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12773360043                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5454000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14366201305                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14371655305                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5454000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14366201305                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14371655305                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8829                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8866                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115493                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115533                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115493                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115533                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137918.918919                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 180410.155397                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 180232.829010                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119753.244234                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 119753.244234                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124394.374811                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124394.374811                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         30355                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3247                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.348630                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8829                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8866                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115493                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115533                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115493                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115533                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3253000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1151391262                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1154644262                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7433322678                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7433322678                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3454000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8584713940                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8588167940                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3454000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8584713940                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8588167940                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87918.918919                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130410.155397                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 130232.829010                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69689.142335                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69689.142335                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1313152                       # number of replacements
system.l2c.tags.tagsinuse                65370.708254                       # Cycle average of tags in use
system.l2c.tags.total_refs                   46163144                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1376667                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    33.532542                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               6637701500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10009.384485                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   223.831306                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   257.129416                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3503.499374                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    24340.454100                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   220.642740                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   259.400016                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2811.960142                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    23744.406675                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.152731                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003415                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003923                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.053459                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.371406                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003367                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003958                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.042907                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.362311                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.997478                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          266                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        63249                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          266                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2          805                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5995                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        56179                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.004059                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.965103                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                392950064                       # Number of tag accesses
system.l2c.tags.data_accesses               392950064                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker       228515                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       155195                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       232922                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       157807                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 774439                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7886218                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7886218                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     13793267                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        13793267                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data           13066                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           13135                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               26201                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           823252                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           809118                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1632370                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       6801903                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       6913178                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          13715081                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3265618                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3290649                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6556267                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       366070                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       355034                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           721104                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        228515                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        155195                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6801903                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4088870                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        232922                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        157807                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6913178                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4099767                       # number of demand (read+write) hits
system.l2c.demand_hits::total                22678157                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       228515                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       155195                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6801903                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4088870                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       232922                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       157807                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6913178                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4099767                       # number of overall hits
system.l2c.overall_hits::total               22678157                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1963                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         2098                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2348                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2153                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8562                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1921                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          1961                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              3882                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         265574                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         256839                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             522413                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        39780                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        40497                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           80277                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       142104                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       140113                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         282217                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       259774                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       251825                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         511599                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1963                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2098                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             39780                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            407678                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2348                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2153                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             40497                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            396952                       # number of demand (read+write) misses
system.l2c.demand_misses::total                893469                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1963                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2098                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            39780                       # number of overall misses
system.l2c.overall_misses::cpu0.data           407678                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2348                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2153                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            40497                       # number of overall misses
system.l2c.overall_misses::cpu1.data           396952                       # number of overall misses
system.l2c.overall_misses::total               893469                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    171313500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    185909000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    205293000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    189294000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      751809500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data     32649000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data     35540500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     68189500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        82000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       162500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  21807133500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  20994818000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  42801951500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3285719000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3349644500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   6635363500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  12013468000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11840561500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  23854029500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data        57000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data       397500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total       454500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    171313500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    185909000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3285719000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  33820601500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    205293000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    189294000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3349644500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  32835379500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     74043154000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    171313500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    185909000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3285719000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  33820601500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    205293000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    189294000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3349644500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  32835379500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    74043154000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       230478                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       157293                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       235270                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       159960                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             783001                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7886218                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7886218                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     13793267                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     13793267                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        14987                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        15096                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           30083                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1088826                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1065957                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2154783                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6841683                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      6953675                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      13795358                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3407722                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3430762                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6838484                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       625844                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       606859                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1232703                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       230478                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       157293                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6841683                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4496548                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       235270                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       159960                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6953675                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4496719                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            23571626                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       230478                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       157293                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6841683                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4496548                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       235270                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       159960                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6953675                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4496719                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           23571626                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.010935                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.128178                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.129902                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.129043                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.243909                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.240947                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.242443                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005814                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005824                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005819                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041701                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.040840                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.041269                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.415078                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.414965                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.415022                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005814                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.090665                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005824                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.088276                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.037904                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005814                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.090665                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005824                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.088276                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.037904                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 87807.696800                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16995.835502                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18123.661397                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 17565.558990                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        82000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        81250                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82113.209501                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81743.107550                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 81931.252668                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82597.259930                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82713.398523                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82655.847877                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84539.970726                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84507.229879                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 84523.715793                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     0.219421                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.578477                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total     0.888391                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82597.259930                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 82959.103753                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82713.398523                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82718.765745                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 82871.542270                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82597.259930                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 82959.103753                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82713.398523                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82718.765745                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 82871.542270                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1124258                       # number of writebacks
system.l2c.writebacks::total                  1124258                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1963                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2098                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2348                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2153                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8562                       # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data         1921                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data         1961                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         3882                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       265574                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       256839                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        522413                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        39780                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        40497                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        80277                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       142104                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       140113                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       282217                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       259774                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       251825                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       511599                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1963                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         2098                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        39780                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       407678                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2348                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2153                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        40497                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       396952                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           893469                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1963                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         2098                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        39780                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       407678                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2348                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2153                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        40497                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       396952                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          893469                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16630                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17075                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76830                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15387                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18323                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32017                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35398                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110540                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    666189500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     36648500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     37294000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     73942500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        72000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       142500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  19151393500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18426428000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  37577821500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   2887919000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2944674500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   5832593500                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10592406543                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10439412039                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  21031818582                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   4849839500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   4701857000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total   9551696500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2887919000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  29743800043                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2944674500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  28865840039                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  65108423082                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2887919000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  29743800043                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2944674500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  28865840039                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  65108423082                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2895695500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2915001000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8535114000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2895695500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2915001000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8535114000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.010935                       # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.128178                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.129902                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.129043                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.243909                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240947                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.242443                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005819                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041701                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040840                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041269                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.415078                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.414965                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.415022                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.037904                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.037904                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77807.696800                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19077.824050                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19017.848037                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19047.527048                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        72000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72113.209501                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71743.107550                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 71931.252668                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72655.847877                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74539.819731                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74507.090984                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74523.570805                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18669.456913                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18671.128760                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.279848                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174124.804570                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170717.481698                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111090.901991                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 90442.436830                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 82349.313521                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 77212.900308                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       2952008                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1460758                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3777                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76830                       # Transaction distribution
system.membus.trans_dist::ReadResp             456752                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1230888                       # Transaction distribution
system.membus.trans_dist::CleanEvict           196616                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4451                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            521854                       # Transaction distribution
system.membus.trans_dist::ReadExResp           521854                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        379922                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        618256                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6940                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3704616                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3834318                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       236933                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       236933                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4071251                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13880                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    129250016                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    129419862                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7203584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7203584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               136623446                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3602                       # Total snoops (count)
system.membus.snoopTraffic                     230016                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1635025                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019925                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.139743                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1602447     98.01%     98.01% # Request fanout histogram
system.membus.snoop_fanout::1                   32578      1.99%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1635025                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106891500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5673000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8054295189                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4944826036                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44675477                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     48651794                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     24630474                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1743                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2027                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2027                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq            1286860                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          21921577                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9010476                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     13794841                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2528106                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           30086                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          30088                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2154783                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2154783                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      13795358                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6841623                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1261461                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1232703                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41471807                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30873248                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       776442                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1216589                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              74338086                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1765945236                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1080533506                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2538024                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3725984                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2852742750                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1772959                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  75424744                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         26717035                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021855                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.146208                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               26133147     97.81%     97.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 583888      2.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           26717035                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        46394041000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1620386                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       20736162000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14171869470                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         459189000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         750841000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------