path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.820975                       # Number of seconds simulated
sim_ticks                                51820974875500                       # Number of ticks simulated
final_tick                               51820974875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 496355                       # Simulator instruction rate (inst/s)
host_op_rate                                   583273                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            28752228320                       # Simulator tick rate (ticks/s)
host_mem_usage                                 675168                       # Number of bytes of host memory used
host_seconds                                  1802.33                       # Real time elapsed on the host
sim_insts                                   894595581                       # Number of instructions simulated
sim_ops                                    1051249500                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       122624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       122112                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2604528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         25895856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       149760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       136256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2570820                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         25432280                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        409472                       # Number of bytes read from this memory
system.physmem.bytes_read::total             57443708                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2604528                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2570820                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5175348                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     78747648                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          78768228                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1916                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1908                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             64977                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            404626                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2340                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         2129                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             56295                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            397389                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6398                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                937978                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1230432                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1233005                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               50260                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              499718                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2890                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2629                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               49610                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              490772                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7902                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1108503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          50260                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          49610                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              99870                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1519610                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1520007                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1519610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2356                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              50260                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             499718                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2890                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2629                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              49610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             491169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7902                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2628510                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        937978                       # Number of read requests accepted
system.physmem.writeReqs                      1233005                       # Number of write requests accepted
system.physmem.readBursts                      937978                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1233005                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 59999232                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     31360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  78767552                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  57443708                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               78768228                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      490                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2262                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               55925                       # Per bank write bursts
system.physmem.perBankRdBursts::1               62794                       # Per bank write bursts
system.physmem.perBankRdBursts::2               56907                       # Per bank write bursts
system.physmem.perBankRdBursts::3               56516                       # Per bank write bursts
system.physmem.perBankRdBursts::4               54249                       # Per bank write bursts
system.physmem.perBankRdBursts::5               59650                       # Per bank write bursts
system.physmem.perBankRdBursts::6               52080                       # Per bank write bursts
system.physmem.perBankRdBursts::7               52710                       # Per bank write bursts
system.physmem.perBankRdBursts::8               54230                       # Per bank write bursts
system.physmem.perBankRdBursts::9              101225                       # Per bank write bursts
system.physmem.perBankRdBursts::10              56377                       # Per bank write bursts
system.physmem.perBankRdBursts::11              58912                       # Per bank write bursts
system.physmem.perBankRdBursts::12              52835                       # Per bank write bursts
system.physmem.perBankRdBursts::13              56393                       # Per bank write bursts
system.physmem.perBankRdBursts::14              52915                       # Per bank write bursts
system.physmem.perBankRdBursts::15              53770                       # Per bank write bursts
system.physmem.perBankWrBursts::0               75516                       # Per bank write bursts
system.physmem.perBankWrBursts::1               81375                       # Per bank write bursts
system.physmem.perBankWrBursts::2               78514                       # Per bank write bursts
system.physmem.perBankWrBursts::3               79379                       # Per bank write bursts
system.physmem.perBankWrBursts::4               75747                       # Per bank write bursts
system.physmem.perBankWrBursts::5               80437                       # Per bank write bursts
system.physmem.perBankWrBursts::6               73343                       # Per bank write bursts
system.physmem.perBankWrBursts::7               74340                       # Per bank write bursts
system.physmem.perBankWrBursts::8               74711                       # Per bank write bursts
system.physmem.perBankWrBursts::9               79754                       # Per bank write bursts
system.physmem.perBankWrBursts::10              76052                       # Per bank write bursts
system.physmem.perBankWrBursts::11              78875                       # Per bank write bursts
system.physmem.perBankWrBursts::12              73771                       # Per bank write bursts
system.physmem.perBankWrBursts::13              78567                       # Per bank write bursts
system.physmem.perBankWrBursts::14              74862                       # Per bank write bursts
system.physmem.perBankWrBursts::15              75500                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          33                       # Number of times write queue was full causing retry
system.physmem.totGap                    51820971954500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  894862                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1230432                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    903465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     28234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1195                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      410                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      171                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      178                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      122                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      117                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       97                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       92                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       51                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1516                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1445                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1435                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1393                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    33891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    39270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    66568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    69647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    73027                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    70654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    69180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    71444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    74057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    71008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    76504                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    74752                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    70724                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    69059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    69030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    66768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    66112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    65180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1211                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      885                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      262                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      232                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      168                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      162                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                      127                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       564009                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      246.035904                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     148.070971                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     287.068931                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         250512     44.42%     44.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       146974     26.06%     70.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        49960      8.86%     79.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27236      4.83%     84.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18139      3.22%     87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12170      2.16%     89.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8948      1.59%     91.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7660      1.36%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        42410      7.52%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         564009                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         65824                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.242267                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      106.817618                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          65819     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           65824                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         65824                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.697481                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.054439                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.954009                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3               139      0.21%      0.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                76      0.12%      0.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11               52      0.08%      0.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15             125      0.19%      0.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           51932     78.90%     79.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9755     14.82%     94.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27            1068      1.62%     95.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             579      0.88%     96.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             868      1.32%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             349      0.53%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              83      0.13%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              31      0.05%     98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              49      0.07%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              50      0.08%     98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              24      0.04%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              26      0.04%     99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             422      0.64%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              35      0.05%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              36      0.05%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              31      0.05%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              19      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               4      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               5      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.00%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            16      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            12      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             6      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             4      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           65824                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12248455604                       # Total ticks spent queuing
system.physmem.totMemAccLat               29826355604                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4687440000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13065.19                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31815.19                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.53                       # Average write queue length when enqueuing
system.physmem.readRowHits                     705562                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    898659                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.26                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.02                       # Row buffer hit rate for writes
system.physmem.avgGap                     23869819.32                       # Average gap between requests
system.physmem.pageHitRate                      73.99                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 2151787680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 1174090500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                3516442800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               4008858480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3384694126320                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1301405336775                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29951001041250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34647951683805                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.608648                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49825590774964                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1730416220000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    264967468786                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 2112120360                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1152446625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                3795924600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3966356160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3384694126320                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1300719308715                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29951602820250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34648043103030                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.610412                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49826557272121                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1730416220000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    264000971629                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   134174                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               134174                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20899                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        96911                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore           13                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       134161                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         134161    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       134161                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       117823                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       116916     99.23%     99.23% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071          782      0.66%     99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607           48      0.04%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679           26      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215            7      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       117823                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples   4912294556                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     1.048082                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0     -236192296     -4.81%     -4.81% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1     5148486852    104.81%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total   4912294556                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        96912     82.26%     82.26% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        20899     17.74%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       117811                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       134174                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       134174                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       117811                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       117811                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       251985                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    83610055                       # DTB read hits
system.cpu0.dtb.read_misses                    101997                       # DTB read misses
system.cpu0.dtb.write_hits                   76232981                       # DTB write hits
system.cpu0.dtb.write_misses                    32177                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              22117                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    537                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   74001                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4744                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10268                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                83712052                       # DTB read accesses
system.cpu0.dtb.write_accesses               76265158                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        159843036                       # DTB hits
system.cpu0.dtb.misses                         134174                       # DTB misses
system.cpu0.dtb.accesses                    159977210                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    79618                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                79618                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4423                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69406                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples        79618                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          79618    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        79618                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        73829                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-32767        36310     49.18%     49.18% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-65535        36530     49.48%     98.66% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-98303          322      0.44%     99.10% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::98304-131071          541      0.73%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::163840-196607           50      0.07%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-229375           12      0.02%     99.93% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::229376-262143           20      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-294911           14      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-491519            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        73829                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0     -294749296    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total   -294749296                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        69406     94.01%     94.01% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         4423      5.99%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        73829                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        79618                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        79618                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        73829                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        73829                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       153447                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   446783848                       # ITB inst hits
system.cpu0.itb.inst_misses                     79618                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51828                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              22117                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    537                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   55085                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               446863466                       # ITB inst accesses
system.cpu0.itb.hits                        446783848                       # DTB hits
system.cpu0.itb.misses                          79618                       # DTB misses
system.cpu0.itb.accesses                    446863466                       # DTB accesses
system.cpu0.numPwrStateTransitions              16584                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         8292                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    5987638231.190425                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   124545672847.091751                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3540     42.69%     42.69% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         4687     56.52%     99.22% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.23% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            5      0.06%     99.29% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.54%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 5700356716960                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           8292                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   2171478662469                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     51821531497                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16350                       # number of quiesce instructions executed
system.cpu0.committedInsts                  446506838                       # Number of instructions committed
system.cpu0.committedOps                    524620955                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            481485743                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                439185                       # Number of float alu accesses
system.cpu0.num_func_calls                   26339620                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     68267650                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   481485743                       # number of integer instructions
system.cpu0.num_fp_insts                       439185                       # number of float instructions
system.cpu0.num_int_register_reads          703915697                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         382127275                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              705229                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             378788                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           117675600                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          117367653                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    159834987                       # number of memory refs
system.cpu0.num_load_insts                   83607531                       # Number of load instructions
system.cpu0.num_store_insts                  76227456                       # Number of store instructions
system.cpu0.num_idle_cycles              50234015072.883141                       # Number of idle cycles
system.cpu0.num_busy_cycles              1587516424.116865                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.030634                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.969366                       # Percentage of idle cycles
system.cpu0.Branches                         99742938                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                363863642     69.32%     69.32% # Class of executed instruction
system.cpu0.op_class::IntMult                 1121256      0.21%     69.53% # Class of executed instruction
system.cpu0.op_class::IntDiv                    48514      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             55488      0.01%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.55% # Class of executed instruction
system.cpu0.op_class::MemRead                83607531     15.93%     85.48% # Class of executed instruction
system.cpu0.op_class::MemWrite               76227456     14.52%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 524923888                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements         10233133                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.965653                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          310246690                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs         10233645                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.316343                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3504381500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   237.355546                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   274.610106                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.463585                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.536348                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          415                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1292621561                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1292621561                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     78084246                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     78779688                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      156863934                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     72276585                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     72648252                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     144924837                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       197426                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       197729                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       395155                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       164722                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data       170823                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       335545                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1869757                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1817939                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3687696                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2017973                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1975667                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3993640                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    150525553                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    151598763                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       302124316                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    150722979                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    151796492                       # number of overall hits
system.cpu0.dcache.overall_hits::total      302519471                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2626633                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2692297                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5318930                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1125686                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1099795                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2225481                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       666350                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       645260                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1311610                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       622669                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data       609834                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total      1232503                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       148976                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       158663                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       307639                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            2                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            3                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      4374988                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      4401926                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       8776914                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      5041338                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      5047186                       # number of overall misses
system.cpu0.dcache.overall_misses::total     10088524                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41851762000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42562196000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  84413958000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  34117734500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  33482014000                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  67599748500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12812675500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12470666000                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  25283341500                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2198112500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2331851500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4529964000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       114000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        83000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       197000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  88782172000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  88514876000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 177297048000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  88782172000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  88514876000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 177297048000                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     80710879                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     81471985                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    162182864                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     73402271                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     73748047                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    147150318                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       863776                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       842989                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1706765                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       787391                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       780657                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1568048                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2018733                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1976602                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3995335                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2017975                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1975668                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3993643                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    154900541                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    156000689                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    310901230                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    155764317                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    156843678                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    312607995                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032544                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033046                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032796                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015336                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014913                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.015124                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771438                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.765443                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.768477                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.790800                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.781180                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786011                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.073797                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.080271                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077000                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028244                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028217                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.028231                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032365                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032180                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.032272                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15933.616154                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15808.878441                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15870.477333                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30308.393726                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30443.868175                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30375.342903                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20577.024872                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20449.279640                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20513.817411                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14754.809500                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14696.882701                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14724.934095                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        57000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        83000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 65666.666667                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20293.123547                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20108.215358                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20200.385694                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17610.835060                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17537.470583                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17574.131558                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      7895103                       # number of writebacks
system.cpu0.dcache.writebacks::total          7895103                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10951                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        10880                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total        21831                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9894                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11327                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21221                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        36169                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35602                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        71771                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        20845                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        22207                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        43052                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        20845                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        22207                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        43052                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2615682                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2681417                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5297099                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1115792                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1088468                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2204260                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       665476                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       644343                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1309819                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       622669                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       609834                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232503                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       112807                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       123061                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       235868                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            2                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            3                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      4354143                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      4379719                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      8733862                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      5019619                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      5024062                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total     10043681                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16676                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17030                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        14991                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18719                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        31667                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35749                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  38950730500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39600598000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78551328500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32683890500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  32050078500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  64733969000                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10672378000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10358334500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21030712500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12190006500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11860832000                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24050838500                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1508170000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1647856500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3156026500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       112000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        82000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83824627500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  83511508500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 167336136000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94497005500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93869843000                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 188366848500                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3111292000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3121623000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232915000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3111292000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3121623000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232915000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032408                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032912                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032661                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015201                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014759                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014980                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.770427                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.764355                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.767428                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.790800                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781180                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.786011                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055880                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.062259                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059036                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028109                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028075                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.028092                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032226                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032032                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.032129                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14891.233147                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14768.533951                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14829.122223                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29292.099692                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29445.127004                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29367.664885                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16037.209456                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16075.808226                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16056.197459                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19577.024872                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19449.279640                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19513.817411                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13369.471753                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13390.566467                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13380.477640                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        56000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        82000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19251.693732                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19067.777750                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19159.466454                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18825.533472                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18684.053461                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18754.762173                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186573.039098                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183301.409278                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184920.043909                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 98250.292102                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87320.568408                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92454.536015                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements         13781825                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.891071                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          881366045                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13782337                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            63.948955                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      31614405500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   231.253269                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   280.637803                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.451667                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.548121                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        908930729                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       908930729                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    439927744                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    441438301                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      881366045                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    439927744                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    441438301                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       881366045                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    439927744                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    441438301                       # number of overall hits
system.cpu0.icache.overall_hits::total      881366045                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6856104                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6926238                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13782342                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6856104                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6926238                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13782342                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6856104                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6926238                       # number of overall misses
system.cpu0.icache.overall_misses::total     13782342                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  92096826500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93000613500                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 185097440000                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  92096826500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  93000613500                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 185097440000                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  92096826500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  93000613500                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 185097440000                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    446783848                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    448364539                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    895148387                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    446783848                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    448364539                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    895148387                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    446783848                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    448364539                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    895148387                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015345                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015448                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015397                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015345                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015448                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015397                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015345                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015448                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015397                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.822270                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.291049                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13430.042586                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.822270                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13427.291049                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13430.042586                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.822270                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13427.291049                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13430.042586                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks     13781825                       # number of writebacks
system.cpu0.icache.writebacks::total         13781825                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6856104                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6926238                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13782342                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6856104                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6926238                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13782342                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6856104                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6926238                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13782342                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85240722500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86074375500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 171315098000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85240722500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86074375500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 171315098000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85240722500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86074375500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 171315098000                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3263480000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   3263480000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015397                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015397                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015345                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015448                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015397                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551                       # average overall mshr uncacheable latency
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   131388                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               131388                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20694                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        94767                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore           12                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       131376                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean     0.304470                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev    84.045560                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-2047       131374    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       131376                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       115473                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       114392     99.06%     99.06% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071          917      0.79%     99.86% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607           63      0.05%     99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143           52      0.05%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           33      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           11      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       115473                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   5991401436                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     1.130704                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -783101296    -13.07%    -13.07% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1     6774502732    113.07%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   5991401436                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        94767     82.08%     82.08% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        20694     17.92%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       115461                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       131388                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       131388                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       115461                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       115461                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       246849                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    84308595                       # DTB read hits
system.cpu1.dtb.read_misses                    100203                       # DTB read misses
system.cpu1.dtb.write_hits                   76530288                       # DTB write hits
system.cpu1.dtb.write_misses                    31185                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              20910                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    530                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   73106                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4660                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9685                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                84408798                       # DTB read accesses
system.cpu1.dtb.write_accesses               76561473                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        160838883                       # DTB hits
system.cpu1.dtb.misses                         131388                       # DTB misses
system.cpu1.dtb.accesses                    160970271                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    76510                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                76510                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4384                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        66713                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples        76510                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          76510    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        76510                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71097                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        69890     98.30%     98.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071         1057      1.49%     99.79% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607           63      0.09%     99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           56      0.08%     99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           18      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215            4      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            6      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71097                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -850152296    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -850152296                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        66713     93.83%     93.83% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         4384      6.17%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        71097                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        76510                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        76510                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        71097                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        71097                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       147607                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   448364539                       # ITB inst hits
system.cpu1.itb.inst_misses                     76510                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51822                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              20910                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    530                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   52840                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               448441049                       # ITB inst accesses
system.cpu1.itb.hits                        448364539                       # DTB hits
system.cpu1.itb.misses                          76510                       # DTB misses
system.cpu1.itb.accesses                    448441049                       # DTB accesses
system.cpu1.numPwrStateTransitions              16068                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         8034                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    6192978089.022779                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   118311828609.490631                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3509     43.68%     43.68% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         4459     55.50%     99.18% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.23% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           13      0.16%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 3977581604528                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           8034                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   2066588908291                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     51820418254                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu1.committedInsts                  448088743                       # Number of instructions committed
system.cpu1.committedOps                    526628545                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            483582453                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                455004                       # Number of float alu accesses
system.cpu1.num_func_calls                   26546962                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     68480445                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   483582453                       # number of integer instructions
system.cpu1.num_fp_insts                       455004                       # number of float instructions
system.cpu1.num_int_register_reads          705060671                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         383633333                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              735821                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             380160                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           117946404                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          117660346                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    160831979                       # number of memory refs
system.cpu1.num_load_insts                   84305574                       # Number of load instructions
system.cpu1.num_store_insts                  76526405                       # Number of store instructions
system.cpu1.num_idle_cycles              50231588268.978668                       # Number of idle cycles
system.cpu1.num_busy_cycles              1588829985.021333                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.030660                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.969340                       # Percentage of idle cycles
system.cpu1.Branches                        100054364                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                364882138     69.25%     69.25% # Class of executed instruction
system.cpu1.op_class::IntMult                 1103160      0.21%     69.46% # Class of executed instruction
system.cpu1.op_class::IntDiv                    49288      0.01%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.47% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             54935      0.01%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.48% # Class of executed instruction
system.cpu1.op_class::MemRead                84305574     16.00%     85.48% # Class of executed instruction
system.cpu1.op_class::MemWrite               76526405     14.52%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 526921542                       # Class of executed instruction
system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40309                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40309                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230976                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230976                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353760                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334336                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334336                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42146500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               323500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25738000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38603500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           568948940                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147736000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115469                       # number of replacements
system.iocache.tags.tagsinuse               10.457310                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115485                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13153887286000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.511180                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946130                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219449                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434133                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653582                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039749                       # Number of tag accesses
system.iocache.tags.data_accesses             1039749                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8824                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8861                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115488                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115528                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115488                       # number of overall misses
system.iocache.overall_misses::total           115528                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1592669163                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1597755163                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  12771081777                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  12771081777                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14363750940                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14369187940                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14363750940                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14369187940                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8824                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8861                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115488                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115528                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115488                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115528                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 180492.878853                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 180313.188466                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119731.884956                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 119731.884956                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124374.402016                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124378.401253                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       135925                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124374.402016                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124378.401253                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         30368                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3349                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.067781                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8824                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8861                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115488                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115528                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115488                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115528                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1151469163                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1154705163                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7431123166                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7431123166                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   8582592329                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8586029329                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   8582592329                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8586029329                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130492.878853                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 130313.188466                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69668.521394                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69668.521394                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74315.879823                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74319.899323                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85925                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74315.879823                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74319.899323                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1307989                       # number of replacements
system.l2c.tags.tagsinuse                65252.064264                       # Cycle average of tags in use
system.l2c.tags.total_refs                   44034643                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1371175                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    32.114532                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               6646395500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38392.380157                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   144.452542                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   212.975590                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3457.790228                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9508.612364                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   156.104056                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   224.227466                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2866.176081                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    10289.345780                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.585821                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002204                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003250                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.052762                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.145090                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002382                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003421                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.043734                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.157003                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.995667                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          258                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62928                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          257                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          416                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2434                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5412                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        54630                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003937                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.960205                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                395596143                       # Number of tag accesses
system.l2c.tags.data_accesses               395596143                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.l2c.ReadReq_hits::cpu0.dtb.walker       248480                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       169318                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       245899                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       163828                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                 827525                       # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks      7895103                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         7895103                       # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks     13780242                       # number of WritebackClean hits
system.l2c.WritebackClean_hits::total        13780242                       # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data            5072                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4937                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total               10009                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           827908                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           804935                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1632843                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst       6817014                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst       6887144                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total          13704158                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data      3253717                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data      3311406                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          6565123                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       363022                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       359819                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           722841                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker        248480                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        169318                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6817014                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             4081625                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        245899                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        163828                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6887144                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             4116341                       # number of demand (read+write) hits
system.l2c.demand_hits::total                22729649                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       248480                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       169318                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6817014                       # number of overall hits
system.l2c.overall_hits::cpu0.data            4081625                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       245899                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       163828                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6887144                       # number of overall hits
system.l2c.overall_hits::cpu1.data            4116341                       # number of overall hits
system.l2c.overall_hits::total               22729649                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1916                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1908                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         2340                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         2129                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 8293                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17934                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         17937                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             35871                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            2                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         264878                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         260659                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             525537                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst        39090                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst        39094                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           78184                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       140248                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       137415                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         277663                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       259647                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       250015                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         509662                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1916                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1908                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             39090                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            405126                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2340                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         2129                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             39094                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            398074                       # number of demand (read+write) misses
system.l2c.demand_misses::total                889677                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1916                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1908                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            39090                       # number of overall misses
system.l2c.overall_misses::cpu0.data           405126                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2340                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         2129                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            39094                       # number of overall misses
system.l2c.overall_misses::cpu1.data           398074                       # number of overall misses
system.l2c.overall_misses::total               889677                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    166477000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    168816000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    202614000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    184858000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      722765000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    256947000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    262070500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    519017500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data       109000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       189500                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  21720472000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  21369705500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  43090177500                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3240963000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3232439000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total   6473402000                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  11837513000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  11624046500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total  23461559500                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data        57000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data       392500                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total       449500                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    166477000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    168816000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   3240963000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  33557985000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    202614000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    184858000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   3232439000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  32993752000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     73747904000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    166477000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    168816000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   3240963000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  33557985000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    202614000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    184858000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   3232439000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  32993752000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    73747904000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       250396                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       171226                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       248239                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       165957                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             835818                       # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks      7895103                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      7895103                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks     13780242                       # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total     13780242                       # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        23006                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        22874                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           45880                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data      1092786                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1065594                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2158380                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst      6856104                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst      6926238                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total      13782342                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data      3393965                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data      3448821                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      6842786                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       622669                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       609834                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total      1232503                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       250396                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       171226                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6856104                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4486751                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       248239                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       165957                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6926238                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4514415                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            23619326                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       250396                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       171226                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6856104                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4486751                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       248239                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       165957                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6926238                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4514415                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           23619326                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.009922                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.779536                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784165                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.781844                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.242388                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.244614                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.243487                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005701                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005644                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.005673                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041323                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.039844                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.040577                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.416990                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.409972                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.413518                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005701                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.090294                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005644                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.088178                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.037667                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007652                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.011143                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005701                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.090294                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.009426                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.012829                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005644                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.088178                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.037667                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86887.787056                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88477.987421                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86587.179487                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 87153.623538                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14327.367012                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14610.609355                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14469.000028                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        54500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 63166.666667                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82001.797054                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81983.378667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 81992.661792                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82910.283960                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82683.762214                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 82797.017293                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84404.148366                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84590.812502                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 84496.528165                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     0.219529                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.569906                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total     0.881957                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86887.787056                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88477.987421                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 82910.283960                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 82833.451815                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86587.179487                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 82683.762214                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 82883.463879                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 82892.897085                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86887.787056                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88477.987421                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 82910.283960                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 82833.451815                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86587.179487                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86828.558008                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 82683.762214                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 82883.463879                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 82892.897085                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1123802                       # number of writebacks
system.l2c.writebacks::total                  1123802                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1916                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1908                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2340                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2129                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            8293                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17934                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        17937                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        35871                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            2                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       264878                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       260659                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        525537                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        39090                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        39094                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        78184                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       140248                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       137415                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total       277663                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       259647                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       250015                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       509662                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1916                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1908                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        39090                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       405126                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2340                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         2129                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        39094                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       398074                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           889677                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1916                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1908                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        39090                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       405126                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2340                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         2129                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        39094                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       398074                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          889677                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16676                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17030                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        14991                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18719                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        31667                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35749                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    147317000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    149736000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    179214000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    163568000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    639835000                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    339250000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    339359000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    678609000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        89000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        70500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       159500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  19071692000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18763115500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  37834807500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   2850063000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2841499000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total   5691562000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10435011543                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10249884524                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total  20684896067                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   4847797000                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   4667831500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total   9515628500                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    147317000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    149736000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2850063000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  29506703543                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    179214000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    163568000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2841499000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  29013000024                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  64851100567                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    147317000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    149736000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2850063000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  29506703543                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    179214000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    163568000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2841499000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  29013000024                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  64851100567                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2902459000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2908357500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   8535234000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2902459000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2908357500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   8535234000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007652                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.011143                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.009426                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.012829                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.009922                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.779536                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784165                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.781844                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.242388                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.244614                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.243487                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005701                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005673                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041323                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.039844                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.040577                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.416990                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.409972                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.413518                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007652                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.011143                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005701                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.090294                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009426                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.012829                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.088178                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.037667                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007652                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.011143                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005701                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.090294                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009426                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.012829                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005644                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.088178                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.037667                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        44500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70500                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 72892.859506                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 72892.859506                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       2973114                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1487263                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3311                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
system.membus.trans_dist::ReadResp             449832                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1230432                       # Transaction distribution
system.membus.trans_dist::CleanEvict           191908                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            36440                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            524978                       # Transaction distribution
system.membus.trans_dist::ReadExResp           524978                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        373001                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        616319                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3721926                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3851630                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237395                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237395                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4089025                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    128978144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    129147994                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7233792                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7233792                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               136381786                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3125                       # Total snoops (count)
system.membus.snoopTraffic                     199488                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1661282                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.019128                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.136975                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1629505     98.09%     98.09% # Request fanout histogram
system.membus.snoop_fanout::1                   31777      1.91%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1661282                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106916500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5690500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          8079257005                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4924178426                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44658046                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     48659442                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests     24643437                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests         1748                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           2028                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         2028                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq            1290012                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          21916025                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      9018905                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean     13781825                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2522217                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           45883                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             3                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          45886                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2158380                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2158380                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq      13782342                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      6845459                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq      1260926                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp      1232503                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41432759                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30927957                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       796484                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1252515                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              74409715                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1764279188                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1081608326                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2697464                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3989080                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             2852574058                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1717339                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  74998872                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         26724704                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.021941                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.146492                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0               26138332     97.81%     97.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 586372      2.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           26724704                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        46394070000                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          1633889                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       20716638000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       14191518968                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         459301000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         753880000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------