path: root/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.781932                       # Number of seconds simulated
sim_ticks                                51781931516000                       # Number of ticks simulated
final_tick                               51781931516000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 513884                       # Simulator instruction rate (inst/s)
host_op_rate                                   603881                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            31103019215                       # Simulator tick rate (ticks/s)
host_mem_usage                                 672564                       # Number of bytes of host memory used
host_seconds                                  1664.85                       # Real time elapsed on the host
sim_insts                                   855540358                       # Number of instructions simulated
sim_ops                                    1005371984                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker       107200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       102528                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          2434152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         20994800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker        96832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       103680                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          2545804                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         20458904                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        379200                       # Number of bytes read from this memory
system.physmem.bytes_read::total             47223100                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      2434152                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      2545804                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         4979956                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     68447104                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
system.physmem.bytes_written::total          68467684                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         1675                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         1602                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             65448                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            328047                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         1513                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1620                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             52771                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            319680                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           5925                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                778281                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1069486                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1072059                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          2070                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          1980                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               47008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              405446                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          1870                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2002                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               49164                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              395097                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7323                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  911961                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          47008                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          49164                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              96172                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1321834                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1322231                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1321834                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         2070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         1980                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              47008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             405447                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         1870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2002                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              49164                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             395495                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7323                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2234192                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        778281                       # Number of read requests accepted
system.physmem.writeReqs                      1672780                       # Number of write requests accepted
system.physmem.readBursts                      778281                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1672780                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 49778368                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     31616                       # Total number of bytes read from write queue
system.physmem.bytesWritten                 106609920                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  47223100                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys              106913828                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      494                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    6998                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          34417                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               49121                       # Per bank write bursts
system.physmem.perBankRdBursts::1               48968                       # Per bank write bursts
system.physmem.perBankRdBursts::2               43998                       # Per bank write bursts
system.physmem.perBankRdBursts::3               44044                       # Per bank write bursts
system.physmem.perBankRdBursts::4               46923                       # Per bank write bursts
system.physmem.perBankRdBursts::5               50978                       # Per bank write bursts
system.physmem.perBankRdBursts::6               43709                       # Per bank write bursts
system.physmem.perBankRdBursts::7               43367                       # Per bank write bursts
system.physmem.perBankRdBursts::8               43043                       # Per bank write bursts
system.physmem.perBankRdBursts::9               89491                       # Per bank write bursts
system.physmem.perBankRdBursts::10              47224                       # Per bank write bursts
system.physmem.perBankRdBursts::11              49584                       # Per bank write bursts
system.physmem.perBankRdBursts::12              42821                       # Per bank write bursts
system.physmem.perBankRdBursts::13              45810                       # Per bank write bursts
system.physmem.perBankRdBursts::14              42383                       # Per bank write bursts
system.physmem.perBankRdBursts::15              46323                       # Per bank write bursts
system.physmem.perBankWrBursts::0              104557                       # Per bank write bursts
system.physmem.perBankWrBursts::1              105414                       # Per bank write bursts
system.physmem.perBankWrBursts::2              105583                       # Per bank write bursts
system.physmem.perBankWrBursts::3              103819                       # Per bank write bursts
system.physmem.perBankWrBursts::4              104348                       # Per bank write bursts
system.physmem.perBankWrBursts::5              108141                       # Per bank write bursts
system.physmem.perBankWrBursts::6              101114                       # Per bank write bursts
system.physmem.perBankWrBursts::7              100245                       # Per bank write bursts
system.physmem.perBankWrBursts::8               99850                       # Per bank write bursts
system.physmem.perBankWrBursts::9              106510                       # Per bank write bursts
system.physmem.perBankWrBursts::10             102540                       # Per bank write bursts
system.physmem.perBankWrBursts::11             107777                       # Per bank write bursts
system.physmem.perBankWrBursts::12             103459                       # Per bank write bursts
system.physmem.perBankWrBursts::13             105336                       # Per bank write bursts
system.physmem.perBankWrBursts::14             101779                       # Per bank write bursts
system.physmem.perBankWrBursts::15             105308                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    51781928959500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  735165                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1670207                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    745946                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     26414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1937                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       535                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       685                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       390                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       348                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       274                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       204                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      132                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                       96                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                       89                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                       77                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       78                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      1607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      1535                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      1509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      1486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      1469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      1453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      1436                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      1422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      1410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      1402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     1388                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     1379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     1371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     1359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     1353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    55685                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    67964                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    89945                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    92025                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    95463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                   110001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                   113998                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    99922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                   100596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    98621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    96222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    93100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    89862                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    88090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    83497                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    82653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    82465                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    81037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     3282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2928                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      420                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      392                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      274                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      251                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       29                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       531423                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.281520                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     167.194093                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.137010                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         219913     41.38%     41.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       131435     24.73%     66.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        44338      8.34%     74.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23886      4.49%     78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15966      3.00%     81.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        10709      2.02%     83.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7995      1.50%     85.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         7287      1.37%     86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        69894     13.15%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         531423                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         80476                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean         9.664621                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       89.984802                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          80471     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::18432-19455            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           80476                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         80476                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.699090                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       19.496721                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       11.527834                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7               200      0.25%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15              177      0.22%      0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23           72247     89.77%     90.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31            4200      5.22%     95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39            1327      1.65%     97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47             446      0.55%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55             582      0.72%     98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63             137      0.17%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71             223      0.28%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79             119      0.15%     98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87             159      0.20%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95              60      0.07%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103            172      0.21%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111            43      0.05%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119            70      0.09%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127            53      0.07%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135           161      0.20%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143            11      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151            23      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159             5      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167            15      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175             5      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183            11      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191             5      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199             4      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215             3      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231             4      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239             3      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           80476                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9983720499                       # Total ticks spent queuing
system.physmem.totMemAccLat               24567226749                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   3888935000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12836.06                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31586.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.96                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.06                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.91                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.06                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        10.17                       # Average write queue length when enqueuing
system.physmem.readRowHits                     580589                       # Number of row buffer hits during reads
system.physmem.writeRowHits                   1331554                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  79.94                       # Row buffer hit rate for writes
system.physmem.avgGap                     21126332.21                       # Average gap between requests
system.physmem.pageHitRate                      78.25                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     49696712332000                       # Time in different power states
system.physmem.memoryStateTime::REF      1729112320000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      356106481500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                2031447600                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                1986110280                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                1108428750                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                1083691125                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               2894642400                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               3172057200                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0              5399272080                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1              5394982320                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          3382143697920                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          3382143697920                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          1286313063165                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          1285469654400                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          29940811051500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          29941550883750                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            34620701603415                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            34620801076995                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.586590                       # Core power per rank (mW)
system.physmem.averagePower::1             668.588511                       # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    80391901                       # DTB read hits
system.cpu0.dtb.read_misses                     93388                       # DTB read misses
system.cpu0.dtb.write_hits                   73043030                       # DTB write hits
system.cpu0.dtb.write_misses                    28813                       # DTB write misses
system.cpu0.dtb.flush_tlb                       51784                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   70641                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  4105                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                     9619                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                80485289                       # DTB read accesses
system.cpu0.dtb.write_accesses               73071843                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        153434931                       # DTB hits
system.cpu0.dtb.misses                         122201                       # DTB misses
system.cpu0.dtb.accesses                    153557132                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.inst_hits                   427471663                       # ITB inst hits
system.cpu0.itb.inst_misses                     76376                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                       51784                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              20238                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                    514                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   52019                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               427548039                       # ITB inst accesses
system.cpu0.itb.hits                        427471663                       # DTB hits
system.cpu0.itb.misses                          76376                       # DTB misses
system.cpu0.itb.accesses                    427548039                       # DTB accesses
system.cpu0.numCycles                     51782412762                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                  427217866                       # Number of instructions committed
system.cpu0.committedOps                    502133426                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            461356318                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                442453                       # Number of float alu accesses
system.cpu0.num_func_calls                   25480565                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     64997329                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   461356318                       # number of integer instructions
system.cpu0.num_fp_insts                       442453                       # number of float instructions
system.cpu0.num_int_register_reads          669433821                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         365789159                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              711452                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             379824                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           111391626                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          111077654                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    153423964                       # number of memory refs
system.cpu0.num_load_insts                   80387324                       # Number of load instructions
system.cpu0.num_store_insts                  73036640                       # Number of store instructions
system.cpu0.num_idle_cycles              50249111943.842865                       # Number of idle cycles
system.cpu0.num_busy_cycles              1533300818.157139                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.029610                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.970390                       # Percentage of idle cycles
system.cpu0.Branches                         95379703                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                347836061     69.23%     69.23% # Class of executed instruction
system.cpu0.op_class::IntMult                 1052847      0.21%     69.44% # Class of executed instruction
system.cpu0.op_class::IntDiv                    47944      0.01%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  6      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  5      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  9      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.45% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc             55653      0.01%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.46% # Class of executed instruction
system.cpu0.op_class::MemRead                80387324     16.00%     85.46% # Class of executed instruction
system.cpu0.op_class::MemWrite               73036640     14.54%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 502416489                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   16160                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements          9666641                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.969685                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          297154926                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          9667153                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            30.738618                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       3092948250                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   283.466253                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data   228.503431                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.553645                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.446296                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999941                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses       1237347722                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses      1237347722                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     75260834                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data     75246301                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total      150507135                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     69349664                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data     69346777                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total     138696441                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       190562                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data       191577                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       382139                       # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data       171619                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data       160816                       # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total       332435                       # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1711920                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1739353                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      3451273                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1857030                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1885244                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      3742274                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    144610498                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data    144593078                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       289203576                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    144801060                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data    144784655                       # number of overall hits
system.cpu0.dcache.overall_hits::total      289585715                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      2479823                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data      2539735                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      5019558                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1027548                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data      1051512                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      2079060                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       586953                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data       604316                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total      1191269                       # number of SoftPFReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data       612872                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data       613029                       # number of WriteInvalidateReq misses
system.cpu0.dcache.WriteInvalidateReq_misses::total      1225901                       # number of WriteInvalidateReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       145963                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       146688                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       292651                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      3507371                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data      3591247                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       7098618                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      4094324                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data      4195563                       # number of overall misses
system.cpu0.dcache.overall_misses::total      8289887                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38409075253                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  39279047002                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total  77688122255                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  27659575882                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  27687644531                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  55347220413                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data  13571753508                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data  13540403000                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.WriteInvalidateReq_miss_latency::total  27112156508                       # number of WriteInvalidateReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2071723750                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2095160250                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4166884000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        75000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total        75000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data  66068651135                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data  66966691533                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 133035342668                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data  66068651135                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data  66966691533                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 133035342668                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     77740657                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data     77786036                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total    155526693                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     70377212                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data     70398289                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total    140775501                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       777515                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       795893                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total      1573408                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data       784491                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data       773845                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total      1558336                       # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1857883                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1886041                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      3743924                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1857031                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1885244                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      3742275                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    148117869                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data    148184325                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    296302194                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    148895384                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data    148980218                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    297875602                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.031899                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.032650                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.032275                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014601                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014937                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.014769                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.754909                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.759293                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.757127                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data     0.781235                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data     0.792186                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total     0.786673                       # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.078564                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.077776                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.078167                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.023680                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.024235                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.023957                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027498                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028162                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.027830                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15488.635783                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15465.805291                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15477.084288                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26918.037777                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26331.268241                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 26621.271350                       # average WriteReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 22144.515507                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 22087.703844                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 22116.106038                       # average WriteInvalidateReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14193.485678                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14283.105980                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14238.406840                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        75000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        75000                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18837.086563                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18647.197348                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18741.020107                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16136.644568                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15961.312351                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 16047.907851                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks      7479557                       # number of writebacks
system.cpu0.dcache.writebacks::total          7479557                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data         3745                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2865                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total         6610                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data        10175                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11006                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total        21181                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        34675                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35236                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total        69911                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data        13920                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data        13871                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total        27791                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data        13920                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data        13871                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total        27791                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2476078                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2536870                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      5012948                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1017373                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1040506                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      2057879                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       586808                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       604126                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total      1190934                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data       612872                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data       613029                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total      1225901                       # number of WriteInvalidateReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       111288                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       111452                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       222740                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      3493451                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data      3577376                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      7070827                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      4080259                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data      4181502                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      8261761                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  33166863497                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  33981034998                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  67147898495                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  25195325118                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  25212990469                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  50408315587                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data   8922621248                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   8744886500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  17667507748                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data  12346009492                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data  12314345000                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total  24660354492                       # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1340334000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1349733250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   2690067250                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        73000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        73000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  58362188615                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  59194025467                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 117556214082                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  67284809863                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  67938911967                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 135223721830                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   2674522248                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3054322749                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   5728844997                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2557892750                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   3016153500                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   5574046250                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   5232414998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   6070476249                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11302891247                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.031850                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032613                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032232                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014456                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014780                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014618                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.754722                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.759054                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.756914                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.781235                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.792186                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total     0.786673                       # mshr miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059900                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.059093                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059494                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.023586                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.024141                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.023864                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027404                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028067                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.027736                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13394.918697                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13394.866508                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13394.892286                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24765.081360                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24231.470524                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24495.276732                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15205.350384                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14475.269232                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14835.001560                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20144.515481                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20087.703844                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20116.106025                       # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12043.832219                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12110.444407                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12077.162836                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        73000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        73000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16706.170665                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16546.772122                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16625.525428                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16490.328154                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16247.490009                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16367.421162                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements         13477112                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.892486                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          842591946                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs         13477624                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            62.517840                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      32076200250                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.322157                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst   270.570329                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471332                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.528458                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999790                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          197                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        869547204                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       869547204                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst    420727456                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst    421864490                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      842591946                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    420727456                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst    421864490                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       842591946                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    420727456                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst    421864490                       # number of overall hits
system.cpu0.icache.overall_hits::total      842591946                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6744207                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst      6733422                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total     13477629                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6744207                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst      6733422                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total      13477629                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6744207                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst      6733422                       # number of overall misses
system.cpu0.icache.overall_misses::total     13477629                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  90268756253                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  90304288753                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 180573045006                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  90268756253                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst  90304288753                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 180573045006                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  90268756253                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst  90304288753                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 180573045006                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    427471663                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst    428597912                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    856069575                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    427471663                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst    428597912                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    856069575                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    427471663                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst    428597912                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    856069575                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015777                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015710                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.015744                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015777                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015710                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.015744                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015777                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015710                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.015744                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13384.636067                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13411.351428                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13397.983058                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13397.983058                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13384.636067                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13411.351428                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13397.983058                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6744207                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6733422                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total     13477629                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6744207                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst      6733422                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total     13477629                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6744207                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst      6733422                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total     13477629                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  76767439747                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  76823488247                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 153590927994                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  76767439747                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  76823488247                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 153590927994                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  76767439747                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  76823488247                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 153590927994                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2831704500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1919614500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    912090000                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2831704500                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015744                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.015744                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015777                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015710                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.015744                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11395.990199                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11382.722942                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11409.278707                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11395.990199                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    80485889                       # DTB read hits
system.cpu1.dtb.read_misses                     94650                       # DTB read misses
system.cpu1.dtb.write_hits                   73083689                       # DTB write hits
system.cpu1.dtb.write_misses                    28922                       # DTB write misses
system.cpu1.dtb.flush_tlb                       51788                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   69957                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4240                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                     9564                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                80580539                       # DTB read accesses
system.cpu1.dtb.write_accesses               73112611                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        153569578                       # DTB hits
system.cpu1.dtb.misses                         123572                       # DTB misses
system.cpu1.dtb.accesses                    153693150                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.inst_hits                   428597912                       # ITB inst hits
system.cpu1.itb.inst_misses                     76336                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                       51788                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              19698                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                    515                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   51781                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               428674248                       # ITB inst accesses
system.cpu1.itb.hits                        428597912                       # DTB hits
system.cpu1.itb.misses                          76336                       # DTB misses
system.cpu1.itb.accesses                    428674248                       # DTB accesses
system.cpu1.numCycles                     51781450270                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                  428322492                       # Number of instructions committed
system.cpu1.committedOps                    503238558                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            462373470                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                457847                       # Number of float alu accesses
system.cpu1.num_func_calls                   25589000                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     65138542                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   462373470                       # number of integer instructions
system.cpu1.num_fp_insts                       457847                       # number of float instructions
system.cpu1.num_int_register_reads          672243876                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         366665103                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              741025                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             381476                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           111687570                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          111401234                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    153562143                       # number of memory refs
system.cpu1.num_load_insts                   80482788                       # Number of load instructions
system.cpu1.num_store_insts                  73079355                       # Number of store instructions
system.cpu1.num_idle_cycles              50246687172.676186                       # Number of idle cycles
system.cpu1.num_busy_cycles              1534763097.323812                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.029639                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.970361                       # Percentage of idle cycles
system.cpu1.Branches                         95580848                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                348749586     69.26%     69.26% # Class of executed instruction
system.cpu1.op_class::IntMult                 1110324      0.22%     69.48% # Class of executed instruction
system.cpu1.op_class::IntDiv                    49704      0.01%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  2      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  8      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                 12      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.49% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc             56056      0.01%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::MemRead                80482788     15.98%     85.49% # Class of executed instruction
system.cpu1.op_class::MemWrite               73079355     14.51%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 503527836                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq                40424                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40424                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136733                       # Transaction distribution
system.iobus.trans_dist::WriteResp              30069                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp       106664                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        48308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       123190                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231044                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  354314                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        48328                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          263                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          251                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       156320                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334608                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7493014                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36706000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               12000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            21947000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy              142000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            32658000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy              101000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy          1042410724                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer28.occupancy               30000                       # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            93124000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           179081273                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              297000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115504                       # number of replacements
system.iocache.tags.tagsinuse               10.454717                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115520                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13154373196000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.509635                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.945082                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219352                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434068                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653420                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040055                       # Number of tag accesses
system.iocache.tags.data_accesses             1040055                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8858                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8895                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide       106664                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total       106664                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8858                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8898                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8858                       # number of overall misses
system.iocache.overall_misses::total             8898                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5479000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1913667012                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1919146012                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       339000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       339000                       # number of WriteReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide  28832566439                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  28832566439                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5818000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1913667012                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1919485012                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5818000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1913667012                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1919485012                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8858                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8895                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total       106664                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8858                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8898                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8858                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8898                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 216038.271845                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 215755.594379                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       113000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       113000                       # average WriteReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270312.068167                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270312.068167                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 215720.949876                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       145450                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 216038.271845                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 215720.949876                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        223529                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                27514                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     8.124191                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106631                       # number of writebacks
system.iocache.writebacks::total               106631                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8858                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8895                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total       106664                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8858                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8898                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8858                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8898                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3555000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1452961512                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1456516512                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       183000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total  23285992485                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3738000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1452961512                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1456699512                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3738000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1452961512                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1456699512                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164028.167984                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 163745.532546                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        61000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        61000                       # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218311.637338                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218311.637338                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        93450                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 164028.167984                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 163710.891436                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                  1132290                       # number of replacements
system.l2c.tags.tagsinuse                65332.905134                       # Cycle average of tags in use
system.l2c.tags.total_refs                   26887895                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1194294                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    22.513631                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               6379783000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   38092.537924                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   152.896952                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   229.074218                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     2954.015231                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     9873.444708                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.350600                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   215.925176                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     4167.527871                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     9496.132455                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.581246                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002333                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.003495                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.045075                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.150657                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002309                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.003295                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.063591                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.144899                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.996901                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          242                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        61762                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          241                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          421                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2430                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         5430                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53446                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003693                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.942413                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                255508368                       # Number of tag accesses
system.l2c.tags.data_accesses               255508368                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker       218363                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker       160178                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst            6707988                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data            3047209                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker       224681                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker       161726                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst            6694510                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data            3129038                       # number of ReadReq hits
system.l2c.ReadReq_hits::total               20343693                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         7479557                       # number of Writeback hits
system.l2c.Writeback_hits::total              7479557                       # number of Writeback hits
system.l2c.WriteInvalidateReq_hits::cpu0.data       365275                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::cpu1.data       366564                       # number of WriteInvalidateReq hits
system.l2c.WriteInvalidateReq_hits::total       731839                       # number of WriteInvalidateReq hits
system.l2c.UpgradeReq_hits::cpu0.data            4770                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data            4600                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                9370                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           793764                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           822353                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total              1616117                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker        218363                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker        160178                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst             6707988                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data             3840973                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker        224681                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker        161726                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst             6694510                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data             3951391                       # number of demand (read+write) hits
system.l2c.demand_hits::total                21959810                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker       218363                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker       160178                       # number of overall hits
system.l2c.overall_hits::cpu0.inst            6707988                       # number of overall hits
system.l2c.overall_hits::cpu0.data            3840973                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker       224681                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker       161726                       # number of overall hits
system.l2c.overall_hits::cpu1.inst            6694510                       # number of overall hits
system.l2c.overall_hits::cpu1.data            3951391                       # number of overall hits
system.l2c.overall_hits::total               21959810                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker         1675                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker         1602                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst            36219                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data           126965                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker         1513                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker         1620                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst            38912                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data           123410                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               331916                       # number of ReadReq misses
system.l2c.WriteInvalidateReq_misses::cpu0.data       247597                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::cpu1.data       246465                       # number of WriteInvalidateReq misses
system.l2c.WriteInvalidateReq_misses::total       494062                       # number of WriteInvalidateReq misses
system.l2c.UpgradeReq_misses::cpu0.data         17085                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         16773                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             33858                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         201754                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         196780                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             398534                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker         1675                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         1602                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             36219                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            328719                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         1513                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1620                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             38912                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            320190                       # number of demand (read+write) misses
system.l2c.demand_misses::total                730450                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         1675                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         1602                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            36219                       # number of overall misses
system.l2c.overall_misses::cpu0.data           328719                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         1513                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1620                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            38912                       # number of overall misses
system.l2c.overall_misses::cpu1.data           320190                       # number of overall misses
system.l2c.overall_misses::total               730450                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    131069250                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker    129298500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst   2691102246                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data   9653109744                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    118435750                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker    129125000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst   2892814245                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data   9397803998                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total    25142758733                       # number of ReadReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::cpu0.data       116995                       # number of WriteInvalidateReq miss cycles
system.l2c.WriteInvalidateReq_miss_latency::total       116995                       # number of WriteInvalidateReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data    202885282                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    199000447                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    401885729                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data        72000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total        72000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  14909964952                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data  14551296991                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  29461261943                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    131069250                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    129298500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   2691102246                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  24563074696                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    118435750                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    129125000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   2892814245                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  23949100989                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     54604020676                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    131069250                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    129298500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   2691102246                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  24563074696                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    118435750                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    129125000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   2892814245                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  23949100989                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    54604020676                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker       220038                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker       161780                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst        6744207                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data        3174174                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker       226194                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker       163346                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst        6733422                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data        3252448                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total           20675609                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      7479557                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          7479557                       # number of Writeback accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu0.data       612872                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::cpu1.data       613029                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.WriteInvalidateReq_accesses::total      1225901                       # number of WriteInvalidateReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        21855                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        21373                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           43228                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       995518                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data      1019133                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          2014651                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker       220038                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker       161780                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst         6744207                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         4169692                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker       226194                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker       163346                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst         6733422                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         4271581                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total            22690260                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker       220038                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker       161780                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst        6744207                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        4169692                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker       226194                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker       163346                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst        6733422                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        4271581                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total           22690260                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.007612                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.009902                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst      0.005370                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data      0.039999                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006689                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.009918                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst      0.005779                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data      0.037944                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.016054                       # miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu0.data     0.403995                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::cpu1.data     0.402045                       # miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_miss_rate::total     0.403019                       # miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.781743                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.784775                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.783242                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.202662                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.193086                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.197818                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.007612                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.009902                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.005370                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.078835                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006689                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.009918                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.005779                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.074958                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.032192                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.007612                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.009902                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.005370                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.078835                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006689                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.009918                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.005779                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.074958                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.032192                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78250.298507                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 80710.674157                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74300.843370                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 76029.691206                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78278.750826                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 79706.790123                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74342.471346                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 76151.073641                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 75750.366758                       # average ReadReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data     0.472522                       # average WriteInvalidateReq miss latency
system.l2c.WriteInvalidateReq_avg_miss_latency::total     0.236802                       # average WriteInvalidateReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11875.053088                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11864.332379                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 11869.742129                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        72000                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        72000                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73901.706791                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73947.032173                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73924.086635                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78250.298507                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80710.674157                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 74300.843370                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 74723.623204                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78278.750826                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 79706.790123                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74342.471346                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 74796.530151                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 74753.947123                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78250.298507                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80710.674157                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 74300.843370                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 74723.623204                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78278.750826                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 79706.790123                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74342.471346                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 74796.530151                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 74753.947123                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              962855                       # number of writebacks
system.l2c.writebacks::total                   962855                       # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1675                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         1602                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst        36219                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data       126965                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         1513                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         1620                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst        38912                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data       123410                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total          331916                       # number of ReadReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data       247597                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data       246465                       # number of WriteInvalidateReq MSHR misses
system.l2c.WriteInvalidateReq_mshr_misses::total       494062                       # number of WriteInvalidateReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        17085                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        16773                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        33858                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data       201754                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data       196780                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        398534                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         1675                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         1602                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        36219                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       328719                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         1513                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1620                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        38912                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       320190                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           730450                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         1675                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         1602                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        36219                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       328719                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         1513                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1620                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        38912                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       320190                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          730450                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst   2232246754                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data   8054556756                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst   2399864755                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data   7845308002                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total  20959851267                       # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data   5354998508                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data   5322652000                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total  10677650508                       # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    170934584                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    167796772                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    338731356                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        60000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total        60000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  12329683548                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  12037605009                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  24367288557                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   2232246754                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  20384240304                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   2399864755                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  19882913011                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total  45327139824                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    110160750                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    109290500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   2232246754                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  20384240304                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     99541250                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    108882500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   2399864755                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  19882913011                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total  45327139824                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2468159752                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2821001751                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7538131503                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2382381500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   2784161000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   5166542500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1524532500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   4850541252                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    724437500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   5605162751                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  12704674003                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.039999                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.037944                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.016054                       # mshr miss rate for ReadReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data     0.403995                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data     0.402045                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total     0.403019                       # mshr miss rate for WriteInvalidateReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.781743                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.784775                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.783242                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.202662                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.193086                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.197818                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.078835                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.074958                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.032192                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.007612                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009902                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005370                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.078835                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006689                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.009918                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005779                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.074958                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.032192                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63439.189981                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63571.088259                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63148.059349                       # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21627.881226                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21595.975088                       # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21611.964709                       # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.950776                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.980922                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.470317                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        60000                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        60000                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61112.461453                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61172.908878                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61142.307951                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62011.141139                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62097.232927                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62053.720068                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65767.611940                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68221.285893                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61631.926724                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62011.141139                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65790.647720                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67211.419753                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61674.155916                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62097.232927                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62053.720068                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              417721                       # Transaction distribution
system.membus.trans_dist::ReadResp             417721                       # Transaction distribution
system.membus.trans_dist::WriteReq              33871                       # Transaction distribution
system.membus.trans_dist::WriteResp             33871                       # Transaction distribution
system.membus.trans_dist::Writeback           1069486                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq       600721                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp       600721                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34423                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           34424                       # Transaction distribution
system.membus.trans_dist::ReadExReq            397977                       # Transaction distribution
system.membus.trans_dist::ReadExResp           397977                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       123190                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6936                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3570318                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      3700502                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       334782                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       334782                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4035284                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       156320                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    140106848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    140277172                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port     14030080                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total     14030080                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               154307252                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             3630                       # Total snoops (count)
system.membus.snoop_fanout::samples           2443419                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2443419    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2443419                       # Request fanout histogram
system.membus.reqLayer0.occupancy           107392500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               31000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5575997                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy         16318205493                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         7697194309                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy          186789727                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq           21137473                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp          21129474                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             33871                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            33871                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback          7479557                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq      1332565                       # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp      1225901                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           43231                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          43232                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          2014651                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         2014651                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     27041508                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     27036574                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       774452                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1144323                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              55996857                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    862740756                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1097639072                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2601008                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3569856                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total             1966550692                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          492520                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples         31930568                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            5.003619                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.060051                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5               31815006     99.64%     99.64% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                 115562      0.36%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              5                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              6                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           31930568                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy        50801737999                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          4033500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy       60715950506                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy       38798201181                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         449711000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         698488000                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------