blob: 369e9779636e713606c714c0914d05cc7a80ccb0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
|
---------- Begin Simulation Statistics ----------
sim_seconds 5.125717 # Number of seconds simulated
sim_ticks 5125716951000 # Number of ticks simulated
final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 203249 # Simulator instruction rate (inst/s)
host_op_rate 401765 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2555120499 # Simulator tick rate (ticks/s)
host_mem_usage 728844 # Number of bytes of host memory used
host_seconds 2006.06 # Real time elapsed on the host
sim_insts 407728401 # Number of instructions simulated
sim_ops 805963181 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory
system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory
system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory
system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory
system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 222005 # Total number of read requests seen
system.physmem.writeReqs 148125 # Total number of write requests seen
system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 14208320 # Total number of bytes read from memory
system.physmem.bytesWritten 9480000 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 13839 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 13931 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 14596 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 13757 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 13936 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 13652 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 13421 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 14010 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 13333 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 13233 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 13920 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 13971 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 14973 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 14183 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 13896 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 13262 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 9392 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 9725 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 9208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 9406 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 9142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 8981 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 9409 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 8580 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 8586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 9440 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 9338 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 10150 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 9429 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 9215 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 8819 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
system.physmem.totGap 5125716897500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 222005 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 148125 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 174153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 21252 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 7390 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2984 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2064 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1035 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 974 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 917 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 864 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 933 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 750 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 519 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 155 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 33 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 5396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5689 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 6383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 6417 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 6425 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 6430 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 6431 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 6433 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1045 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 752 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 4 0.01% 98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 1 0.00% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 3 0.00% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 2 0.00% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 1 0.00% 98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 4 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 3 0.00% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 7 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10499 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10563 3 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10627 2 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12739 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 7 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451 4 0.01% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17219 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17344-17347 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17728-17731 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation
system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests
system.physmem.totBusLat 1109565000 # Total cycles spent in databus access
system.physmem.totBankLat 3154263750 # Total cycles spent in bank access
system.physmem.avgQLat 18030.39 # Average queueing delay per request
system.physmem.avgBankLat 14213.97 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 37244.35 # Average memory access latency
system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 11.40 # Average write queue length over time
system.physmem.readRowHits 198637 # Number of row buffer hits during reads
system.physmem.writeRowHits 108987 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes
system.physmem.avgGap 13848423.25 # Average gap between requests
system.membus.throughput 5098961 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 662131 # Transaction distribution
system.membus.trans_dist::ReadResp 662131 # Transaction distribution
system.membus.trans_dist::WriteReq 13694 # Transaction distribution
system.membus.trans_dist::WriteResp 13694 # Transaction distribution
system.membus.trans_dist::Writeback 148125 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution
system.membus.trans_dist::ReadExReq 179249 # Transaction distribution
system.membus.trans_dist::ReadExResp 179246 # Transaction distribution
system.membus.trans_dist::MessageReq 1640 # Transaction distribution
system.membus.trans_dist::MessageResp 1640 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 25486679 # Total data (bytes)
system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.replacements 47577 # number of replacements
system.iocache.tagsinuse 0.079131 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
system.iocache.overall_misses::total 47632 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 639145 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 225496 # Transaction distribution
system.iobus.trans_dist::ReadResp 225496 # Transaction distribution
system.iobus.trans_dist::WriteReq 57527 # Transaction distribution
system.iobus.trans_dist::WriteResp 57527 # Transaction distribution
system.iobus.trans_dist::MessageReq 1640 # Transaction distribution
system.iobus.trans_dist::MessageResp 1640 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3276074 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.branchPred.lookups 85601186 # Number of BP lookups
system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups
system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions.
system.cpu.numCycles 453375451 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued
system.cpu.iq.rate 1.810787 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed
system.cpu.iew.exec_branches 83095032 # Number of branches executed
system.cpu.iew.exec_stores 9034738 # Number of stores executed
system.cpu.iew.exec_rate 1.807683 # Inst execution rate
system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back
system.cpu.iew.wb_producers 638600685 # num instructions producing a value
system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407728401 # Number of instructions committed
system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 22399743 # Number of memory references committed
system.cpu.commit.loads 13982748 # Number of loads committed
system.cpu.commit.membars 474399 # Number of memory barriers committed
system.cpu.commit.branches 82153759 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 734952654 # Number of committed integer instructions.
system.cpu.commit.function_calls 1154691 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1079657633 # The number of ROB reads
system.cpu.rob.rob_writes 1655096826 # The number of ROB writes
system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407728401 # Number of Instructions Simulated
system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated
system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads
system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads
system.cpu.int_regfile_writes 975319683 # number of integer regfile writes
system.cpu.fp_regfile_reads 50 # number of floating regfile reads
system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads
system.cpu.misc_regfile_writes 401987 # number of misc regfile writes
system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 102839393 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu.icache.replacements 953322 # number of replacements
system.cpu.icache.tagsinuse 510.127378 # Cycle average of tags in use
system.cpu.icache.total_refs 7473092 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 953834 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.834793 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 147390294000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.127378 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996343 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996343 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7473092 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7473092 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7473092 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7473092 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7473092 # number of overall hits
system.cpu.icache.overall_hits::total 7473092 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1006614 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1006614 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1006614 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1006614 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1006614 # number of overall misses
system.cpu.icache.overall_misses::total 1006614 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14222924496 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14222924496 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14222924496 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14222924496 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14222924496 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14222924496 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8479706 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8479706 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8479706 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8479706 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8479706 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8479706 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118709 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.118709 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.118709 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.118709 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.118709 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.118709 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14129.472167 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14129.472167 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14129.472167 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14129.472167 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14129.472167 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 8172 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 43.238095 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52705 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 52705 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 52705 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 52705 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 52705 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 52705 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953909 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 953909 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 953909 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 953909 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 953909 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 953909 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11745970674 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11745970674 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11745970674 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11745970674 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11745970674 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11745970674 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112493 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.112493 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112493 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.112493 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12313.512792 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12313.512792 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12313.512792 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12313.512792 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 7857 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.317656 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 21864 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 7868 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.778851 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5104284128000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.317656 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.394853 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.394853 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21875 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 21875 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21877 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 21877 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21877 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 21877 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8730 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 8730 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8730 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 8730 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8730 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 8730 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 99800500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 99800500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 99800500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 99800500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 99800500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 99800500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30605 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 30605 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30607 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 30607 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30607 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 30607 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285248 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285248 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285229 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.285229 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285229 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.285229 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11431.901489 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11431.901489 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11431.901489 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11431.901489 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11431.901489 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 1569 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1569 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8730 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8730 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8730 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 8730 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8730 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 8730 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 82333015 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 82333015 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 82333015 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 82333015 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 82333015 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 82333015 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285248 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285248 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285229 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285229 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285229 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9431.044101 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9431.044101 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9431.044101 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 67431 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 14.830291 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 90986 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 67447 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.349000 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 4994048518000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.830291 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.926893 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.926893 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90986 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 90986 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90986 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 90986 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90986 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 90986 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68526 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 68526 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68526 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 68526 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68526 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 68526 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854232500 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854232500 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854232500 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 854232500 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854232500 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 854232500 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 159512 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 159512 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 159512 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 159512 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 159512 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 159512 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.429598 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.429598 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.429598 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.429598 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.429598 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.429598 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.815895 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.815895 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.815895 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.815895 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.815895 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 18479 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 18479 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68526 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68526 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68526 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 68526 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68526 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 68526 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 717130107 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 717130107 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 717130107 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 717130107 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 717130107 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 717130107 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.429598 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.429598 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.429598 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.429598 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.080510 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.080510 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.080510 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1656381 # number of replacements
system.cpu.dcache.tagsinuse 511.996762 # Cycle average of tags in use
system.cpu.dcache.total_refs 18981789 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1656893 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.456255 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 37864000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.996762 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10887156 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10887156 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8091896 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8091896 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 18979052 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18979052 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18979052 # number of overall hits
system.cpu.dcache.overall_hits::total 18979052 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2237799 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2237799 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 315625 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315625 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2553424 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2553424 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2553424 # number of overall misses
system.cpu.dcache.overall_misses::total 2553424 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33108471000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33108471000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12021128996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12021128996 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 45129599996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 45129599996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45129599996 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45129599996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13124955 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13124955 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8407521 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8407521 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21532476 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21532476 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21532476 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21532476 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170500 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.170500 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037541 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037541 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.118585 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.118585 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118585 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118585 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14795.104922 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14795.104922 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38086.745334 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38086.745334 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17674.150472 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17674.150472 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17674.150472 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 405217 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 42719 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.485639 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1558312 # number of writebacks
system.cpu.dcache.writebacks::total 1558312 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 868331 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 868331 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25900 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25900 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 894231 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 894231 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 894231 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 894231 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369468 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1369468 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289725 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 289725 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1659193 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1659193 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1659193 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1659193 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17883109030 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17883109030 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11189452001 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11189452001 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29072561031 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29072561031 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29072561031 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29072561031 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349104500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349104500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2521383000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2521383000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99870487500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99870487500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104341 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104341 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034460 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034460 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077055 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077055 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077055 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13058.435122 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13058.435122 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38620.940551 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38620.940551 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17522.109261 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17522.109261 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 110887 # number of replacements
system.cpu.l2cache.tagsinuse 64831.056251 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3780740 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 175156 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 21.584987 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50733.546083 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 16.870188 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.435873 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3102.105896 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 10978.098210 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.774132 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000257 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.047334 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.167512 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989243 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63592 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7072 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 937746 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1332853 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2341263 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1578360 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1578360 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 154746 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 154746 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 63592 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 7072 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 937746 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1487599 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2496009 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 63592 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 7072 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 937746 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1487599 # number of overall hits
system.cpu.l2cache.overall_hits::total 2496009 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 16053 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 51995 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1482 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1482 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 132789 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 132789 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 16053 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168664 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 184784 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 16053 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168664 # number of overall misses
system.cpu.l2cache.overall_misses::total 184784 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6023000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 505500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1392940500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2991754000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4391223000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17604000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 17604000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9307246499 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9307246499 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6023000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 505500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1392940500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12299000499 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13698469499 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6023000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 505500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1392940500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12299000499 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13698469499 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63653 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7078 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 953799 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1368728 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2393258 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1578360 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1578360 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 287535 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 287535 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63653 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 7078 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 953799 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1656263 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2680793 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63653 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 7078 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 953799 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1656263 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2680793 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000958 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000848 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016831 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026210 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823791 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823791 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461819 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.461819 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000958 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000848 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016831 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.101834 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.068929 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000958 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000848 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016831 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.101834 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.068929 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 98737.704918 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84250 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86771.351149 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83393.839721 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84454.716800 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11878.542510 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11878.542510 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70090.493181 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70090.493181 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74132.335586 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 98737.704918 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84250 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86771.351149 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72920.128178 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74132.335586 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 101458 # number of writebacks
system.cpu.l2cache.writebacks::total 101458 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16050 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35873 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 51990 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1482 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132789 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 132789 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16050 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168662 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 184779 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16050 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168662 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 184779 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5260750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1193323263 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545977303 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3744991316 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15894959 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15894959 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7671814321 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7671814321 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5260750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1193323263 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10217791624 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11416805637 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5260750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1193323263 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10217791624 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11416805637 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236814500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236814500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2356578000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2356578000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91593392500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91593392500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026209 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823791 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823791 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461819 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461819 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.068927 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000958 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000848 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016827 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101833 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.068927 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74350.359065 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70971.965071 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72032.916253 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10725.343455 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10725.343455 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57774.471688 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57774.471688 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 86241.803279 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74350.359065 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60581.468404 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61786.272450 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|