path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.133818                       # Number of seconds simulated
sim_ticks                                5133817564000                       # Number of ticks simulated
final_tick                               5133817564000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 116267                       # Simulator instruction rate (inst/s)
host_op_rate                                   229827                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1463849171                       # Simulator tick rate (ticks/s)
host_mem_usage                                 730944                       # Number of bytes of host memory used
host_seconds                                  3507.07                       # Real time elapsed on the host
sim_insts                                   407756178                       # Number of instructions simulated
sim_ops                                     806017145                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2427456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1027392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10775296                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14234240                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1027392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1027392                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9523712                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9523712                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        37929                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16053                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168364                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222410                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148808                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148808                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       472836                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            723                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               200122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2098886                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2772642                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          200122                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             200122                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1855094                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1855094                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1855094                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       472836                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           723                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              200122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2098886                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4627736                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222410                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       148808                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      222410                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     148808                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                     14234240                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9523712                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14234240                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9523712                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       59                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               1680                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14445                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13880                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 14292                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 13655                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13870                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13478                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13505                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 14003                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13721                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13556                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13489                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                13720                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                14708                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                14278                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                14115                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                13636                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9830                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  9327                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  9583                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  9096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  9291                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8966                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8927                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  9335                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  9016                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8977                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8994                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 9147                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 9992                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 9572                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 9603                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 9152                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           8                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5133817509500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  222410                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 148808                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    174478                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21469                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7432                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2969                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2498                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2034                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1242                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1131                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1042                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       990                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      926                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      901                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      960                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      914                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      731                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      134                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5728                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6410                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6470                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6469                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1064                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      742                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        62679                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      378.930359                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     154.401970                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1268.483208                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          27823     44.39%     44.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         9775     15.60%     59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         5839      9.32%     69.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         3939      6.28%     75.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         2540      4.05%     79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         2068      3.30%     82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1534      2.45%     85.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515         1237      1.97%     87.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579          969      1.55%     88.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          885      1.41%     90.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          570      0.91%     91.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          566      0.90%     92.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          409      0.65%     92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          368      0.59%     93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          359      0.57%     93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          470      0.75%     94.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          261      0.42%     95.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          223      0.36%     95.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          183      0.29%     95.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          154      0.25%     96.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          153      0.24%     96.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          166      0.26%     96.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          503      0.80%     97.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          192      0.31%     97.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603          116      0.19%     97.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           97      0.15%     97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           69      0.11%     98.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           63      0.10%     98.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           31      0.05%     98.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           26      0.04%     98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           27      0.04%     98.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           24      0.04%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           21      0.03%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           14      0.02%     98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           16      0.03%     98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           18      0.03%     98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371           16      0.03%     98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435           13      0.02%     98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            7      0.01%     98.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563            6      0.01%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627           11      0.02%     98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            6      0.01%     98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            5      0.01%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            7      0.01%     98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            8      0.01%     98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947            4      0.01%     98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            3      0.00%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            4      0.01%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139            4      0.01%     98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            4      0.01%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267            6      0.01%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331            6      0.01%     98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            2      0.00%     98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           10      0.02%     98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            4      0.01%     98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            6      0.01%     98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            4      0.01%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715            2      0.00%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779           10      0.02%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843            4      0.01%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            1      0.00%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971            2      0.00%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035            4      0.01%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           25      0.04%     98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163            7      0.01%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227            2      0.00%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291            3      0.00%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            5      0.01%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419            2      0.00%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483            2      0.00%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            5      0.01%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611            2      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            1      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803            1      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867            1      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            5      0.01%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995            2      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059            4      0.01%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123            6      0.01%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187            1      0.00%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251            2      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315            1      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379            1      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443            2      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571            2      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635            2      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699            3      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891            1      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955            1      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019            2      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083            1      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147            5      0.01%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211            1      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275            2      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403            2      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467            2      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            2      0.00%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            5      0.01%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            3      0.00%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915            8      0.01%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979            2      0.00%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171            5      0.01%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491            2      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            3      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683            1      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            2      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875            1      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            1      0.00%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067            3      0.00%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            4      0.01%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195          340      0.54%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387            2      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8515            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899            2      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539            6      0.01%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603            3      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731            3      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9923            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115            3      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10563            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10755            2      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10816-10819            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11075            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12163            2      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12355            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13763            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13891            2      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147            2      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            2      0.00%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275            1      0.00%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339            4      0.01%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14531            2      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915           32      0.05%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979           14      0.02%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043            7      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107           11      0.02%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            4      0.01%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            5      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299            6      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363            4      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427            4      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491            5      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555            6      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619            5      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683            9      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            2      0.00%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811            3      0.00%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875            8      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939            3      0.00%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003            8      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067            2      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131            8      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195            6      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259           15      0.02%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323            9      0.01%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387           59      0.09%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579            3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17795            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          62679                       # Bytes accessed per row activation
system.physmem.totQLat                     3976321749                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                8255787999                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1111755000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3167711250                       # Total cycles spent in bank access
system.physmem.avgQLat                       17883.08                       # Average queueing delay per request
system.physmem.avgBankLat                    14246.44                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  37129.53                       # Average memory access latency
system.physmem.avgRdBW                           2.77                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.77                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.86                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        11.10                       # Average write queue length over time
system.physmem.readRowHits                     198876                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109583                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.44                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.64                       # Row buffer hit rate for writes
system.physmem.avgGap                     13829656.72                       # Average gap between requests
system.membus.throughput                      5107370                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662136                       # Transaction distribution
system.membus.trans_dist::ReadResp             662131                       # Transaction distribution
system.membus.trans_dist::WriteReq              13778                       # Transaction distribution
system.membus.trans_dist::WriteResp             13778                       # Transaction distribution
system.membus.trans_dist::Writeback            148808                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2204                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1699                       # Transaction distribution
system.membus.trans_dist::ReadExReq            179955                       # Transaction distribution
system.membus.trans_dist::ReadExResp           179952                       # Transaction distribution
system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
system.membus.trans_dist::BadAddressError            5                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471084                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775074                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475656                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721824                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132231                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       132231                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1857341                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241828                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550145                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18343808                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20135781                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5414144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5414144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25556497                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25556497                       # Total data (bytes)
system.membus.snoop_data_through_bus           663808                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250614500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583282500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1610621247                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                7000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3158121946                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429462997                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47580                       # number of replacements
system.iocache.tags.tagsinuse                0.104004                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992837152000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.104004                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006500                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006500                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47635                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47635                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47635                       # number of overall misses
system.iocache.overall_misses::total            47635                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    155029196                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    155029196                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10272164340                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10272164340                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10427193536                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10427193536                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10427193536                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10427193536                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47635                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47635                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47635                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47635                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169430.815301                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 169430.815301                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 219866.531250                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 219866.531250                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 218897.733515                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 218897.733515                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 218897.733515                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 218897.733515                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        145846                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                13667                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.671398                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47635                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47635                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47635                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47635                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    107414696                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    107414696                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7841262846                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7841262846                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7948677542                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7948677542                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7948677542                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7948677542                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117393.110383                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117393.110383                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 167835.249272                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 167835.249272                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 166866.328162                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 166866.328162                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        638173                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225571                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225571                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57606                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57606                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471084                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569640                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241828                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276264                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276264                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3919850                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424475539                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460198000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53455003                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu.branchPred.lookups                85568278                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85568278                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            875805                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79194721                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77515005                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.879005                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1436703                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             179530                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        453826303                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25491689                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422571983                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85568278                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78951708                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162597841                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 3951278                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     103753                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               71390541                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                42483                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         91488                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          407                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8456173                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                381386                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2285                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          262749158                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.176501                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.411322                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                100566215     38.27%     38.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1530086      0.58%     38.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71818264     27.33%     66.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   889095      0.34%     66.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1565087      0.60%     67.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2386199      0.91%     68.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1016423      0.39%     68.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1323196      0.50%     68.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81654593     31.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            262749158                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.188549                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.931132                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29394099                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              68537094                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158445926                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3341083                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3030956                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832311849                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   975                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3030956                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32089229                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                43247389                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12548061                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158740332                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13093191                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829412646                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 22400                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6072204                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               5134846                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             9895                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           991013941                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1799757815                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1799757415                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               400                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963928798                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27085141                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             453471                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         459839                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29598553                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16699186                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9813003                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1103116                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           919400                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  824665019                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1185670                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 820786759                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            149059                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19014850                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     28966021                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         131061                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     262749158                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.123842                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.400884                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            76415434     29.08%     29.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15773446      6.00%     35.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10534030      4.01%     39.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7363874      2.80%     41.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75721487     28.82%     70.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3737655      1.42%     72.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72289188     27.51%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              768072      0.29%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              145972      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       262749158                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  347595     33.06%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    241      0.02%     33.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     298      0.03%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 548989     52.22%     85.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                154170     14.66%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            308427      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793336759     96.66%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149572      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124334      0.02%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17650951      2.15%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9216716      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              820786759                       # Type of FU issued
system.cpu.iq.rate                           1.808592                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1051293                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001281                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905631270                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         844875947                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    816895262                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 170                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                180                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           48                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821529545                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      80                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1693324                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2710358                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        18596                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11994                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1389490                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1931520                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12323                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3030956                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                31365465                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2153394                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           825850689                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            245046                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16699186                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9813003                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             690244                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1620381                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 14551                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11994                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         492991                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506844                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               999835                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819394540                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17351060                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1392218                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26384270                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83073397                       # Number of branches executed
system.cpu.iew.exec_stores                    9033210                       # Number of stores executed
system.cpu.iew.exec_rate                     1.805525                       # Inst execution rate
system.cpu.iew.wb_sent                      818994723                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     816895310                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638461899                       # num instructions producing a value
system.cpu.iew.wb_consumers                1043741013                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.800018                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611705                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19724455                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054609                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            885977                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    259718202                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.103430                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863863                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     88192844     33.96%     33.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11850002      4.56%     38.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3832476      1.48%     40.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74743456     28.78%     68.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2382743      0.92%     69.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1477125      0.57%     70.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       857323      0.33%     70.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70846576     27.28%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5535657      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    259718202                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407756178                       # Number of instructions committed
system.cpu.commit.committedOps              806017145                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22412340                       # Number of memory references committed
system.cpu.commit.loads                      13988827                       # Number of loads committed
system.cpu.commit.membars                      474703                       # Number of memory barriers committed
system.cpu.commit.branches                   82157257                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735004802                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155200                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5535657                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1079845864                       # The number of ROB reads
system.cpu.rob.rob_writes                  1654528920                       # The number of ROB writes
system.cpu.timesIdled                         1259880                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       191077145                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9813814465                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407756178                       # Number of Instructions Simulated
system.cpu.committedOps                     806017145                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407756178                       # Number of Instructions Simulated
system.cpu.cpi                               1.112984                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.112984                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.898485                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.898485                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1504160790                       # number of integer regfile reads
system.cpu.int_regfile_writes               975149499                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
system.cpu.misc_regfile_reads               263996873                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402343                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53588361                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3012770                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3012220                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13778                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13778                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1579976                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2276                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2276                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       334451                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287744                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            5                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1911499                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6119032                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        17478                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       153515                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8201524                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61164352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207421989                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       548096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5363392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      274497829                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         274473317                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       639552                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4034739870                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       574500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1437663197                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3140492264                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      13374496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     104626155                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            955225                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.955368                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7446917                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            955737                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.791806                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147479365250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.955368                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996007                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996007                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7446917                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7446917                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7446917                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7446917                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7446917                       # number of overall hits
system.cpu.icache.overall_hits::total         7446917                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1009251                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1009251                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1009251                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1009251                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1009251                       # number of overall misses
system.cpu.icache.overall_misses::total       1009251                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14258935392                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14258935392                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14258935392                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14258935392                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14258935392                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14258935392                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8456168                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8456168                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8456168                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8456168                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8456168                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8456168                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119351                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.119351                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.119351                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.119351                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.119351                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.119351                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14128.235089                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14128.235089                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14128.235089                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14128.235089                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14128.235089                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14128.235089                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6628                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               229                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    28.943231                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53445                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        53445                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        53445                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        53445                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        53445                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        53445                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       955806                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       955806                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       955806                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       955806                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       955806                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       955806                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11762227547                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11762227547                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11762227547                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11762227547                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11762227547                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11762227547                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.113031                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.113031                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.113031                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.113031                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.113031                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.113031                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12306.082560                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12306.082560                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12306.082560                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12306.082560                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12306.082560                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12306.082560                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         8028                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.311146                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        21788                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         8039                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.710287                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5106556199500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.311146                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.394447                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.394447                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        21802                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        21802                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        21804                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        21804                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        21804                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        21804                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         8914                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         8914                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         8914                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         8914                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         8914                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         8914                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     98082749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     98082749                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     98082749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     98082749                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     98082749                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     98082749                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30716                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        30716                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30718                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        30718                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30718                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        30718                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.290207                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.290207                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.290188                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.290188                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.290188                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.290188                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11003.225151                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11003.225151                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11003.225151                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11003.225151                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11003.225151                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11003.225151                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1772                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1772                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         8914                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         8914                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         8914                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         8914                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         8914                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         8914                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     80247757                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     80247757                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     80247757                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     80247757                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     80247757                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     80247757                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.290207                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.290207                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.290188                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.290188                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.290188                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.290188                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9002.440767                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9002.440767                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9002.440767                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9002.440767                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9002.440767                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9002.440767                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        68638                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    13.809611                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        91506                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        68653                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.332877                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5104119753500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.809611                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.863101                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.863101                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        91510                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        91510                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        91510                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        91510                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        91510                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        91510                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        69712                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        69712                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        69712                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        69712                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        69712                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        69712                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    854471475                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    854471475                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    854471475                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    854471475                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    854471475                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    854471475                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       161222                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       161222                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       161222                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       161222                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       161222                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       161222                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.432398                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.432398                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.432398                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.432398                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.432398                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.432398                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12257.164835                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12257.164835                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12257.164835                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12257.164835                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12257.164835                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12257.164835                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        20719                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        20719                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        69712                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        69712                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        69712                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        69712                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        69712                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        69712                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    714931165                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    714931165                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    714931165                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    714931165                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    714931165                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    714931165                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.432398                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.432398                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.432398                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.432398                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.432398                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.432398                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10255.496399                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10255.496399                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10255.496399                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1655321                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.993756                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18976383                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1655833                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.460324                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          38296250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.993756                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999988                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999988                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10875506                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10875506                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8098167                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8098167                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      18973673                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18973673                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18973673                       # number of overall hits
system.cpu.dcache.overall_hits::total        18973673                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2232931                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2232931                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315791                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315791                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2548722                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2548722                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2548722                       # number of overall misses
system.cpu.dcache.overall_misses::total       2548722                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33105603008                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33105603008                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12178134710                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12178134710                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45283737718                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45283737718                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45283737718                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45283737718                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13108437                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13108437                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8413958                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8413958                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21522395                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21522395                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21522395                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21522395                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170343                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170343                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037532                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037532                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118422                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118422                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118422                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118422                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14826.075238                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14826.075238                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38563.906856                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38563.906856                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.233036                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17767.233036                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.233036                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17767.233036                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       397899                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42056                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.461171                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1557485                       # number of writebacks
system.cpu.dcache.writebacks::total           1557485                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       864709                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       864709                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25884                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25884                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       890593                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       890593                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       890593                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       890593                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1368222                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1368222                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289907                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289907                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1658129                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1658129                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1658129                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1658129                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17890826726                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17890826726                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11280486479                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11280486479                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29171313205                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29171313205                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29171313205                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29171313205                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97364618000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97364618000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2538596500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2538596500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99903214500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99903214500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104377                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104377                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034455                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034455                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077042                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077042                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077042                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077042                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13075.967735                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13075.967735                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38910.707499                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38910.707499                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.909360                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.909360                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.909360                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.909360                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111515                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64833.541766                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3779668                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           175596                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.524796                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50736.164769                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.333778                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.436924                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3104.326837                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10979.279458                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.774172                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000203                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047368                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.167531                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989281                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        63026                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         6786                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       939635                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1331578                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2341025                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1579976                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1579976                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          330                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          330                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154233                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154233                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        63026                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         6786                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       939635                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1485811                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2495258                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        63026                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         6786                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       939635                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1485811                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2495258                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16058                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35805                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        51927                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1441                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1441                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133490                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133490                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16058                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169295                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185417                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           58                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16058                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169295                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185417                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6074750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       507000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1388421484                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3011977215                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4406980449                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17718298                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17718298                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9403560917                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9403560917                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6074750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       507000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1388421484                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12415538132                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13810541366                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6074750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       507000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1388421484                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12415538132                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13810541366                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        63084                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         6792                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       955693                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1367383                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2392952                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1579976                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1579976                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1771                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1771                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287723                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287723                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        63084                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         6792                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       955693                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1655106                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2680675                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        63084                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         6792                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       955693                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1655106                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2680675                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000919                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000883                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016802                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026185                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021700                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.813665                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.813665                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463953                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.463953                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000919                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000883                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016802                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102287                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.069168                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000919                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000883                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016802                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102287                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.069168                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 104737.068966                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        84500                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86462.914684                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84121.692920                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84868.766711                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12295.834837                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12295.834837                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70443.935254                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70443.935254                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 104737.068966                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        84500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86462.914684                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73336.708893                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74483.684700                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 104737.068966                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        84500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86462.914684                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73336.708893                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74483.684700                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102141                       # number of writebacks
system.cpu.l2cache.writebacks::total           102141                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            7                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            7                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            7                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16053                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35803                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        51920                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1441                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1441                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133490                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133490                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16053                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169293                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185410                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16053                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169293                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185410                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5335250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       430000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1185393516                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2560977283                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3752136049                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15491421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15491421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7726929083                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7726929083                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5335250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       430000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1185393516                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10287906366                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11479065132                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5335250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       430000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1185393516                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10287906366                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11479065132                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89251391500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89251391500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2372712000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2372712000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91624103500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91624103500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000919                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000883                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016797                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026184                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021697                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.813665                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.813665                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463953                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463953                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000919                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000883                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016797                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102285                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.069165                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000919                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000883                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016797                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102285                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.069165                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73842.491497                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71529.684188                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72267.643471                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10750.465649                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10750.465649                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.954476                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.954476                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73842.491497                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60769.827258                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61911.790799                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73842.491497                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60769.827258                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61911.790799                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------