path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.147413                       # Number of seconds simulated
sim_ticks                                5147413032500                       # Number of ticks simulated
final_tick                               5147413032500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 192321                       # Simulator instruction rate (inst/s)
host_op_rate                                   378987                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2320932369                       # Simulator tick rate (ticks/s)
host_mem_usage                                 367552                       # Number of bytes of host memory used
host_seconds                                  2217.82                       # Real time elapsed on the host
sim_insts                                   426532736                       # Number of instructions simulated
sim_ops                                     840526050                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2503168                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1073280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10624512                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14204736                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1073280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1073280                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9409088                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9409088                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        39112                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           53                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16770                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             166008                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                221949                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          147017                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               147017                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       486296                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            659                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               208509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2064049                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2759587                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          208509                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             208509                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1827926                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1827926                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1827926                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       486296                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           659                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              208509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2064049                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4587513                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        110659                       # number of replacements
system.l2c.tagsinuse                     64846.009272                       # Cycle average of tags in use
system.l2c.total_refs                         3990913                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        174907                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         22.817343                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        50048.797239                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       13.777958                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.155980                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           3384.461133                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data          11398.816962                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.763684                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000210                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.051643                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.173932                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.989472                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        111705                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          9478                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst             1055456                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data             1342066                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2518705                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         1610504                       # number of Writeback hits
system.l2c.Writeback_hits::total              1610504                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data              315                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 315                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            161822                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               161822                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         111705                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           9478                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst              1055456                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data              1503888                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2680527                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        111705                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          9478                       # number of overall hits
system.l2c.overall_hits::cpu.inst             1055456                       # number of overall hits
system.l2c.overall_hits::cpu.data             1503888                       # number of overall hits
system.l2c.overall_hits::total                2680527                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker           53                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             16771                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             36056                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                52886                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           1746                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              1746                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          130897                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             130897                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker           53                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              16771                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             166953                       # number of demand (read+write) misses
system.l2c.demand_misses::total                183783                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker           53                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.l2c.overall_misses::cpu.inst             16771                       # number of overall misses
system.l2c.overall_misses::cpu.data            166953                       # number of overall misses
system.l2c.overall_misses::total               183783                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2763500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       312000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst    876462500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data   1897742000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2777280000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data     38052500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     38052500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   6815913500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6815913500                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      2763500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       312000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst    876462500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   8713655500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      9593193500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      2763500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       312000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst    876462500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   8713655500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     9593193500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       111758                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         9484                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst         1072227                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data         1378122                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2571591                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1610504                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1610504                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         2061                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2061                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        292719                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292719                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       111758                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         9484                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst          1072227                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data          1670841                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2864310                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       111758                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         9484                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1072227                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data         1670841                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2864310                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000633                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.015641                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.026163                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.020565                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.847162                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.847162                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.447176                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.447176                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000633                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.015641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.099922                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.064163                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000474                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000633                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.015641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.099922                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.064163                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52260.598652                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52633.181717                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52514.465076                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 21794.100802                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 21794.100802                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52070.815221                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52070.815221                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52260.598652                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52192.266686                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52198.481361                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52141.509434                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52260.598652                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52192.266686                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52198.481361                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              100350                       # number of writebacks
system.l2c.writebacks::total                   100350                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           53                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        16770                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        36055                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           52884                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         1746                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1746                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       130897                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        130897                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker           53                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         16770                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        166952                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           183781                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker           53                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        16770                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       166952                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          183781                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       240000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    671584500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data   1456546000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2130491500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     70212000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     70212000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5237071500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5237071500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker       240000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    671584500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   6693617500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   7367563000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2121000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker       240000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    671584500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   6693617500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   7367563000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59976004500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59976004500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1230258000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1230258000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data  61206262500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  61206262500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026162                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.020565                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.847162                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.847162                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.447176                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.447176                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.099921                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.064162                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000474                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000633                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.015640                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.099921                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.064162                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40397.892109                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40286.126239                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40213.058419                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40213.058419                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40009.102577                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40009.102577                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40093.065672                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40088.817669                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40018.867925                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40046.779964                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40093.065672                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40088.817669                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47569                       # number of replacements
system.iocache.tagsinuse                     0.147452                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47585                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4996357767000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.147452                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.009216                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.009216                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
system.iocache.overall_misses::total            47624                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    113343932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    113343932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6309295160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   6309295160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   6422639092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   6422639092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   6422639092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   6422639092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125380.455752                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125380.455752                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 135044.845034                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 135044.845034                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 134861.395347                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 134861.395347                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 134861.395347                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 134861.395347                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      66555216                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11227                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  5928.138951                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47624                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47624                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47624                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66312982                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     66312982                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3879551568                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3879551568                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3945864550                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   3945864550                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3945864550                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   3945864550                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73355.068584                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73355.068584                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 83038.346918                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 83038.346918                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82854.538678                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 82854.538678                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82854.538678                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        459902894                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 90033870                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           90033870                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1172024                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              84304215                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 81702749                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           29359737                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      447000113                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    90033870                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           81702749                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     169792580                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5290860                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     149776                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               97806900                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                37530                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         36600                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          214                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9375679                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                523969                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5232                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          301265833                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.919513                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.390338                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                131910949     43.79%     43.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1767278      0.59%     44.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72780383     24.16%     68.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   988082      0.33%     68.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1637864      0.54%     69.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3667894      1.22%     70.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1147346      0.38%     71.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1446143      0.48%     71.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85919894     28.52%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            301265833                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.195767                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.971945                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 34474494                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              93907388                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 163990791                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4810664                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4082496                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              876264710                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   919                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4082496                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 38727929                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                39278399                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10114969                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 164053704                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              45008336                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              872424503                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  9763                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               34576608                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3790570                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents         31863881                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1394114241                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2488384373                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       2488383477                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               896                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1347565425                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 46548809                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             469868                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         476809                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  46309775                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             18907776                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10445518                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1298255                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1025454                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  865635268                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1719822                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 864337626                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            112774                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        25913081                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     53108345                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         204185                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     301265833                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.869020                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.387854                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            94932773     31.51%     31.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            22142074      7.35%     38.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            18888671      6.27%     45.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7860945      2.61%     47.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            80656411     26.77%     74.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3302785      1.10%     75.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72810465     24.17%     99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              540656      0.18%     99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              131053      0.04%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       301265833                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  170381      8.07%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1776523     84.09%     92.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                165648      7.84%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            297256      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             829421724     95.96%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25169917      2.91%     98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9448729      1.09%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              864337626                       # Type of FU issued
system.cpu.iq.rate                           1.879392                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2112552                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002444                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2032304206                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         893278706                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    853918308                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 381                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                418                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           98                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              866152744                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     178                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1572054                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3603717                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        21501                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11898                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2033136                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7821637                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          2389                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4082496                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                25489851                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1396862                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           867355090                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            297196                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              18907776                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10445518                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             881207                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 698514                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12367                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11898                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         698869                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       624345                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1323214                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             862415633                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              24733940                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1921992                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     33937040                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86496224                       # Number of branches executed
system.cpu.iew.exec_stores                    9203100                       # Number of stores executed
system.cpu.iew.exec_rate                     1.875212                       # Inst execution rate
system.cpu.iew.wb_sent                      861954133                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     853918406                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 669978264                       # num instructions producing a value
system.cpu.iew.wb_consumers                1919317191                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.856736                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.349071                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      426532736                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        840526050                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        26723975                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1515635                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1176103                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    297198870                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.828160                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.864352                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    116541377     39.21%     39.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14339767      4.82%     44.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4295097      1.45%     45.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76671720     25.80%     71.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3910835      1.32%     72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1786901      0.60%     73.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1117084      0.38%     73.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71988132     24.22%     97.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6547957      2.20%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    297198870                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            426532736                       # Number of instructions committed
system.cpu.commit.committedOps              840526050                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23716438                       # Number of memory references committed
system.cpu.commit.loads                      15304056                       # Number of loads committed
system.cpu.commit.membars                      781569                       # Number of memory barriers committed
system.cpu.commit.branches                   85505804                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768351683                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6547957                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1157821631                       # The number of ROB reads
system.cpu.rob.rob_writes                  1738597524                       # The number of ROB writes
system.cpu.timesIdled                         2901104                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       158637061                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9834920608                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   426532736                       # Number of Instructions Simulated
system.cpu.committedOps                     840526050                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             426532736                       # Number of Instructions Simulated
system.cpu.cpi                               1.078236                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.078236                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.927441                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.927441                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2163268420                       # number of integer regfile reads
system.cpu.int_regfile_writes              1362711366                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        98                       # number of floating regfile reads
system.cpu.misc_regfile_reads               281060274                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 403581                       # number of misc regfile writes
system.cpu.icache.replacements                1071746                       # number of replacements
system.cpu.icache.tagsinuse                509.688073                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8235470                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1072258                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.680493                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56594855000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.688073                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.995485                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.995485                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      8235470                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8235470                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8235470                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8235470                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8235470                       # number of overall hits
system.cpu.icache.overall_hits::total         8235470                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1140205                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1140205                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1140205                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1140205                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1140205                       # number of overall misses
system.cpu.icache.overall_misses::total       1140205                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16916733991                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16916733991                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16916733991                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16916733991                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16916733991                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16916733991                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9375675                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9375675                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9375675                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9375675                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9375675                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9375675                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121613                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.121613                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.121613                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.121613                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.121613                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.121613                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14836.572363                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14836.572363                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14836.572363                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14836.572363                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14836.572363                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14836.572363                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2216492                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               241                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  9197.062241                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks         1572                       # number of writebacks
system.cpu.icache.writebacks::total              1572                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        67614                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        67614                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        67614                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        67614                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        67614                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        67614                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1072591                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1072591                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1072591                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1072591                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1072591                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1072591                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12848213492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12848213492                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12848213492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12848213492                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12848213492                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12848213492                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114401                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.114401                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114401                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.114401                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11978.669868                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11978.669868                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11978.669868                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11978.669868                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        12981                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.013322                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          25373                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        12993                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         1.952821                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5123561713000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.013322                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375833                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375833                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25418                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25418                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25421                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25421                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25421                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25421                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        13864                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        13864                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        13864                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        13864                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        13864                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        13864                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    165480500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    165480500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    165480500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    165480500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    165480500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    165480500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        39282                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        39282                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        39285                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        39285                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        39285                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        39285                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.352935                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.352935                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.352908                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.352908                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.352908                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.352908                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11935.985286                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11935.985286                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11935.985286                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11935.985286                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11935.985286                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11935.985286                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1460                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1460                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        13864                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        13864                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        13864                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        13864                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        13864                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        13864                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    123445500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    123445500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    123445500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    123445500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    123445500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    123445500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.352935                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.352935                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.352908                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.352908                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.352908                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.352908                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8904.032025                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8904.032025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8904.032025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8904.032025                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       120380                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       12.933344                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         133363                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       120396                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.107703                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5104613509000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.933344                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.808334                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.808334                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       133363                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       133363                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       133363                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       133363                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       133363                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       133363                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       121457                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       121457                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       121457                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       121457                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       121457                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       121457                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1679660000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1679660000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1679660000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1679660000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1679660000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1679660000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       254820                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       254820                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       254820                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       254820                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       254820                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       254820                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.476638                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.476638                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.476638                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.476638                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13829.256445                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13829.256445                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13829.256445                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13829.256445                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        37082                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        37082                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       121457                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       121457                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       121457                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       121457                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       121457                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       121457                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1312360500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1312360500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1312360500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1312360500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.476638                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.476638                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.476638                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.476638                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10805.145031                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10805.145031                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10805.145031                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10805.145031                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1670972                       # number of replacements
system.cpu.dcache.tagsinuse                511.998179                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19056575                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1671484                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.400992                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               34328000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.998179                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10967822                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10967822                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8085914                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8085914                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19053736                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19053736                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19053736                       # number of overall hits
system.cpu.dcache.overall_hits::total        19053736                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2407391                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2407391                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       317109                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       317109                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2724500                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2724500                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2724500                       # number of overall misses
system.cpu.dcache.overall_misses::total       2724500                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  35545734500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  35545734500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10083377990                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10083377990                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45629112490                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45629112490                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45629112490                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45629112490                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13375213                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13375213                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8403023                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8403023                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21778236                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21778236                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21778236                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21778236                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.179989                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.179989                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037737                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037737                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.125102                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.125102                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.125102                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.125102                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.251885                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.251885                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31797.829737                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31797.829737                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16747.701409                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16747.701409                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16747.701409                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16747.701409                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     19144990                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              3356                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  5704.705006                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1570390                       # number of writebacks
system.cpu.dcache.writebacks::total           1570390                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1028077                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1028077                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22422                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        22422                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1050499                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1050499                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1050499                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1050499                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1379314                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1379314                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294687                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       294687                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1674001                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1674001                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1674001                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1674001                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17753874500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17753874500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8876538990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8876538990                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26630413490                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26630413490                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26630413490                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26630413490                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208379000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208379000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1393915000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1393915000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86602294000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  86602294000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103125                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103125                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035069                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035069                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076866                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076866                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076866                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076866                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.524903                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.524903                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30121.922548                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30121.922548                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15908.242283                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15908.242283                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15908.242283                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15908.242283                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------