path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.133763                       # Number of seconds simulated
sim_ticks                                5133762710000                       # Number of ticks simulated
final_tick                               5133762710000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 156198                       # Simulator instruction rate (inst/s)
host_op_rate                                   308758                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1966557914                       # Simulator tick rate (ticks/s)
host_mem_usage                                 728732                       # Number of bytes of host memory used
host_seconds                                  2610.53                       # Real time elapsed on the host
sim_insts                                   407759186                       # Number of instructions simulated
sim_ops                                     806023868                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2444032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1025408                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10767936                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14241664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1025408                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1025408                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9508160                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9508160                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38188                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16022                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168249                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222526                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148565                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148565                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       476070                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            773                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               199738                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2097474                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2774118                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          199738                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             199738                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1852084                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1852084                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1852084                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       476070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           773                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              199738                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2097474                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4626202                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222526                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       148565                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      222526                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     148565                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                     14241664                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9508160                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14241664                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9508160                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       75                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               1733                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14338                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13735                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 14393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 13573                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13866                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13628                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13175                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 13794                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13878                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13620                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13949                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                13975                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                14441                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                14348                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                14346                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                13392                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9773                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  9207                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  9622                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  9014                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  9405                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  9183                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8703                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  9254                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  9156                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8973                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 9367                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 9240                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 9684                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 9527                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 9658                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8799                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           5                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5133762656000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  222526                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 148565                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    174531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21417                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7486                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2970                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2509                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2070                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1259                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1043                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       993                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      934                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      896                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      849                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      913                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      939                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      911                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      711                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      498                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      146                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5408                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6454                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        6                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        62801                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      377.966975                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     153.936826                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1272.632195                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          27908     44.44%     44.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         9784     15.58%     60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         5938      9.46%     69.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         3957      6.30%     75.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         2545      4.05%     79.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         2018      3.21%     83.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1524      2.43%     85.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515         1187      1.89%     87.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579         1022      1.63%     88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          897      1.43%     90.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          594      0.95%     91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          559      0.89%     92.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          423      0.67%     92.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          383      0.61%     93.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          375      0.60%     94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          421      0.67%     94.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          292      0.46%     95.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          205      0.33%     95.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          157      0.25%     95.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          163      0.26%     96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          146      0.23%     96.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          144      0.23%     96.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          476      0.76%     97.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          183      0.29%     97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603          124      0.20%     97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           88      0.14%     97.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           60      0.10%     98.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           51      0.08%     98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           42      0.07%     98.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           29      0.05%     98.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           32      0.05%     98.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           30      0.05%     98.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           20      0.03%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           17      0.03%     98.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           11      0.02%     98.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           16      0.03%     98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371           17      0.03%     98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435           10      0.02%     98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499            8      0.01%     98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563           13      0.02%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            7      0.01%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            4      0.01%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            8      0.01%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            3      0.00%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            3      0.00%     98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947            6      0.01%     98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            8      0.01%     98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            6      0.01%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139            6      0.01%     98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            8      0.01%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267            4      0.01%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331            6      0.01%     98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            8      0.01%     98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           10      0.02%     98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            7      0.01%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            4      0.01%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            2      0.00%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715            3      0.00%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779            8      0.01%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843            3      0.00%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            1      0.00%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971            5      0.01%     98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035            5      0.01%     98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           27      0.04%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163            6      0.01%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227            3      0.00%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291            1      0.00%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            3      0.00%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419            4      0.01%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483            2      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            3      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611            2      0.00%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            1      0.00%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739            3      0.00%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803            2      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867            1      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            2      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995            3      0.00%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123            8      0.01%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187            1      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251            3      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891            3      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955            1      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019            3      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083            1      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147            1      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211            1      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275            1      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403            2      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467            2      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531            1      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            1      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659            2      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            6      0.01%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            1      0.00%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915            4      0.01%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979            3      0.00%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            2      0.00%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107            1      0.00%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171            4      0.01%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            2      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            3      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7491            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            3      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875            4      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            2      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            1      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067            4      0.01%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195          337      0.54%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259            2      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8707            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899            2      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8963            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            2      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539           10      0.02%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9987            3      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10179            2      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10304-10307            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10627            3      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11011            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11587            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11712-11715            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12227            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12480-12483            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12739            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12995            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13187            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14083            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            3      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467            2      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14528-14531            1      0.00%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595            2      0.00%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659            3      0.00%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723            1      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            3      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915           33      0.05%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979            9      0.01%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043           11      0.02%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107           12      0.02%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            2      0.00%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            9      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299            5      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363            8      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491            6      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555            4      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619            5      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683            3      0.00%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            7      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811            6      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875            3      0.00%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939            3      0.00%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003            3      0.00%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067           10      0.02%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131            5      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195           10      0.02%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259            6      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323           10      0.02%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387           63      0.10%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            4      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643            2      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16960-16963            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17155            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17859            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18371            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          62801                       # Bytes accessed per row activation
system.physmem.totQLat                     4020206249                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                8301079999                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1112255000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3168618750                       # Total cycles spent in bank access
system.physmem.avgQLat                       18072.32                       # Average queueing delay per request
system.physmem.avgBankLat                    14244.12                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  37316.44                       # Average memory access latency
system.physmem.avgRdBW                           2.77                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.77                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.85                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        13.16                       # Average write queue length over time
system.physmem.readRowHits                     198897                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109310                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.41                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.58                       # Row buffer hit rate for writes
system.physmem.avgGap                     13834241.89                       # Average gap between requests
system.membus.throughput                      5102506                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662304                       # Transaction distribution
system.membus.trans_dist::ReadResp             662304                       # Transaction distribution
system.membus.trans_dist::WriteReq              13698                       # Transaction distribution
system.membus.trans_dist::WriteResp             13698                       # Transaction distribution
system.membus.trans_dist::Writeback            148565                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2229                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1751                       # Transaction distribution
system.membus.trans_dist::ReadExReq            179560                       # Transaction distribution
system.membus.trans_dist::ReadExResp           179558                       # Transaction distribution
system.membus.trans_dist::MessageReq             1642                       # Transaction distribution
system.membus.trans_dist::MessageResp            1642                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3284                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3284                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       470782                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775072                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475204                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721058                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       132484                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1856826                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241674                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550141                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18319104                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20110919                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5430720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5430720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25548207                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25548207                       # Total data (bytes)
system.membus.snoop_data_through_bus           646848                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250293000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583289000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3284000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1608355497                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1642000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3156883661                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429399995                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47574                       # number of replacements
system.iocache.tags.tagsinuse                0.103958                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992794933000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103958                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006497                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006497                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47629                       # number of overall misses
system.iocache.overall_misses::total            47629                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151796185                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    151796185                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10322328602                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10322328602                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10474124787                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10474124787                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10474124787                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10474124787                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47629                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47629                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166992.502750                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 166992.502750                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 220940.252611                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 220940.252611                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 219910.659199                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 219910.659199                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 219910.659199                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 219910.659199                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        148616                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                13635                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.899597                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47629                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47629                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47629                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104494685                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    104494685                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7891444112                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7891444112                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7995938797                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7995938797                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7995938797                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7995938797                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114955.649065                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114955.649065                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 168909.334589                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 168909.334589                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 167879.627895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 167879.627895                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 167879.627895                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        638140                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225493                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225493                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57527                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57527                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1642                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1642                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        26980                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       470782                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3284                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3284                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569324                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13490                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241674                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276058                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276058                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3920600                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20182000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424430792                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           459975000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53423005                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu.branchPred.lookups                85618831                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85618831                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            881906                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79126559                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77540225                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.995194                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1441540                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180626                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        453839632                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25514423                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422776164                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85618831                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78981765                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162666633                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 3997481                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     100403                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               71304729                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                44393                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         94570                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          219                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8483452                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                380361                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2201                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          262796476                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.177336                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.411374                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                100544783     38.26%     38.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1535684      0.58%     38.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71830288     27.33%     66.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   894888      0.34%     66.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1570094      0.60%     67.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2394528      0.91%     68.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1014297      0.39%     68.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1322217      0.50%     68.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81689697     31.08%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            262796476                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.188654                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.931554                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29415381                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              68460720                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158509709                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3339560                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3071106                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832655242                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   935                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3071106                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32114015                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                43120028                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12611794                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158799152                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13080381                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829727330                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 21673                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6047730                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               5146675                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             9377                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           991375726                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1800594508                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1800594068                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               440                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963942859                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27432865                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             453030                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         459006                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29568179                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16736842                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9827220                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1098890                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           921986                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  824947174                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1184809                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 820992991                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            145624                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19292542                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     29357019                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         130694                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     262796476                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.124064                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.400943                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            76438982     29.09%     29.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15751400      5.99%     35.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10538627      4.01%     39.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7358771      2.80%     41.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75737390     28.82%     70.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3750331      1.43%     72.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72306613     27.51%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              767765      0.29%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              146597      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       262796476                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  351017     33.38%     33.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      1      0.00%     33.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     348      0.03%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.41% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 547344     52.04%     85.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                152992     14.55%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            308184      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793508376     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149615      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124401      0.02%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17677574      2.15%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9224841      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              820992991                       # Type of FU issued
system.cpu.iq.rate                           1.808994                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1051702                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001281                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1906088677                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         845434927                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    817071068                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 189                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                196                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           56                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821736420                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      89                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1694381                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2750139                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        17720                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12102                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1408836                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1931381                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12080                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3071106                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                31257120                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2152669                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826131983                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            242676                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16736842                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9827220                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             690491                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1620064                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 13028                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12102                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         497258                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506632                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1003890                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819577252                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17369785                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1415738                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26409608                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83098710                       # Number of branches executed
system.cpu.iew.exec_stores                    9039823                       # Number of stores executed
system.cpu.iew.exec_rate                     1.805874                       # Inst execution rate
system.cpu.iew.wb_sent                      819172462                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     817071124                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638600161                       # num instructions producing a value
system.cpu.iew.wb_consumers                1043929120                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.800352                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611728                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19998846                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054115                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            892238                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    259725370                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.103370                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863932                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     88203628     33.96%     33.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11848657      4.56%     38.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3832219      1.48%     40.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74739253     28.78%     68.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2381920      0.92%     69.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1474779      0.57%     70.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       859132      0.33%     70.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70849609     27.28%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5536173      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    259725370                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407759186                       # Number of instructions committed
system.cpu.commit.committedOps              806023868                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22405086                       # Number of memory references committed
system.cpu.commit.loads                      13986702                       # Number of loads committed
system.cpu.commit.membars                      474409                       # Number of memory barriers committed
system.cpu.commit.branches                   82159690                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735008844                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1154896                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5536173                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1080133651                       # The number of ROB reads
system.cpu.rob.rob_writes                  1655131261                       # The number of ROB writes
system.cpu.timesIdled                         1259877                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       191043156                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9813691352                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407759186                       # Number of Instructions Simulated
system.cpu.committedOps                     806023868                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407759186                       # Number of Instructions Simulated
system.cpu.cpi                               1.113009                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.113009                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.898465                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.898465                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1504423855                       # number of integer regfile reads
system.cpu.int_regfile_writes               975340027                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        56                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264091330                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402284                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53596956                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3010019                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3009469                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1583020                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2243                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2243                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       334736                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       288025                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1906694                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6122854                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        16266                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       154977                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8200791                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61010496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207591623                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       510912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5512832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      274625863                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         274602311                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       551744                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4037956918                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       552000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1434043234                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3142652791                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      12430241                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     103328135                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            952820                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.973198                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7477461                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            953332                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.843502                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147437101250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.973198                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996041                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996041                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7477461                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7477461                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7477461                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7477461                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7477461                       # number of overall hits
system.cpu.icache.overall_hits::total         7477461                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1005989                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1005989                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1005989                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1005989                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1005989                       # number of overall misses
system.cpu.icache.overall_misses::total       1005989                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14232079935                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14232079935                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14232079935                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14232079935                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14232079935                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14232079935                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8483450                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8483450                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8483450                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8483450                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8483450                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8483450                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118583                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.118583                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.118583                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.118583                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.118583                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.118583                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14147.351447                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14147.351447                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14147.351447                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14147.351447                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14147.351447                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14147.351447                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6191                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               174                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    35.580460                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        52584                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        52584                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        52584                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        52584                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        52584                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        52584                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       953405                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       953405                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       953405                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       953405                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       953405                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       953405                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11737352011                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11737352011                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11737352011                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11737352011                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11737352011                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11737352011                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112384                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112384                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112384                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.112384                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112384                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.112384                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12310.982228                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12310.982228                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12310.982228                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12310.982228                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12310.982228                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12310.982228                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         7402                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.006857                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        21909                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         7416                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.954288                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104253177000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.006857                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375429                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.375429                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        21911                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        21911                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        21913                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        21913                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        21913                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        21913                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         8283                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         8283                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         8283                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         8283                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         8283                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         8283                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     92582993                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total     92582993                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     92582993                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total     92582993                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     92582993                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total     92582993                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30194                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        30194                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30196                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        30196                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30196                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        30196                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.274326                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.274326                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.274308                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.274308                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.274308                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.274308                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11177.471085                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11177.471085                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11177.471085                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11177.471085                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11177.471085                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11177.471085                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1499                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1499                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         8283                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         8283                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         8283                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         8283                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         8283                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         8283                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     76005511                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     76005511                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     76005511                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     76005511                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     76005511                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     76005511                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.274326                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.274326                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.274308                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.274308                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.274308                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.274308                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9176.084873                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9176.084873                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9176.084873                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9176.084873                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9176.084873                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9176.084873                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        67804                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    13.886481                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        92487                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        67819                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.363733                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101460528500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.886481                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.867905                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.867905                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92498                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92498                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92498                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92498                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92498                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92498                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68839                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        68839                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68839                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        68839                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68839                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        68839                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    851625712                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    851625712                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    851625712                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    851625712                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    851625712                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    851625712                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       161337                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       161337                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       161337                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       161337                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       161337                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       161337                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.426678                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.426678                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.426678                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.426678                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.426678                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.426678                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12371.267915                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12371.267915                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12371.267915                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12371.267915                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12371.267915                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12371.267915                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        23017                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        23017                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68839                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68839                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68839                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        68839                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68839                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        68839                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    713808442                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    713808442                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    713808442                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    713808442                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    713808442                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    713808442                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.426678                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.426678                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.426678                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.426678                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.426678                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.426678                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10369.244789                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10369.244789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10369.244789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10369.244789                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1656828                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.997492                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18985847                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1657340                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.455614                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          38296250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.997492                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10890330                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10890330                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8092849                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8092849                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      18983179                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18983179                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18983179                       # number of overall hits
system.cpu.dcache.overall_hits::total        18983179                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2236067                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2236067                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       316060                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       316060                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2552127                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2552127                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2552127                       # number of overall misses
system.cpu.dcache.overall_misses::total       2552127                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33180539725                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33180539725                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12164482246                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12164482246                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45345021971                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45345021971                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45345021971                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45345021971                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13126397                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13126397                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8408909                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8408909                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21535306                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21535306                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21535306                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21535306                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170349                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170349                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037586                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037586                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118509                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118509                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118509                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118509                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.794958                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.794958                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38487.889154                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38487.889154                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.541337                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17767.541337                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.541337                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17767.541337                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       401774                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42434                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.468209                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1558504                       # number of writebacks
system.cpu.dcache.writebacks::total           1558504                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       866614                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       866614                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25901                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25901                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       892515                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       892515                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       892515                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       892515                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1369453                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1369453                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290159                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290159                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1659612                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1659612                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1659612                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1659612                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17930492982                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17930492982                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11266233199                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11266233199                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29196726181                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29196726181                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29196726181                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29196726181                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97349090500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97349090500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2521949000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2521949000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99871039500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99871039500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104328                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104328                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034506                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034506                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077065                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077065                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077065                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077065                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13093.178796                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13093.178796                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38827.791656                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38827.791656                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.501248                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.501248                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.501248                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.501248                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111287                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64824.187334                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3785036                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           175649                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.548862                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50594.922506                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     9.467907                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.125935                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3127.998862                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11091.672124                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.772017                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000144                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047729                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.169245                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989139                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        63059                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         6479                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       937263                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1332664                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2339465                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1583020                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1583020                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          302                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          302                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154882                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154882                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        63059                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         6479                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       937263                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1487546                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2494347                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        63059                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         6479                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       937263                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1487546                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2494347                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           62                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16026                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36078                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52171                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1463                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1463                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133126                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133126                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           62                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16026                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169204                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185297                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           62                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16026                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169204                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185297                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6809750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       417750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1389559236                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3040297215                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4437083951                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17341812                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17341812                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9382369904                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9382369904                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6809750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       417750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1389559236                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12422667119                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13819453855                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6809750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       417750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1389559236                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12422667119                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13819453855                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        63121                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         6484                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       953289                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1368742                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2391636                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1583020                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1583020                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1765                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1765                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288008                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288008                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        63121                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         6484                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       953289                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1656750                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2679644                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        63121                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         6484                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       953289                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1656750                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2679644                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000771                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016811                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026359                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021814                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.828895                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.828895                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.462230                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.462230                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000771                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016811                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102130                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.069150                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000982                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000771                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016811                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102130                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.069150                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109834.677419                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        83550                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86706.554100                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84270.115167                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85048.857622                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11853.596719                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11853.596719                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70477.366585                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70477.366585                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109834.677419                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83550                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86706.554100                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73418.282777                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74580.019401                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109834.677419                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83550                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86706.554100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73418.282777                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74580.019401                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       101898                       # number of writebacks
system.cpu.l2cache.writebacks::total           101898                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           62                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16022                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36077                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52166                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1463                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1463                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133126                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133126                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16022                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169203                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185292                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           62                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16022                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169203                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185292                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      6018750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       353750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1186972764                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2585018535                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3778363799                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15641444                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15641444                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7710305096                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7710305096                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      6018750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       353750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1186972764                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10295323631                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11488668895                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      6018750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       353750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1186972764                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10295323631                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11488668895                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89236799000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89236799000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2357013000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2357013000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91593812000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91593812000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000771                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016807                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026358                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021812                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.828895                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.828895                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.462230                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.462230                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000771                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016807                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102129                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.069148                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000982                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000771                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016807                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102129                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.069148                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74083.932343                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71652.813011                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72429.624641                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.349282                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.349282                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57917.349699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57917.349699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74083.932343                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60845.987548                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62003.048675                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 97076.612903                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74083.932343                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60845.987548                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62003.048675                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------