path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.149802                       # Number of seconds simulated
sim_ticks                                5149801602000                       # Number of ticks simulated
final_tick                               5149801602000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 149544                       # Simulator instruction rate (inst/s)
host_op_rate                                   295611                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1888705545                       # Simulator tick rate (ticks/s)
host_mem_usage                                 733444                       # Number of bytes of host memory used
host_seconds                                  2726.63                       # Real time elapsed on the host
sim_insts                                   407752265                       # Number of instructions simulated
sim_ops                                     806021401                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2464448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1029696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10712000                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14210368                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1029696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1029696                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9492864                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9492864                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38507                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16089                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167375                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222037                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148326                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148326                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       478552                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            758                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               199949                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2080080                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2759401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          199949                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             199949                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1843346                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1843346                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1843346                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       478552                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           758                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              199949                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2080080                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4602747                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222037                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                       148326                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      222037                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                     148326                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                     14210368                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9492864                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14210368                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9492864                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      119                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               1678                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14222                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 14028                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 14693                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 13767                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13958                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13755                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13651                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 13963                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13415                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13462                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13512                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                13712                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                14980                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                14150                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13362                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                13288                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9612                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  9534                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  9830                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  9200                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  9484                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  9208                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  9093                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  9396                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8748                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8829                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 9077                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 9138                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                10300                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 9366                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8795                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 8716                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           4                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5149801548000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  222037                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 148326                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    173642                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     21423                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7433                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1084                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1011                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      947                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      856                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      918                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      965                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      955                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      745                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      522                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      251                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5426                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5696                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6386                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6435                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6449                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1023                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        6                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        62488                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      379.140187                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     154.041653                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev    1280.875932                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67          27817     44.52%     44.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131         9622     15.40%     59.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195         5951      9.52%     69.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259         3940      6.31%     75.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323         2520      4.03%     79.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387         1986      3.18%     82.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451         1542      2.47%     85.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515         1215      1.94%     87.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579         1005      1.61%     88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643          910      1.46%     90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707          598      0.96%     91.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771          543      0.87%     92.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835          367      0.59%     92.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899          364      0.58%     93.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963          356      0.57%     94.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027          454      0.73%     94.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091          284      0.45%     95.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155          192      0.31%     95.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219          180      0.29%     95.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283          146      0.23%     96.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347          174      0.28%     96.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411          177      0.28%     96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475          484      0.77%     97.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539          176      0.28%     97.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603          118      0.19%     97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667           94      0.15%     97.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731           80      0.13%     98.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795           58      0.09%     98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859           28      0.04%     98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923           25      0.04%     98.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987           31      0.05%     98.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051           34      0.05%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115           13      0.02%     98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179           15      0.02%     98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243           10      0.02%     98.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307           19      0.03%     98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371           17      0.03%     98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435            8      0.01%     98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499           10      0.02%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563            8      0.01%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627            4      0.01%     98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691            3      0.00%     98.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755            9      0.01%     98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819            5      0.01%     98.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883            9      0.01%     98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947            4      0.01%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011            4      0.01%     98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075            3      0.00%     98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139            7      0.01%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203            2      0.00%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267            3      0.00%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331            3      0.00%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395            5      0.01%     98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459           14      0.02%     98.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523            3      0.00%     98.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587            5      0.01%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651            4      0.01%     98.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715            6      0.01%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779           11      0.02%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843            3      0.00%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907            3      0.00%     98.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971            5      0.01%     98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035            1      0.00%     98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099           21      0.03%     98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163            7      0.01%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291            1      0.00%     98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355            4      0.01%     98.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419            6      0.01%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483            3      0.00%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547            5      0.01%     98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675            4      0.01%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803            2      0.00%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867            1      0.00%     98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931            3      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995            1      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059            2      0.00%     98.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123            4      0.01%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187            2      0.00%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251            3      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5315            1      0.00%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379            4      0.01%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635            2      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827            1      0.00%     98.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955            2      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019            2      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083            2      0.00%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147            2      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275            1      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339            2      0.00%     98.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403            2      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467            1      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595            1      0.00%     98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723            6      0.01%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851            2      0.00%     98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915            7      0.01%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979            1      0.00%     98.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043            2      0.00%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107            2      0.00%     98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171            4      0.01%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7299            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427            1      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555            2      0.00%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619            2      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7683            2      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747            1      0.00%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875            2      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939            1      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003            2      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067            2      0.00%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131            1      0.00%     98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195          339      0.54%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9344-9347            2      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9411            1      0.00%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539            8      0.01%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9600-9603            1      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667            3      0.00%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731            2      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051            4      0.01%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115            1      0.00%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10176-10179            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10563            2      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10624-10627            1      0.00%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10688-10691            1      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10755            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11075            1      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203            2      0.00%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11331            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11392-11395            2      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11456-11459            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12099            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12227            1      0.00%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12352-12355            2      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12867            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379            1      0.00%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13504-13507            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13760-13763            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13891            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13955            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147            2      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14464-14467            3      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915           28      0.04%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979           15      0.02%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043           10      0.02%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107            9      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171            7      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235            4      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299            5      0.01%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363            3      0.00%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427            5      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491            6      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555            3      0.00%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619            4      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683            6      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747            2      0.00%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811            6      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875            7      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939            6      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003            4      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067            8      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131            6      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195           10      0.02%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259           12      0.02%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323           11      0.02%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387           62      0.10%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16448-16451            2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16512-16515            3      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16576-16579            3      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16643            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16704-16707            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16832-16835            1      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17024-17027            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17088-17091            1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17219            2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          62488                       # Bytes accessed per row activation
system.physmem.totQLat                     4021160000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                8281507500                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1109590000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3150757500                       # Total cycles spent in bank access
system.physmem.avgQLat                       18120.03                       # Average queueing delay per request
system.physmem.avgBankLat                    14197.85                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  37317.87                       # Average memory access latency
system.physmem.avgRdBW                           2.76                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.84                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.76                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.84                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         9.63                       # Average write queue length over time
system.physmem.readRowHits                     198603                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109131                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   89.49                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.58                       # Row buffer hit rate for writes
system.physmem.avgGap                     13904740.88                       # Average gap between requests
system.membus.throughput                      5073674                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662109                       # Transaction distribution
system.membus.trans_dist::ReadResp             662107                       # Transaction distribution
system.membus.trans_dist::WriteReq              13770                       # Transaction distribution
system.membus.trans_dist::WriteResp             13770                       # Transaction distribution
system.membus.trans_dist::Writeback            148326                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2172                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1696                       # Transaction distribution
system.membus.trans_dist::ReadExReq            179020                       # Transaction distribution
system.membus.trans_dist::ReadExResp           179014                       # Transaction distribution
system.membus.trans_dist::MessageReq             1646                       # Transaction distribution
system.membus.trans_dist::MessageResp            1646                       # Transaction distribution
system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3292                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3292                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471038                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775088                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       473242                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1719372                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132805                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       132805                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1855469                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6584                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241802                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550173                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18252032                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20044007                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5451200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5451200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25501791                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25501791                       # Total data (bytes)
system.membus.snoop_data_through_bus           626624                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250581000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583304500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3292000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1605050249                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1646000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3149132971                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429400997                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47576                       # number of replacements
system.iocache.tags.tagsinuse                0.153339                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47592                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992838664000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.153339                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.009584                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.009584                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47630                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47630                       # number of overall misses
system.iocache.overall_misses::total            47630                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    152977935                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    152977935                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10361858110                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10361858110                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10514836045                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10514836045                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10514836045                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10514836045                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47630                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47630                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47630                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47630                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 168107.620879                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 221786.346533                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 220760.781965                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 220760.781965                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        148180                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                13622                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.877991                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46668                       # number of writebacks
system.iocache.writebacks::total                46668                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47630                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47630                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47630                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47630                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    105623935                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    105623935                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7930990116                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7930990116                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   8036614051                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   8036614051                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   8036614051                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   8036614051                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 168730.087151                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 168730.087151                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        636182                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225558                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225558                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1646                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1646                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3292                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3292                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569590                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6584                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6584                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276210                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276210                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3927144                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           424444048                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460167000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53407003                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1646000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu.branchPred.lookups                85588006                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85588006                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            877454                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79215990                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77530840                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.872715                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1437704                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180381                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        453669464                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25482716                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422686689                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85588006                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78968544                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162633276                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 3972302                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     106554                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               71193509                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                45334                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         89294                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          278                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8469801                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                382535                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2385                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          262601517                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.178991                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.411463                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                100383881     38.23%     38.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1533037      0.58%     38.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71821115     27.35%     66.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   895642      0.34%     66.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1564995      0.60%     67.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2390879      0.91%     68.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1017520      0.39%     68.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1329446      0.51%     68.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81665002     31.10%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            262601517                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.188657                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.931706                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29392698                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              68340203                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158479192                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3338868                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3050556                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832478930                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   959                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3050556                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32088006                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                43079490                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12529275                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158770454                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13083736                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829577701                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 21771                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6064622                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               5141489                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           991205554                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1800191267                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1106790785                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               123                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963930499                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27275048                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             452761                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         458610                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29575764                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16714812                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9817459                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1139197                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           962008                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  824812969                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1184552                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 820895267                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            151456                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19155682                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     29185416                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         129934                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     262601517                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.126011                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.400353                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            76255592     29.04%     29.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15761044      6.00%     35.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10531368      4.01%     39.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7369443      2.81%     41.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75730840     28.84%     70.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3739599      1.42%     72.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72299562     27.53%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              768121      0.29%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              145948      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       262601517                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  345012     32.94%     32.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    241      0.02%     32.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     974      0.09%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 547730     52.30%     85.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                153356     14.64%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            307746      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793434579     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149572      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124688      0.02%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.73% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17663300      2.15%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9215382      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              820895267                       # Type of FU issued
system.cpu.iq.rate                           1.809457                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1047313                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001276                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905699959                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         845163637                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    816985295                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 199                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                210                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           54                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821634741                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      93                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1691465                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2728859                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        17017                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11975                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1400009                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1931860                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12243                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3050556                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                31208951                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2150350                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           825997521                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            243405                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16714812                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9817459                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             689575                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1619766                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 13837                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11975                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         493977                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506066                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1000043                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819488058                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17361171                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1407208                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26390625                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83079645                       # Number of branches executed
system.cpu.iew.exec_stores                    9029454                       # Number of stores executed
system.cpu.iew.exec_rate                     1.806355                       # Inst execution rate
system.cpu.iew.wb_sent                      819086222                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     816985349                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638544896                       # num instructions producing a value
system.cpu.iew.wb_consumers                1043866074                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.800838                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611712                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19867682                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054616                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            887449                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    259550960                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.105446                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863698                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     88027122     33.92%     33.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11847553      4.56%     38.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3827434      1.47%     39.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74752127     28.80%     68.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2379438      0.92%     69.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1475953      0.57%     70.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       857436      0.33%     70.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70850710     27.30%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5533187      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    259550960                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407752265                       # Number of instructions committed
system.cpu.commit.committedOps              806021401                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22403400                       # Number of memory references committed
system.cpu.commit.loads                      13985950                       # Number of loads committed
system.cpu.commit.membars                      474657                       # Number of memory barriers committed
system.cpu.commit.branches                   82156128                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 734862948                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155170                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5533187                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1079828496                       # The number of ROB reads
system.cpu.rob.rob_writes                  1654843441                       # The number of ROB writes
system.cpu.timesIdled                         1258915                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       191067947                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9845938983                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407752265                       # Number of Instructions Simulated
system.cpu.committedOps                     806021401                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407752265                       # Number of Instructions Simulated
system.cpu.cpi                               1.112611                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.112611                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.898787                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.898787                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1088694796                       # number of integer regfile reads
system.cpu.int_regfile_writes               653771353                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        54                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415601025                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321483560                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264032145                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402444                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53392020                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3013693                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3013151                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13770                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13770                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1577044                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2235                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2235                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       334035                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1908198                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6121437                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18680                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       151603                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8199918                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61058944                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207524391                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       566848                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5217216                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      274367399                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         274343271                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       615040                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4030545417                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       565500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1435258580                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3141587747                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      14741736                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     105191645                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            953576                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.036469                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7463561                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            954088                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.822718                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147479259250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.036469                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996165                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996165                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7463561                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7463561                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7463561                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7463561                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7463561                       # number of overall hits
system.cpu.icache.overall_hits::total         7463561                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1006237                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1006237                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1006237                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1006237                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1006237                       # number of overall misses
system.cpu.icache.overall_misses::total       1006237                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14239259264                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14239259264                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14239259264                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14239259264                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14239259264                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14239259264                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8469798                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8469798                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8469798                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8469798                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8469798                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8469798                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118803                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.118803                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.118803                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.118803                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.118803                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.118803                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14150.999480                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14150.999480                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         7035                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          587                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               207                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    33.985507                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          587                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        52085                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        52085                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        52085                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        52085                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        52085                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        52085                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       954152                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       954152                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       954152                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       954152                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       954152                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       954152                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11748055164                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11748055164                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11748055164                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11748055164                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11748055164                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11748055164                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112653                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112653                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112653                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.112653                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112653                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.112653                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12312.561483                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12312.561483                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12312.561483                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12312.561483                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12312.561483                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12312.561483                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         8937                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.031585                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        20273                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         8949                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.265393                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.031585                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376974                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376974                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20288                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        20288                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20290                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        20290                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20290                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        20290                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9823                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         9823                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9823                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         9823                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9823                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         9823                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    106143491                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    106143491                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    106143491                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    106143491                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    106143491                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    106143491                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30111                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        30111                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30113                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        30113                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30113                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        30113                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.326226                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.326226                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.326205                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.326205                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.326205                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.326205                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10805.608368                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10805.608368                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10805.608368                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10805.608368                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10805.608368                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10805.608368                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1536                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1536                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9823                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9823                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9823                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         9823                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9823                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         9823                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     86483019                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     86483019                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     86483019                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     86483019                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     86483019                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     86483019                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.326226                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.326226                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.326205                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.326205                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.326205                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.326205                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8804.135091                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8804.135091                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8804.135091                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8804.135091                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8804.135091                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8804.135091                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        69051                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    14.904441                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        92410                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        69067                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.337976                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.904441                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.931528                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.931528                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92410                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92410                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92410                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92410                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92410                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92410                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        70084                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        70084                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        70084                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        70084                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        70084                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        70084                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    863900211                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    863900211                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    863900211                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    863900211                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    863900211                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    863900211                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       162494                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       162494                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       162494                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       162494                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       162494                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       162494                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.431302                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.431302                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.431302                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.431302                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.431302                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.431302                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        17433                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        17433                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        70084                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        70084                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        70084                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        70084                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        70084                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        70084                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    723600921                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    723600921                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    723600921                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    723600921                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    723600921                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    723600921                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.431302                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.431302                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.431302                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.431302                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.431302                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.431302                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1656223                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995363                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18981681                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1656735                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.457283                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          38296250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995363                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999991                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10886449                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10886449                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8092566                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8092566                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      18979015                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18979015                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18979015                       # number of overall hits
system.cpu.dcache.overall_hits::total        18979015                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2233485                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2233485                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       315362                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       315362                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2548847                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2548847                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2548847                       # number of overall misses
system.cpu.dcache.overall_misses::total       2548847                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33146878091                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33146878091                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12110851955                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12110851955                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45257730046                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45257730046                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45257730046                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45257730046                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13119934                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13119934                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8407928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8407928                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21527862                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21527862                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21527862                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21527862                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170236                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170236                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037508                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037508                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118398                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118398                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118398                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118398                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17756.157998                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17756.157998                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       397029                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42211                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.405818                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1558075                       # number of writebacks
system.cpu.dcache.writebacks::total           1558075                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       863964                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       863964                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25903                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25903                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       889867                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       889867                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       889867                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       889867                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1369521                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1369521                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289459                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289459                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1658980                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1658980                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1658980                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1658980                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17890697467                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17890697467                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11213904776                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11213904776                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29104602243                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29104602243                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29104602243                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29104602243                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363389500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363389500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537212500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537212500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99900602000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99900602000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104385                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104385                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034427                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034427                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077062                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077062                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077062                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077062                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13063.470708                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13063.470708                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38740.908992                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38740.908992                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17543.672765                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17543.672765                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17543.672765                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17543.672765                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111030                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64826.472459                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3778684                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           175194                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.568570                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50681.739726                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.389473                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.126360                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3154.839076                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10976.377823                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.773342                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000204                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048139                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.167486                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989173                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64025                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7316                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       937955                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333061                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2342357                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1577044                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1577044                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          316                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          316                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154757                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154757                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64025                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         7316                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       937955                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1487818                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2497114                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64025                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         7316                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       937955                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1487818                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2497114                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           61                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16091                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35754                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        51911                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1443                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1443                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132547                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132547                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16091                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168301                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        184458                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           61                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16091                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168301                       # number of overall misses
system.cpu.l2cache.overall_misses::total       184458                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5633750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       417750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1393223986                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2996305709                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4395581195                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16716837                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     16716837                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9332768700                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9332768700                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5633750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       417750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1393223986                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12329074409                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13728349895                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5633750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       417750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1393223986                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12329074409                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13728349895                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64086                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7321                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       954046                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1368815                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2394268                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1577044                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1577044                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1759                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1759                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287304                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287304                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64086                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         7321                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       954046                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1656119                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2681572                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64086                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         7321                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       954046                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1656119                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2681572                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000952                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000683                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016866                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026120                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021681                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820352                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820352                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.461348                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.461348                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000952                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000683                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016866                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101624                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068787                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000952                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000683                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016866                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101624                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068787                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92356.557377                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        83550                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86584.052327                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83803.370504                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84675.332685                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11584.779626                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11584.779626                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70411.014206                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70411.014206                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92356.557377                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83550                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86584.052327                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73256.097165                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74425.342869                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92356.557377                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83550                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86584.052327                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73256.097165                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74425.342869                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       101658                       # number of writebacks
system.cpu.l2cache.writebacks::total           101658                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16089                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35751                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        51906                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1443                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1443                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132547                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132547                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16089                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168298                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       184453                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16089                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168298                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       184453                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4857750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       353750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1189838014                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2545516291                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3740565805                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15357924                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15357924                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7668131300                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7668131300                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4857750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       353750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1189838014                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10213647591                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11408697105                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4857750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       353750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1189838014                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10213647591                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11408697105                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250267000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250267000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2371416000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2371416000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91621683000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91621683000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000952                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000683                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016864                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026118                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021679                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820352                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820352                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461348                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461348                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000952                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000683                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016864                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101622                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068785                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000952                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000683                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016864                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101622                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068785                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73953.509479                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71201.261251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72064.227739                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10643.051975                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10643.051975                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57852.167910                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57852.167910                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73953.509479                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60687.872649                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61851.512879                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        70750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------