path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.144266                       # Number of seconds simulated
sim_ticks                                5144266112000                       # Number of ticks simulated
final_tick                               5144266112000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 171088                       # Simulator instruction rate (inst/s)
host_op_rate                                   338186                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2162643270                       # Simulator tick rate (ticks/s)
host_mem_usage                                 817576                       # Number of bytes of host memory used
host_seconds                                  2378.69                       # Real time elapsed on the host
sim_insts                                   406967147                       # Number of instructions simulated
sim_ops                                     804441344                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1037760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10694784                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11765248                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1037760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1037760                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9531136                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9531136                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16215                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167106                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                183832                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148924                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148924                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            771                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               201731                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2078972                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5511                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2287061                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          201731                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             201731                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1852769                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1852769                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1852769                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           771                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              201731                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2078972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4139829                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        183832                       # Number of read requests accepted
system.physmem.writeReqs                       148924                       # Number of write requests accepted
system.physmem.readBursts                      183832                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     148924                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11753920                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11328                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9529408                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11765248                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9531136                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      177                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11604                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10712                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11807                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11944                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11505                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10649                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11472                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11273                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10779                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10837                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10616                       # Per bank write bursts
system.physmem.perBankRdBursts::11              10970                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12334                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12596                       # Per bank write bursts
system.physmem.perBankRdBursts::14              12433                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12124                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10095                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9143                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9309                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9560                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9320                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8650                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9309                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8633                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9264                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9181                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8947                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9087                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9676                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9763                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9717                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9243                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    5144265940500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  183832                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148924                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    169282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1942                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       435                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     8552                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7509                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8532                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8001                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     8626                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8882                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9922                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8766                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1369                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      261                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      207                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      139                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      151                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      125                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       75                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       71                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       57                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        72695                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      292.774799                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     175.092405                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     313.788617                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27722     38.13%     38.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17851     24.56%     62.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7685     10.57%     73.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4254      5.85%     79.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2907      4.00%     83.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2448      3.37%     86.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1364      1.88%     88.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1142      1.57%     89.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7322     10.07%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          72695                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7110                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.828551                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      569.649701                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7109     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7110                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7110                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.941913                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.730767                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       15.006357                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6192     87.09%     87.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             167      2.35%     89.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              37      0.52%     89.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              45      0.63%     90.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              23      0.32%     90.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              21      0.30%     91.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              97      1.36%     92.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.13%     92.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             166      2.33%     95.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              18      0.25%     95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               7      0.10%     95.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              16      0.23%     95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             121      1.70%     97.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.11%     97.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.06%     97.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              38      0.53%     98.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             106      1.49%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.01%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.01%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            17      0.24%     99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.01%     99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             3      0.04%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             5      0.07%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7110                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2119857534                       # Total ticks spent queuing
system.physmem.totMemAccLat                5563388784                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    918275000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11542.61                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30292.61                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.28                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.91                       # Average write queue length when enqueuing
system.physmem.readRowHits                     149881                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109975                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.85                       # Row buffer hit rate for writes
system.physmem.avgGap                     15459573.80                       # Average gap between requests
system.physmem.pageHitRate                      78.13                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  270058320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  147353250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 709527000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                479643120                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           132965716590                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2969918703000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3440488964880                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.801684                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4940650410974                       # Time in different power states
system.physmem_0.memoryStateTime::REF    171778100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31837441026                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  279515880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  152513625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 722974200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                485209440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           132979028940                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2969907025500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3440524231185                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.808539                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4940617535740                       # Time in different power states
system.physmem_1.memoryStateTime::REF    171778100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     31863205510                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86364991                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86364991                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            844127                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79785258                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77812669                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.527627                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1536742                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             177773                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        465360105                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27264808                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      426684669                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86364991                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79349411                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     433306610                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1772802                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     134530                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                64125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        192382                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           61                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          876                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8941256                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                423617                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4382                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          461849793                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.823288                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.015889                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                297255411     64.36%     64.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2121995      0.46%     64.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72014573     15.59%     80.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1541910      0.33%     80.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2093291      0.45%     81.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2283864      0.49%     81.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1472775      0.32%     82.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1848688      0.40%     82.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81217286     17.59%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            461849793                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185587                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.916891                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 22977374                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             281921600                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 147739670                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               8324748                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 886401                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              834278152                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 886401                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 26267496                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               229970737                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       14504506                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 152095213                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              38125440                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              830978624                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                455578                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12565136                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 219239                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               22179017                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           992691182                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1804301856                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1109183623                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               354                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             961933159                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 30758021                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             459775                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         462810                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  42714636                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17039027                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10018616                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1305141                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1111349                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  825753425                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1154163                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 820868911                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            214819                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22466239                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33875924                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         142660                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     461849793                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.777350                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.400586                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           278664222     60.34%     60.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13660041      2.96%     63.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9686600      2.10%     65.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7488458      1.62%     67.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            73146885     15.84%     82.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4790867      1.04%     83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72643551     15.73%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1186237      0.26%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              582932      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       461849793                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2421761     76.44%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 586525     18.51%     94.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                160044      5.05%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            284830      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             792980272     96.60%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149980      0.02%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                126454      0.02%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  89      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18050334      2.20%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9276952      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              820868911                       # Type of FU issued
system.cpu.iq.rate                           1.763943                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     3168330                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003860                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2106970311                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         849385719                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    816582122                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 452                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                530                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          164                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              823752187                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     224                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1863434                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3081685                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14588                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13991                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1596193                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2095838                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         68033                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 886401                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               206156511                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              15627383                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826907588                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            167586                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17039027                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10018616                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             684984                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 384487                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              14418162                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13991                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         476529                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       505758                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               982287                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819355250                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17680454                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1388114                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26746540                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 82995794                       # Number of branches executed
system.cpu.iew.exec_stores                    9066086                       # Number of stores executed
system.cpu.iew.exec_rate                     1.760691                       # Inst execution rate
system.cpu.iew.wb_sent                      818880550                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     816582286                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638742122                       # num instructions producing a value
system.cpu.iew.wb_consumers                1046798890                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.754732                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610186                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        22341740                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1011503                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            854574                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    458481638                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.754577                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.647842                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    288021226     62.82%     62.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11081670      2.42%     65.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3642063      0.79%     66.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74473498     16.24%     82.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2428435      0.53%     82.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1625237      0.35%     83.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1003852      0.22%     83.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70853239     15.45%     98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5352418      1.17%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    458481638                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            406967147                       # Number of instructions committed
system.cpu.commit.committedOps              804441344                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22379764                       # Number of memory references committed
system.cpu.commit.loads                      13957341                       # Number of loads committed
system.cpu.commit.membars                      448127                       # Number of memory barriers committed
system.cpu.commit.branches                   82004213                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 733419549                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155856                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171897      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        781625831     97.16%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144579      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121842      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13954756      1.73%     98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8422423      1.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         804441344                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5352418                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1279833930                       # The number of ROB reads
system.cpu.rob.rob_writes                  1656952294                       # The number of ROB writes
system.cpu.timesIdled                          286358                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3510312                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9823169535                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   406967147                       # Number of Instructions Simulated
system.cpu.committedOps                     804441344                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.143483                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.143483                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.874521                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.874521                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1088188706                       # number of integer regfile reads
system.cpu.int_regfile_writes               653573677                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       164                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 414911991                       # number of cc regfile reads
system.cpu.cc_regfile_writes                320992687                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264310319                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400396                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1655678                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.993569                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18965333                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1656190                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.451182                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.993569                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87673930                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87673930                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10821466                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10821466                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8077929                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8077929                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        63073                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         63073                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      18899395                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18899395                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18962468                       # number of overall hits
system.cpu.dcache.overall_hits::total        18962468                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1800836                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1800836                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334794                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334794                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406327                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406327                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2135630                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2135630                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2541957                       # number of overall misses
system.cpu.dcache.overall_misses::total       2541957                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  30075089000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  30075089000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21061915731                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21061915731                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  51137004731                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  51137004731                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  51137004731                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  51137004731                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12622302                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12622302                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8412723                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8412723                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       469400                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       469400                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21035025                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21035025                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21504425                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21504425                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142671                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142671                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039796                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039796                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865631                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.865631                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101527                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101527                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118206                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118206                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23944.693009                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20117.179296                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       547266                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             52094                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.505356                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1558302                       # number of writebacks
system.cpu.dcache.writebacks::total           1558302                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       835082                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       835082                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44918                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44918                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       880000                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       880000                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       880000                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       880000                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       965754                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       965754                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289876                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289876                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402839                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402839                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1255630                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1255630                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1658469                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1658469                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       573476                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       573476                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13931                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13931                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587407                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       587407                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14293741500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  14293741500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19116755234                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19116755234                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6811295000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6811295000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33410496734                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  33410496734                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40221791734                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  40221791734                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98116957000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98116957000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2783856500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2783856500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100900813500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076512                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076512                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034457                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034457                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858200                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858200                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059692                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059692                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077122                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077122                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        70584                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.821836                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       110496                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        70598                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.565143                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821836                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988865                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988865                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       435866                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       435866                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       110530                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       110530                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       110530                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       110530                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       110530                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       110530                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71602                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        71602                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71602                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        71602                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71602                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        71602                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    914983500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    914983500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    914983500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    914983500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    914983500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    914983500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       182132                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       182132                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       182132                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       182132                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       182132                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       182132                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.393132                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.393132                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.393132                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.393132                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12778.742214                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12778.742214                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12778.742214                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12778.742214                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        20861                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        20861                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71602                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71602                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71602                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        71602                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71602                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        71602                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    843381500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    843381500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    843381500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    843381500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.393132                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.393132                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.393132                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.393132                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11778.742214                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11778.742214                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11778.742214                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            975620                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.114510                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7899697                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            976132                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.092857                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      150355632500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.114510                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994364                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994364                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          137                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9917449                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9917449                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7899697                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7899697                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7899697                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7899697                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7899697                       # number of overall hits
system.cpu.icache.overall_hits::total         7899697                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1041547                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1041547                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1041547                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1041547                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1041547                       # number of overall misses
system.cpu.icache.overall_misses::total       1041547                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15667212986                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15667212986                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15667212986                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15667212986                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15667212986                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15667212986                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8941244                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8941244                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8941244                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8941244                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8941244                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8941244                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116488                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116488                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116488                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116488                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116488                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116488                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15042.252521                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15042.252521                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15042.252521                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15042.252521                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15042.252521                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15042.252521                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        12938                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          311                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               471                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    27.469214                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    77.750000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks       975620                       # number of writebacks
system.cpu.icache.writebacks::total            975620                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65342                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        65342                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        65342                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        65342                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        65342                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        65342                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       976205                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       976205                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       976205                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       976205                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       976205                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       976205                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13808957489                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13808957489                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13808957489                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13808957489                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13808957489                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13808957489                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109180                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.109180                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109180                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.109180                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14145.550872                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14145.550872                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14145.550872                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14145.550872                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        12936                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.024979                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        24186                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        12951                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.867501                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5115444997000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.024979                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376561                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376561                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        89804                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        89804                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24185                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        24185                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24187                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        24187                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24187                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        24187                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        13810                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        13810                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        13810                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        13810                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        13810                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        13810                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    163118000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    163118000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    163118000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    163118000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    163118000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    163118000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        37995                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        37995                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        37997                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        37997                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        37997                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        37997                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.363469                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.363469                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.363450                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.363450                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.363450                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.363450                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11811.585807                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11811.585807                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11811.585807                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11811.585807                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11811.585807                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11811.585807                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         2462                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         2462                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        13810                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        13810                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        13810                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        13810                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        13810                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        13810                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    149308000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    149308000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    149308000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    149308000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    149308000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    149308000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.363469                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.363469                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.363450                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.363450                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.363450                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.363450                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10811.585807                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10811.585807                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10811.585807                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10811.585807                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111812                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64798.412308                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4876376                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176112                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.689062                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50635.420946                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.805219                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.143023                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3115.012545                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11033.030575                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.772635                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000226                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047531                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.168351                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.988745                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64300                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          754                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3256                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6271                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53979                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.981140                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43447179                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43447179                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      1581625                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1581625                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       974382                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       974382                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       155418                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       155418                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       959842                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       959842                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        64107                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        10951                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332187                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1407245                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64107                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        10951                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       959842                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1487605                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2522505                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64107                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        10951                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       959842                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1487605                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2522505                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1494                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1494                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132350                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132350                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16217                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16217                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           62                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            6                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35695                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35763                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           62                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16217                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168045                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        184330                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           62                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16217                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168045                       # number of overall misses
system.cpu.l2cache.overall_misses::total       184330                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     55230000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     55230000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16916399500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16916399500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2173643500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2173643500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      9044000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       812500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4836164500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   4846021000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9044000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       812500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2173643500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  21752564000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  23936064000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9044000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       812500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2173643500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  21752564000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  23936064000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1581625                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1581625                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       974382                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       974382                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1814                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1814                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287768                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287768                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       976059                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       976059                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        64169                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        10957                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1367882                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1443008                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64169                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        10957                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       976059                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1655650                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2706835                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64169                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        10957                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       976059                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1655650                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2706835                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.823594                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.823594                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.459919                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.459919                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016615                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016615                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000548                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026095                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024784                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000548                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016615                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101498                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068098                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000966                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000548                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016615                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101498                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068098                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 36967.871486                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 36967.871486                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127815.636570                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127815.636570                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134034.870815                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134034.870815                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135416.666667                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135485.768315                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135503.760870                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135416.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134034.870815                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129444.874885                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 129854.413281                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 145870.967742                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135416.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134034.870815                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129444.874885                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 129854.413281                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102257                       # number of writebacks
system.cpu.l2cache.writebacks::total           102257                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            1                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            1                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            8                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            8                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1494                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1494                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132350                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132350                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16215                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16215                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           62                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            6                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35694                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35762                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16215                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168044                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       184327                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           62                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16215                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168044                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       184327                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       573476                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       573476                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13931                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13931                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       587407                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587407                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    102660500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    102660500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15592899500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15592899500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2011389507                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2011389507                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8424000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       752500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4479803007                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4488979507                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8424000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       752500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2011389507                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20072702507                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  22093268514                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8424000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       752500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2011389507                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20072702507                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  22093268514                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90948457000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90948457000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2623573000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2623573000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93572030000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93572030000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.823594                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.823594                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.459919                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.459919                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016613                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026094                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024783                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101497                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068097                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000966                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000548                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016613                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101497                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068097                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68715.194110                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68715.194110                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117815.636570                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117815.636570                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124044.989639                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125523.726497                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119449.087781                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119859.101022                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125416.666667                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124044.989639                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5434918                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2706203                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        65803                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1240                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1240                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         573476                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3003914                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13931                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1730558                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       975620                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       168030                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2247                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2247                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287779                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287779                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       976205                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1454773                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1647                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2927884                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6146809                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        37703                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       206355                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9318751                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    124907456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207405643                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       858816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5441920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          338613835                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      220482                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3516168                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.019658                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.160049                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3458199     98.35%     98.35% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              46816      1.33%     99.68% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              11153      0.32%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3516168                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5575385475                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       661286                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1466090916                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3066273273                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      20730469                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     107476352                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               212032                       # Transaction distribution
system.iobus.trans_dist::ReadResp              212032                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57756                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57756                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1647                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1647                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       400004                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       444328                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95248                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95248                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  542870                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       200002                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       228450                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027776                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027776                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6588                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3262814                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3982096                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                42500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy             10538500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy              1023500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy                92500                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                59500                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                32500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy            300003000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy              1174500                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy              212500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            24563000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               12500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           242078063                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1233000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           433292000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50160000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1647000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47569                       # number of replacements
system.iocache.tags.tagsinuse                0.116006                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47585                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4999354367000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116006                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007250                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007250                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
system.iocache.tags.data_accesses              428616                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          904                       # number of demand (read+write) misses
system.iocache.demand_misses::total               904                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          904                       # number of overall misses
system.iocache.overall_misses::total              904                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149927198                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    149927198                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5867794865                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5867794865                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    149927198                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    149927198                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    149927198                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    149927198                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          904                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             904                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          904                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            904                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165848.670354                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 165848.670354                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 165848.670354                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           254                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   23                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.043478                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          904                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          904                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          904                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          904                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    104727198                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3529874733                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3529874733                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    104727198                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104727198                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    104727198                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115848.670354                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 115848.670354                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              573476                       # Transaction distribution
system.membus.trans_dist::ReadResp             626351                       # Transaction distribution
system.membus.trans_dist::WriteReq              13931                       # Transaction distribution
system.membus.trans_dist::WriteResp             13931                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       148924                       # Transaction distribution
system.membus.trans_dist::CleanEvict            10358                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2192                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              19                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132088                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132085                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         52881                       # Transaction distribution
system.membus.trans_dist::MessageReq             1647                       # Transaction distribution
system.membus.trans_dist::MessageResp            1647                       # Transaction distribution
system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       444328                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730486                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       481353                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1656179                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        95636                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total        95636                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1755109                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       228450                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460969                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18281344                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     19970763                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22992391                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1583                       # Total snoops (count)
system.membus.snoop_fanout::samples            982226                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001677                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040914                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  980579     99.83%     99.83% # Request fanout histogram
system.membus.snoop_fanout::2                    1647      0.17%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total              982226                       # Request fanout histogram
system.membus.reqLayer0.occupancy           339026000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           369109500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3981904                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1012407982                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                8500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            2334904                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2135091502                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy            4662400                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------