path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.125918                       # Number of seconds simulated
sim_ticks                                5125917808500                       # Number of ticks simulated
final_tick                               5125917808500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 163224                       # Simulator instruction rate (inst/s)
host_op_rate                                   322646                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2051147218                       # Simulator tick rate (ticks/s)
host_mem_usage                                 753920                       # Number of bytes of host memory used
host_seconds                                  2499.05                       # Real time elapsed on the host
sim_insts                                   407905794                       # Number of instructions simulated
sim_ops                                     806307064                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4992                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1044736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10779456                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11857920                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1044736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1044736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9592896                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9592896                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           78                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16324                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168429                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                185280                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149889                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149889                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            974                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               203814                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2102932                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2313326                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          203814                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             203814                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1871449                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1871449                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1871449                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           974                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              203814                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2102932                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5531                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4184776                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        185280                       # Number of read requests accepted
system.physmem.writeReqs                       196609                       # Number of write requests accepted
system.physmem.readBursts                      185280                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     196609                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11848512                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      9408                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  12427072                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11857920                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               12582976                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      147                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2411                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1705                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11356                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10792                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11765                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11427                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11775                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11293                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11205                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11692                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11087                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11285                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11605                       # Per bank write bursts
system.physmem.perBankRdBursts::11              12031                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11880                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12674                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11994                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11272                       # Per bank write bursts
system.physmem.perBankWrBursts::0               13000                       # Per bank write bursts
system.physmem.perBankWrBursts::1               12435                       # Per bank write bursts
system.physmem.perBankWrBursts::2               11147                       # Per bank write bursts
system.physmem.perBankWrBursts::3               11517                       # Per bank write bursts
system.physmem.perBankWrBursts::4               12452                       # Per bank write bursts
system.physmem.perBankWrBursts::5               12346                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11719                       # Per bank write bursts
system.physmem.perBankWrBursts::7               11239                       # Per bank write bursts
system.physmem.perBankWrBursts::8               12215                       # Per bank write bursts
system.physmem.perBankWrBursts::9               12097                       # Per bank write bursts
system.physmem.perBankWrBursts::10              12764                       # Per bank write bursts
system.physmem.perBankWrBursts::11              12134                       # Per bank write bursts
system.physmem.perBankWrBursts::12              12379                       # Per bank write bursts
system.physmem.perBankWrBursts::13              12264                       # Per bank write bursts
system.physmem.perBankWrBursts::14              12219                       # Per bank write bursts
system.physmem.perBankWrBursts::15              12246                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5125917756500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  185280                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 196609                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11800                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2009                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       409                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        44                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2619                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     9692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    11040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    11520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    12479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    12952                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    14075                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    13662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    14219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    13150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    12683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    11195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10547                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8304                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      332                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      295                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      266                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      250                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        74985                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      323.738348                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     187.730188                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     342.091209                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27875     37.17%     37.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17344     23.13%     60.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7346      9.80%     70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4205      5.61%     75.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3044      4.06%     79.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1991      2.66%     82.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1466      1.96%     84.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1106      1.47%     85.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10608     14.15%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          74985                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7802                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.727634                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      544.765031                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7801     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7802                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7802                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.887593                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.377135                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       24.103132                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6364     81.57%     81.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              53      0.68%     82.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              22      0.28%     82.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             275      3.52%     86.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             179      2.29%     88.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              53      0.68%     89.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              27      0.35%     89.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              51      0.65%     90.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             164      2.10%     92.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.22%     92.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              13      0.17%     92.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              14      0.18%     92.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              32      0.41%     93.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              25      0.32%     93.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               7      0.09%     93.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              50      0.64%     94.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             101      1.29%     95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               3      0.04%     95.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               9      0.12%     95.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              29      0.37%     95.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             150      1.92%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             8      0.10%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             7      0.09%     98.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             3      0.04%     98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            28      0.36%     98.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             4      0.05%     98.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            11      0.14%     98.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             4      0.05%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            23      0.29%     99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             7      0.09%     99.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             3      0.04%     99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            14      0.18%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151            10      0.13%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             9      0.12%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             4      0.05%     99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             2      0.03%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.01%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             2      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             1      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             3      0.04%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             2      0.03%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::244-247             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7802                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2011030750                       # Total ticks spent queuing
system.physmem.totMemAccLat                5482274500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    925665000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10862.63                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29612.63                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.42                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.45                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.38                       # Average write queue length when enqueuing
system.physmem.readRowHits                     151985                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    152335                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.44                       # Row buffer hit rate for writes
system.physmem.avgGap                     13422533.14                       # Average gap between requests
system.physmem.pageHitRate                      80.23                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     4919402035500                       # Time in different power states
system.physmem.memoryStateTime::REF      171165540000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       35350129500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 274957200                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 291929400                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 150026250                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 159286875                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0                712179000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1                731850600                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               621140400                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               637100640                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0          334799796240                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1          334799796240                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0          129444240060                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1          129652397505                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          2962001074500                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          2961818480250                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            3428003413650                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            3428090841510                       # Total energy per rank (pJ)
system.physmem.averagePower::0             668.759392                       # Core power per rank (mW)
system.physmem.averagePower::1             668.776448                       # Core power per rank (mW)
system.cpu.branchPred.lookups                86891854                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86891854                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            902474                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             80057154                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78172464                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.645819                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1556145                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             178539                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        449528542                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27579139                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      429063602                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86891854                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79728609                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     417924990                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1892404                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     141641                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                49747                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        210937                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles       127048                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          749                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9185584                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                447344                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4767                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          446980453                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.894336                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.051866                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                281454432     62.97%     62.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2285018      0.51%     63.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72162718     16.14%     79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1595292      0.36%     79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2151182      0.48%     80.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2328836      0.52%     80.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1532887      0.34%     81.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1872269      0.42%     81.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81597819     18.26%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            446980453                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.193296                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.954475                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 23006879                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             264875775                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150713064                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7438533                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 946202                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838427175                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 946202                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25861517                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               223289477                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       13277674                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154607234                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              28998349                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834936902                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                476513                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12412504                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 177326                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               13726812                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           997336716                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1813473834                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1114859292                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               146                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964283425                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 33053286                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             468997                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         473016                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  39075310                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17327574                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10191135                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1313699                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1076527                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  829405798                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1211413                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 824144334                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            238741                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23374016                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     36157635                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         155810                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     446980453                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.843804                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.418028                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           262751782     58.78%     58.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13860127      3.10%     61.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10088289      2.26%     64.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6929216      1.55%     65.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74323701     16.63%     82.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4464363      1.00%     83.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72802131     16.29%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1196176      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              564668      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       446980453                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1984017     71.87%     71.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    212      0.01%     71.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                    1649      0.06%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 613790     22.24%     94.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                160788      5.82%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            292283      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795766200     96.56%     96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150572      0.02%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                125282      0.02%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   8      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18411850      2.23%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9398139      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              824144334                       # Type of FU issued
system.cpu.iq.rate                           1.833353                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2760456                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003349                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2098268090                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         854003641                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819590055                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 227                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                270                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           62                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              826612402                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     105                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1877597                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3329866                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14364                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14470                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1763076                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2224552                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         71468                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 946202                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               205595274                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               9411486                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           830617211                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            184433                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17327584                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10191135                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             714161                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 416193                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8093117                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14470                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         516905                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       536436                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1053341                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822534076                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              18016449                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1476395                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27187129                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83286990                       # Number of branches executed
system.cpu.iew.exec_stores                    9170680                       # Number of stores executed
system.cpu.iew.exec_rate                     1.829771                       # Inst execution rate
system.cpu.iew.wb_sent                      822027813                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819590117                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640953314                       # num instructions producing a value
system.cpu.iew.wb_consumers                1050450596                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.823222                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610170                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        24215626                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1055602                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            914308                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    443339838                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.818711                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.675515                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    272569121     61.48%     61.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11207092      2.53%     64.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3543073      0.80%     64.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74545535     16.81%     81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2433206      0.55%     82.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1610406      0.36%     82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       913346      0.21%     82.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71032181     16.02%     98.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5485878      1.24%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    443339838                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407905794                       # Number of instructions committed
system.cpu.commit.committedOps              806307064                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22425775                       # Number of memory references committed
system.cpu.commit.loads                      13997716                       # Number of loads committed
system.cpu.commit.membars                      475203                       # Number of memory barriers committed
system.cpu.commit.branches                   82185787                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735131032                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155610                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       174231      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783440615     97.16%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144913      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121530      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13997716      1.74%     98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8428059      1.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806307064                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5485878                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1268298437                       # The number of ROB reads
system.cpu.rob.rob_writes                  1664703185                       # The number of ROB writes
system.cpu.timesIdled                          295137                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2548089                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9802307300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407905794                       # Number of Instructions Simulated
system.cpu.committedOps                     806307064                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.102040                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.102040                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.907408                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.907408                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1092406866                       # number of integer regfile reads
system.cpu.int_regfile_writes               656005719                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        62                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416194474                       # number of cc regfile reads
system.cpu.cc_regfile_writes                322040205                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265569258                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402671                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1659070                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.990007                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19130419                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1659582                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.527251                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.990007                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999980                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999980                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          203                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88317394                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88317394                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10978879                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10978879                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8084521                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8084521                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64338                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64338                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19063400                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19063400                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19127738                       # number of overall hits
system.cpu.dcache.overall_hits::total        19127738                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1796470                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1796470                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       333911                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       333911                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406328                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406328                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2130381                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2130381                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2536709                       # number of overall misses
system.cpu.dcache.overall_misses::total       2536709                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  26526077953                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  26526077953                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12856931699                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12856931699                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  39383009652                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  39383009652                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  39383009652                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  39383009652                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12775349                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12775349                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8418432                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8418432                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       470666                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       470666                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21193781                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21193781                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21664447                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21664447                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140620                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.140620                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039664                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039664                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863304                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.863304                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.100519                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.100519                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117091                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117091                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14765.667088                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14765.667088                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38504.067548                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38504.067548                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18486.369176                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18486.369176                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15525.237484                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15525.237484                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       375690                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             39932                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.408244                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1560667                       # number of writebacks
system.cpu.dcache.writebacks::total           1560667                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       827312                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       827312                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44114                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44114                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       871426                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       871426                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       871426                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       871426                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       969158                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       969158                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289797                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289797                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402869                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402869                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1258955                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1258955                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1661824                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1661824                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12253110515                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12253110515                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11193391556                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11193391556                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5590029250                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5590029250                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23446502071                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23446502071                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29036531321                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29036531321                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97386643000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97386643000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2557063000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2557063000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99943706000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99943706000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075862                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075862                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034424                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034424                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855955                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855955                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059402                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059402                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076707                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076707                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12643.047382                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12643.047382                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38624.939375                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38624.939375                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13875.550737                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13875.550737                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18623.780891                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18623.780891                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.687433                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.687433                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        73854                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.812426                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       117340                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        73869                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.588488                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.812426                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988277                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988277                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       459584                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       459584                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       117385                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       117385                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       117385                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       117385                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       117385                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       117385                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74938                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        74938                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74938                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        74938                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74938                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        74938                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    912423463                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    912423463                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    912423463                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    912423463                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    912423463                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    912423463                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       192323                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       192323                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       192323                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       192323                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       192323                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       192323                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.389647                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.389647                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.389647                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.389647                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12175.711428                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12175.711428                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12175.711428                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12175.711428                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        19615                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        19615                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74938                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74938                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74938                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        74938                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74938                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        74938                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    762426693                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    762426693                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    762426693                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    762426693                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.389647                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.389647                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.389647                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.389647                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10174.099829                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10174.099829                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10174.099829                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            996223                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.034964                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8125334                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            996735                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.151950                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147627648000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.034964                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996162                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996162                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          129                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10182364                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10182364                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8125334                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8125334                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8125334                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8125334                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8125334                       # number of overall hits
system.cpu.icache.overall_hits::total         8125334                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1060246                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1060246                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1060246                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1060246                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1060246                       # number of overall misses
system.cpu.icache.overall_misses::total       1060246                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14710988702                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14710988702                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14710988702                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14710988702                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14710988702                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14710988702                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9185580                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9185580                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9185580                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9185580                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9185580                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9185580                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115425                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.115425                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.115425                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.115425                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.115425                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.115425                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13875.071165                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13875.071165                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13875.071165                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13875.071165                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13875.071165                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         8852                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    29.408638                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        63462                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        63462                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        63462                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        63462                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        63462                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        63462                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       996784                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       996784                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       996784                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       996784                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       996784                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       996784                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12075236643                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12075236643                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12075236643                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12075236643                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12075236643                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12075236643                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108516                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108516                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108516                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108516                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12114.195897                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12114.195897                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12114.195897                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        13757                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.017843                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        26179                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        13772                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.900886                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104067070500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.017843                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376115                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376115                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        96280                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        96280                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26178                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        26178                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26180                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        26180                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26180                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        26180                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14640                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        14640                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14640                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        14640                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14640                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        14640                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    168910997                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    168910997                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    168910997                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    168910997                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    168910997                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    168910997                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        40818                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        40818                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        40820                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        40820                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        40820                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        40820                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358665                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358665                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358648                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.358648                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358648                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.358648                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11537.636407                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11537.636407                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11537.636407                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11537.636407                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11537.636407                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         3000                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         3000                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14640                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14640                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14640                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        14640                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14640                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        14640                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    139618019                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    139618019                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    139618019                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    139618019                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    139618019                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    139618019                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358665                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358665                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358648                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358648                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358648                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9536.749932                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9536.749932                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9536.749932                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           113048                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64817.930454                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3838289                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           177093                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.673861                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50426.330308                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    22.730844                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.138507                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3266.844648                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11101.886147                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.769445                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000347                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.049848                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.169401                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989043                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64045                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          604                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3317                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5815                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54248                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977249                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         35033990                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        35033990                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67104                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12092                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       980368                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1335401                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2394965                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1583282                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1583282                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          318                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          318                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154206                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154206                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        67104                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12092                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       980368                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1489607                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2549171                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        67104                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12092                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       980368                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1489607                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2549171                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           78                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16326                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35890                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52300                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1440                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1440                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133494                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133494                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           78                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16326                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169384                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185794                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           78                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16326                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169384                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185794                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6504500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       472000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1249428250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2850151495                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4106556245                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17517303                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17517303                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9319163717                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9319163717                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6504500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       472000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1249428250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12169315212                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13425719962                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6504500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       472000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1249428250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12169315212                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13425719962                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67182                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12098                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       996694                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1371291                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2447265                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1583282                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1583282                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1758                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1758                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287700                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287700                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67182                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12098                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       996694                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1658991                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2734965                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67182                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12098                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       996694                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1658991                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2734965                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001161                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000496                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016380                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026172                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021371                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.819113                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.819113                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464004                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.464004                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001161                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000496                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016380                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102101                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067933                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001161                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000496                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016380                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102101                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067933                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83391.025641                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78666.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76529.967536                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79413.527306                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78519.239866                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12164.793750                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12164.793750                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69809.607301                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69809.607301                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83391.025641                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78666.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76529.967536                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71844.537926                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72261.321474                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83391.025641                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78666.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76529.967536                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71844.537926                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72261.321474                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       103222                       # number of writebacks
system.cpu.l2cache.writebacks::total           103222                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           78                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16324                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35888                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52296                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1440                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1440                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133494                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133494                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           78                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16324                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169382                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185790                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           78                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16324                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169382                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185790                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5539000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       396000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1044610750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2405275997                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3455821747                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15368421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15368421                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7642927283                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7642927283                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5539000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       396000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1044610750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10048203280                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11098749030                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5539000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       396000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1044610750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10048203280                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11098749030                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89272220000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89272220000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2390455500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2390455500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91662675500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91662675500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026171                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021369                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819113                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819113                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464004                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464004                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102099                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067931                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001161                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016378                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102099                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067931                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67021.734201                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66081.951717                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10672.514583                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10672.514583                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57252.964800                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57252.964800                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59738.139997                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71012.820513                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63992.327248                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59322.733703                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59738.139997                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3068576                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3068035                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13841                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13841                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1583282                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2219                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2219                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1993478                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6130100                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        29738                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       161735                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8315051                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63788416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207873825                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       966272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5555008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278183521                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       59487                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4379111                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.010877                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.103722                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            4331481     98.91%     98.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              47630      1.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4379111                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4067623882                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       571500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1499268850                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3141964932                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      21966489                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     112467385                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               225657                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225657                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57676                       # Transaction distribution
system.iobus.trans_dist::WriteResp              10956                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1641                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1641                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27696                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471406                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95260                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3282                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3282                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569948                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       241980                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027824                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3276368                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3911656                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20719000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           448438152                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460450000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            52358513                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1641000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47575                       # number of replacements
system.iocache.tags.tagsinuse                0.091509                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47591                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992976927000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091509                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005719                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005719                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428670                       # Number of tag accesses
system.iocache.tags.data_accesses              428670                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          910                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              910                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          910                       # number of demand (read+write) misses
system.iocache.demand_misses::total               910                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          910                       # number of overall misses
system.iocache.overall_misses::total              910                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151600663                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    151600663                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12348426976                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  12348426976                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    151600663                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    151600663                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    151600663                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    151600663                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          910                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            910                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          910                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             910                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          910                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            910                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 166594.135165                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264307.084247                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264307.084247                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 166594.135165                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166594.135165                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 166594.135165                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         70653                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 9154                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.718265                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          910                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          910                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          910                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          910                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          910                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          910                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    104259663                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9918961002                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    104259663                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104259663                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    104259663                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114571.058242                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212306.528296                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212306.528296                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114571.058242                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 114571.058242                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              662598                       # Transaction distribution
system.membus.trans_dist::ReadResp             662586                       # Transaction distribution
system.membus.trans_dist::WriteReq              13841                       # Transaction distribution
system.membus.trans_dist::WriteResp             13841                       # Transaction distribution
system.membus.trans_dist::Writeback            149889                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2184                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1723                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133213                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133211                       # Transaction distribution
system.membus.trans_dist::MessageReq             1641                       # Transaction distribution
system.membus.trans_dist::MessageResp            1641                       # Transaction distribution
system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3282                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3282                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471406                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775060                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       477445                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723935                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141460                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141460                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1868677                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241980                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550117                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18435776                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20227873                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                26239557                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1606                       # Total snoops (count)
system.membus.snoop_fanout::samples            385212                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  385212    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              385212                       # Request fanout histogram
system.membus.reqLayer0.occupancy           251510000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583228000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3282000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1995467500                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               16000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1641000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3158524545                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy           54933487                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------