path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.154240                       # Number of seconds simulated
sim_ticks                                5154239928000                       # Number of ticks simulated
final_tick                               5154239928000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 179131                       # Simulator instruction rate (inst/s)
host_op_rate                                   354077                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2263170239                       # Simulator tick rate (ticks/s)
host_mem_usage                                 759084                       # Number of bytes of host memory used
host_seconds                                  2277.44                       # Real time elapsed on the host
sim_insts                                   407959851                       # Number of instructions simulated
sim_ops                                     806389826                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4224                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1048832                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10760128                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11841856                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1048832                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1048832                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9579968                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9579968                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           66                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16388                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168127                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                185029                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149687                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149687                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            820                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               203489                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2087627                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5501                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2297498                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          203489                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             203489                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1858658                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1858658                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1858658                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              203489                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2087627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4156156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        185029                       # Number of read requests accepted
system.physmem.writeReqs                       196407                       # Number of write requests accepted
system.physmem.readBursts                      185029                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     196407                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11835328                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6528                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  10911872                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11841856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               12570048                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      102                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                   25884                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1735                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11576                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11057                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12153                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11198                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11802                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11348                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11143                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11153                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11425                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11213                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11332                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11504                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11762                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12902                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11974                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11385                       # Per bank write bursts
system.physmem.perBankWrBursts::0               11439                       # Per bank write bursts
system.physmem.perBankWrBursts::1               10429                       # Per bank write bursts
system.physmem.perBankWrBursts::2               10485                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9453                       # Per bank write bursts
system.physmem.perBankWrBursts::4               11713                       # Per bank write bursts
system.physmem.perBankWrBursts::5               11103                       # Per bank write bursts
system.physmem.perBankWrBursts::6               10277                       # Per bank write bursts
system.physmem.perBankWrBursts::7               10587                       # Per bank write bursts
system.physmem.perBankWrBursts::8               10639                       # Per bank write bursts
system.physmem.perBankWrBursts::9               10347                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10880                       # Per bank write bursts
system.physmem.perBankWrBursts::11              10311                       # Per bank write bursts
system.physmem.perBankWrBursts::12              10712                       # Per bank write bursts
system.physmem.perBankWrBursts::13              11096                       # Per bank write bursts
system.physmem.perBankWrBursts::14              11110                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9917                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          48                       # Number of times write queue was full causing retry
system.physmem.totGap                    5154239876000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  185029                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 196407                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170541                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11600                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1966                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        41                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        35                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1636                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1926                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     7830                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     8415                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     7894                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8094                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9954                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8496                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     7725                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    10840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8567                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7987                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     1631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     2901                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     3411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     2551                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     2324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     2194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     2613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     2036                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1543                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      438                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      298                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      219                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       57                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        73580                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      309.148356                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     181.632665                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     329.613307                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27722     37.68%     37.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17426     23.68%     61.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7585     10.31%     71.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4195      5.70%     77.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2982      4.05%     81.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2040      2.77%     84.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1416      1.92%     86.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1303      1.77%     87.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8911     12.11%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          73580                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          6767                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.326437                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      584.974446                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           6766     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            6767                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          6767                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        25.195508                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.700984                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       42.210035                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31            6335     93.62%     93.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47              84      1.24%     94.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63              17      0.25%     95.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79              17      0.25%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95              19      0.28%     95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111             20      0.30%     95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127            33      0.49%     96.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143            32      0.47%     96.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159            26      0.38%     97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175             8      0.12%     97.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191            61      0.90%     98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207            50      0.74%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223            12      0.18%     99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239             1      0.01%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255             2      0.03%     99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287             3      0.04%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303             2      0.03%     99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319             2      0.03%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335             4      0.06%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351             9      0.13%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367            14      0.21%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383             6      0.09%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495             2      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559             3      0.04%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            6767                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2002245948                       # Total ticks spent queuing
system.physmem.totMemAccLat                5469627198                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    924635000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10827.22                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29577.22                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.30                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.12                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.30                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.44                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.30                       # Average write queue length when enqueuing
system.physmem.readRowHits                     151945                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    129899                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.16                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  76.18                       # Row buffer hit rate for writes
system.physmem.avgGap                     13512725.27                       # Average gap between requests
system.physmem.pageHitRate                      79.29                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  271547640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  148165875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 713146200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                553949280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           336649428960                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           130302295830                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2978239548750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3446878082535                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.747042                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4954509635136                       # Time in different power states
system.physmem_0.memoryStateTime::REF    172111160000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27619022864                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  284717160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  155351625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 729276600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                550877760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           336649428960                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           130834885590                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2977772364750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3446976902445                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.766215                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4953723422640                       # Time in different power states
system.physmem_1.memoryStateTime::REF    172111160000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     28398444860                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86886659                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86886659                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            896606                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             80012064                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78173158                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.701714                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1555790                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180979                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        452015949                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27708415                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      429123541                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86886659                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79728948                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     420284778                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1879978                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     144708                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                58405                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        207121                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           57                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          651                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9181144                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                450119                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5089                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          449344124                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.884391                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.047300                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                283935319     63.19%     63.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2153229      0.48%     63.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72170843     16.06%     79.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1584001      0.35%     80.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2141625      0.48%     80.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2336888      0.52%     81.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1524270      0.34%     81.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1887238      0.42%     81.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81610711     18.16%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            449344124                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192220                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.949355                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 23005123                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             267198709                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150742142                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7458161                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 939989                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838443104                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 939989                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25847202                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               224345308                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       13466568                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154654216                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              30090841                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834933758                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                459142                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12335285                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 199811                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               14823013                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           997303578                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1813575837                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1114848675                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               334                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964352232                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32951344                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             467055                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         470880                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  38821668                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17323479                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10180206                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1295686                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1069829                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  829469634                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1196558                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 824230120                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            243416                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23349289                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     36028466                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         151024                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     449344124                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.834296                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.415438                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           265024726     58.98%     58.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            14037592      3.12%     62.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9914300      2.21%     64.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7059540      1.57%     65.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74309398     16.54%     82.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4399488      0.98%     83.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72817937     16.21%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1206490      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              574653      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       449344124                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1987162     71.98%     71.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    137      0.00%     71.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     645      0.02%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 611861     22.16%     94.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                160804      5.82%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            290308      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795868269     96.56%     96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150766      0.02%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                125160      0.02%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  92      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18401922      2.23%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9393603      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              824230120                       # Type of FU issued
system.cpu.iq.rate                           1.823454                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2760609                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003349                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2100807897                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         854027763                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819692227                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 491                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                488                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          172                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              826700185                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     236                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1868049                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3330814                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14803                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14207                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1754572                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207477                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         74768                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 939989                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               205903045                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10169335                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           830666192                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            152285                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17323479                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10180206                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             703380                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 416558                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8857895                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14207                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         510302                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       537060                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1047362                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822616274                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              18004247                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1478799                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27174393                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83301836                       # Number of branches executed
system.cpu.iew.exec_stores                    9170146                       # Number of stores executed
system.cpu.iew.exec_rate                     1.819883                       # Inst execution rate
system.cpu.iew.wb_sent                      822114086                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819692399                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640992347                       # num instructions producing a value
system.cpu.iew.wb_consumers                1050518142                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.813415                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610168                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        24149765                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1045534                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            907960                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    445713409                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.809212                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.671420                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    274913705     61.68%     61.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11179565      2.51%     64.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3571950      0.80%     64.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74564778     16.73%     81.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2421074      0.54%     82.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1628213      0.37%     82.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       937027      0.21%     82.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71052272     15.94%     98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5444825      1.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    445713409                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407959851                       # Number of instructions committed
system.cpu.commit.committedOps              806389826                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22418298                       # Number of memory references committed
system.cpu.commit.loads                      13992664                       # Number of loads committed
system.cpu.commit.membars                      471797                       # Number of memory barriers committed
system.cpu.commit.branches                   82198639                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735203522                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155963                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171777      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783535872     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144976      0.02%     97.21% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121468      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13990083      1.73%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8425634      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806389826                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5444825                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1270729806                       # The number of ROB reads
system.cpu.rob.rob_writes                  1664729387                       # The number of ROB writes
system.cpu.timesIdled                          294275                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2671825                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9856461520                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407959851                       # Number of Instructions Simulated
system.cpu.committedOps                     806389826                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.107991                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.107991                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.902534                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.902534                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1092541258                       # number of integer regfile reads
system.cpu.int_regfile_writes               656084038                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       176                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416293281                       # number of cc regfile reads
system.cpu.cc_regfile_writes                322054452                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265591845                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400328                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1659836                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.989699                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19130413                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1660348                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.521930                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          41264250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.989699                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999980                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999980                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88364873                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88364873                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10981747                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10981747                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8081553                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8081553                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64328                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64328                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19063300                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19063300                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19127628                       # number of overall hits
system.cpu.dcache.overall_hits::total        19127628                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1807734                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1807734                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334390                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334390                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406367                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406367                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2142124                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2142124                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2548491                       # number of overall misses
system.cpu.dcache.overall_misses::total       2548491                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  27237843437                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  27237843437                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  13894605384                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  13894605384                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41132448821                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41132448821                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41132448821                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41132448821                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12789481                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12789481                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8415943                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8415943                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       470695                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       470695                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21205424                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21205424                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21676119                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21676119                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.141345                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.141345                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039733                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039733                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863334                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.863334                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101018                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101018                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.117571                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.117571                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19201.712329                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16139.923124                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       413510                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            7                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             44186                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.358394                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets            7                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1561658                       # number of writebacks
system.cpu.dcache.writebacks::total           1561658                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       837908                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       837908                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44444                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44444                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       882352                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       882352                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       882352                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       882352                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       969826                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       969826                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289946                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289946                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402900                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402900                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1259772                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1259772                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1662672                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1662672                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12862571524                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12862571524                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12285238213                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12285238213                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5938147500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5938147500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25147809737                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25147809737                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31085957237                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31085957237                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97453049000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97453049000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2592894500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2592894500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075830                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075830                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034452                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034452                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.855968                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.855968                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059408                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059408                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076705                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076705                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        73822                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.784353                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       116295                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        73836                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.575045                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.784353                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.986522                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.986522                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       457427                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       457427                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       116311                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       116311                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       116311                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       116311                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       116311                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       116311                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74935                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        74935                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74935                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        74935                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74935                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        74935                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    914897711                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    914897711                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    914897711                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    914897711                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    914897711                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    914897711                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       191246                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       191246                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       191246                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       191246                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       191246                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       191246                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.391825                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.391825                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.391825                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.391825                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        20337                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        20337                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74935                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74935                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74935                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        74935                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74935                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        74935                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    802357975                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    802357975                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    802357975                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    802357975                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.391825                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.391825                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.391825                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.391825                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1000631                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.729229                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8114183                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1001143                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.104919                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      148026169000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.729229                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.993612                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.993612                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          172                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10182374                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10182374                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8114183                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8114183                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8114183                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8114183                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8114183                       # number of overall hits
system.cpu.icache.overall_hits::total         8114183                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1066954                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1066954                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1066954                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1066954                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1066954                       # number of overall misses
system.cpu.icache.overall_misses::total       1066954                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14925731792                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14925731792                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14925731792                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14925731792                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14925731792                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14925731792                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9181137                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9181137                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9181137                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9181137                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9181137                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9181137                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116212                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116212                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116212                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116212                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116212                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116212                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13989.105240                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13989.105240                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        10002                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               328                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    30.493902                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        65717                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        65717                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        65717                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        65717                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        65717                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        65717                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1001237                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1001237                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1001237                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1001237                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1001237                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1001237                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12740674547                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12740674547                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12740674547                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12740674547                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12740674547                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12740674547                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109054                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.109054                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109054                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.109054                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        14933                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.063651                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        25583                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        14948                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.711466                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.063651                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.378978                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.378978                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        98613                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        98613                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25588                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25588                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25590                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25590                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25590                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25590                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        15811                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        15811                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        15811                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        15811                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        15811                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        15811                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    183242996                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    183242996                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    183242996                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    183242996                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    183242996                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    183242996                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41399                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        41399                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41401                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        41401                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41401                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        41401                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.381917                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.381917                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.381899                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.381899                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.381899                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.381899                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         3310                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         3310                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15811                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        15811                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        15811                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        15811                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        15811                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        15811                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    159511522                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    159511522                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    159511522                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    159511522                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    159511522                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    159511522                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.381917                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.381917                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.381899                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.381899                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.381899                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.381899                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112684                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64825.802499                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3846196                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176714                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.765089                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    15.517179                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.137228                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3161.997282                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768450                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000237                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048248                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.172226                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989163                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64030                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          558                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3484                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5616                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54343                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977020                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         35101682                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        35101682                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        67331                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        13137                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       984666                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1336353                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2401487                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1585305                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1585305                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          326                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          326                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154346                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154346                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        67331                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        13137                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       984666                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1490699                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2555833                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        67331                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        13137                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       984666                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1490699                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2555833                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           66                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16391                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35623                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52085                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1473                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1473                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133459                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133459                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           66                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16391                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169082                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185544                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           66                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16391                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169082                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185544                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      6193250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       446000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1375483774                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3059797000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4441920024                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     22673320                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     22673320                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10319199473                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10319199473                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6193250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       446000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1375483774                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13378996473                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  14761119497                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6193250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       446000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1375483774                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13378996473                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  14761119497                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        67397                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        13142                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1001057                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1371976                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2453572                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1585305                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1585305                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1799                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1799                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287805                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287805                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67397                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        13142                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1001057                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1659781                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2741377                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67397                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        13142                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1001057                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1659781                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2741377                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000380                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016374                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025965                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021228                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.818788                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818788                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463713                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.463713                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000380                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016374                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101870                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067683                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000979                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000380                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016374                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101870                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067683                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        89200                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        89200                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        89200                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       103019                       # number of writebacks
system.cpu.l2cache.writebacks::total           103019                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           66                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16388                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35622                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52081                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1473                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1473                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133459                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133459                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           66                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16388                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169081                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185540                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           66                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16388                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169081                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185540                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5361750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       383000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1170197226                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2615090750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3791032726                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27003455                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27003455                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8650755527                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8650755527                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5361750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       383000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1170197226                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11265846277                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12441788253                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5361750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       383000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1170197226                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11265846277                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12441788253                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  88987317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  88987317500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2410942500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2410942500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91398260000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91398260000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016371                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025964                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021227                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818788                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818788                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463713                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463713                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016371                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101869                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067681                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000979                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000380                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016371                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101869                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067681                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        76600                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3070183                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3069642                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1585305                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46754                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2280                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2280                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287814                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287814                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2002294                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6123530                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        32263                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       162669                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8320756                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64067648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207974818                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1052928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5614976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278710370                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       59545                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4387643                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.010865                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.103666                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            4339973     98.91%     98.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              47670      1.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4387643                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4071571970                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       574500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1506228195                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3139390437                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      23723987                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     112471118                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               223900                       # Transaction distribution
system.iobus.trans_dist::ReadResp              223900                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57738                       # Transaction distribution
system.iobus.trans_dist::WriteResp              11018                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1650                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1650                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       423734                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       468004                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95272                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95272                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3300                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  566576                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       211867                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       240285                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027872                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3274757                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3933000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            211868000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           257352407                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           456986000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50389253                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1650000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47582                       # number of replacements
system.iocache.tags.tagsinuse                0.177916                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47598                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4993302485000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.177916                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.011120                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.011120                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428724                       # Number of tag accesses
system.iocache.tags.data_accesses              428724                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          916                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              916                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          916                       # number of demand (read+write) misses
system.iocache.demand_misses::total               916                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          916                       # number of overall misses
system.iocache.overall_misses::total              916                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144791938                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144791938                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide   8565273216                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total   8565273216                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    144791938                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    144791938                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    144791938                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    144791938                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          916                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            916                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          916                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             916                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          916                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            916                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 158069.801310                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 158069.801310                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 158069.801310                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         29224                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 4409                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     6.628260                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46668                       # number of writebacks
system.iocache.writebacks::total                46668                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          916                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          916                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          916                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          916                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          916                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          916                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     96734432                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   6135821228                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   6135821228                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     96734432                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96734432                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     96734432                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 105605.275109                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 105605.275109                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              657690                       # Transaction distribution
system.membus.trans_dist::ReadResp             657682                       # Transaction distribution
system.membus.trans_dist::WriteReq              13919                       # Transaction distribution
system.membus.trans_dist::WriteResp             13919                       # Transaction distribution
system.membus.trans_dist::Writeback            149687                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2233                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1752                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133182                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133180                       # Transaction distribution
system.membus.trans_dist::MessageReq             1650                       # Transaction distribution
system.membus.trans_dist::MessageResp            1650                       # Transaction distribution
system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3300                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3300                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       468004                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769220                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       476828                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1714068                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141467                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141467                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1858835                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       240285                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538437                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18406720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20185442                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005184                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6005184                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                26197226                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1640                       # Total snoops (count)
system.membus.snoop_fanout::samples            384867                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  384867    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              384867                       # Request fanout histogram
system.membus.reqLayer0.occupancy           357799000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388520500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3300000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1203232654                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               10500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1650000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2208381292                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           51518747                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------