path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.132953                       # Number of seconds simulated
sim_ticks                                5132953103000                       # Number of ticks simulated
final_tick                               5132953103000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 118788                       # Simulator instruction rate (inst/s)
host_op_rate                                   234812                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1494512187                       # Simulator tick rate (ticks/s)
host_mem_usage                                 768808                       # Number of bytes of host memory used
host_seconds                                  3434.53                       # Real time elapsed on the host
sim_insts                                   407981680                       # Number of instructions simulated
sim_ops                                     806469686                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2427072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1080064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10859584                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14370176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1080064                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1080064                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9570112                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9570112                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        37923                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           49                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16876                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             169681                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                224534                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149533                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149533                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       472841                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            611                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               210418                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2115660                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2799592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          210418                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             210418                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1864446                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1864446                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1864446                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       472841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           611                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              210418                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2115660                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4664038                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        224534                       # Total number of read requests seen
system.physmem.writeReqs                       149533                       # Total number of write requests seen
system.physmem.cpureqs                         378540                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     14370176                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9570112                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14370176                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9570112                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      118                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4466                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14182                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13235                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 13224                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 16247                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13672                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 13108                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13087                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 16327                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13931                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13220                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13507                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                15686                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                13366                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12693                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13279                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                15652                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9160                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  8678                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8635                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 11642                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8788                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8537                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8431                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 11660                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  9003                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8633                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8850                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                11092                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 8524                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8172                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8641                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                11087                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           7                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5132953050000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  224534                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                 149533                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    174096                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     19313                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7127                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3462                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2988                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1869                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1810                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1754                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1686                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1155                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1047                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      960                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      876                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      799                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      788                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      880                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      827                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      370                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      214                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5748                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6326                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6441                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6502                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1108                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      754                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      176                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
system.physmem.totQLat                     4726159249                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                9244557999                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1122080000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3396318750                       # Total cycles spent in bank access
system.physmem.avgQLat                       21059.81                       # Average queueing delay per request
system.physmem.avgBankLat                    15134.03                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  41193.85                       # Average memory access latency
system.physmem.avgRdBW                           2.80                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.80                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.86                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        11.69                       # Average write queue length over time
system.physmem.readRowHits                     193610                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    105925                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.27                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  70.84                       # Row buffer hit rate for writes
system.physmem.avgGap                     13722015.17                       # Average gap between requests
system.iocache.replacements                     47570                       # number of replacements
system.iocache.tagsinuse                     0.103974                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47586                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4991995541000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.103974                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.006498                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.006498                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          905                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47625                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47625                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47625                       # number of overall misses
system.iocache.overall_misses::total            47625                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    145555660                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    145555660                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10008674105                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10008674105                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10154229765                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10154229765                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10154229765                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10154229765                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          905                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47625                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47625                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47625                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47625                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160834.983425                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 160834.983425                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214226.757384                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 214226.757384                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213212.173543                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 213212.173543                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213212.173543                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 213212.173543                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        133059                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                12235                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.875276                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          905                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47625                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47625                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47625                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47625                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98473941                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     98473941                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7577901783                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7577901783                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7676375724                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7676375724                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7676375724                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7676375724                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108810.984530                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 108810.984530                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162198.240218                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 162198.240218                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 161183.742236                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 161183.742236                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                86237029                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86237029                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1109949                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             81299216                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                79239397                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.466373                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        448469531                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27529474                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      426122909                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86237029                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79239397                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     163627324                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4728707                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     117219                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               63156445                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                36498                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         53889                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          420                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9038392                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                487130                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2791                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          258101520                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.259173                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.417982                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 94901402     36.77%     36.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1566001      0.61%     37.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71924847     27.87%     65.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   935145      0.36%     65.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1600289      0.62%     66.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2428838      0.94%     67.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1075499      0.42%     67.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1377865      0.53%     68.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 82291634     31.88%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            258101520                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192292                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.950171                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31223769                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              60616281                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 159439032                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3242187                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3580251                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838065302                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   921                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3580251                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33968457                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37481730                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       11034324                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159610574                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              12426184                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834407058                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 18980                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                5821881                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4760224                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             8257                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           995986207                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1811362671                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1811361735                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               936                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964469787                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 31516413                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             458013                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         465231                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  28772388                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17093245                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10135018                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1252851                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1005934                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  828306143                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1250828                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823325440                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            150511                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22168488                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33636711                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         196648                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     258101520                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.189929                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.384557                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            71580535     27.73%     27.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15499802      6.01%     33.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10327986      4.00%     37.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7455254      2.89%     40.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75927506     29.42%     70.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3856019      1.49%     71.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72517162     28.10%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              787235      0.31%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              150021      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       258101520                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  366750     34.22%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.22% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 553108     51.61%     85.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                151931     14.18%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            309801      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795758940     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17866354      2.17%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9390345      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823325440                       # Type of FU issued
system.cpu.iq.rate                           1.835856                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1071789                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001302                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1906104602                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         851735215                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818848735                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 378                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                450                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           94                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              824087257                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     171                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1645357                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3104742                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        23669                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11440                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1716567                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1932461                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         11842                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3580251                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                26245227                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2113533                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           829556971                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            304073                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17093245                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10135018                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             718533                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1617499                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11192                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11440                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         653820                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       594083                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1247903                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             821445654                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17451760                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1879785                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26608752                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83225006                       # Number of branches executed
system.cpu.iew.exec_stores                    9156992                       # Number of stores executed
system.cpu.iew.exec_rate                     1.831664                       # Inst execution rate
system.cpu.iew.wb_sent                      820984205                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818848829                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639993786                       # num instructions producing a value
system.cpu.iew.wb_consumers                1045886534                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.825874                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611915                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22977930                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054178                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1115022                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    254521269                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.168575                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.855004                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     82765060     32.52%     32.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11818595      4.64%     37.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3860584      1.52%     38.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74956276     29.45%     68.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2441275      0.96%     69.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1480165      0.58%     69.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       888603      0.35%     70.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70922136     27.86%     97.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5388575      2.12%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    254521269                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407981680                       # Number of instructions committed
system.cpu.commit.committedOps              806469686                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22406951                       # Number of memory references committed
system.cpu.commit.loads                      13988500                       # Number of loads committed
system.cpu.commit.membars                      474453                       # Number of memory barriers committed
system.cpu.commit.branches                   82201236                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735408262                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5388575                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1078502153                       # The number of ROB reads
system.cpu.rob.rob_writes                  1662494402                       # The number of ROB writes
system.cpu.timesIdled                         1221401                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190368011                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9817434094                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407981680                       # Number of Instructions Simulated
system.cpu.committedOps                     806469686                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407981680                       # Number of Instructions Simulated
system.cpu.cpi                               1.099239                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.099239                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.909720                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.909720                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1507130605                       # number of integer regfile reads
system.cpu.int_regfile_writes               977067823                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        94                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264732336                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402254                       # number of misc regfile writes
system.cpu.icache.replacements                1049385                       # number of replacements
system.cpu.icache.tagsinuse                509.447090                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7923264                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1049897                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.546706                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56158934000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     509.447090                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.995014                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.995014                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7923264                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7923264                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7923264                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7923264                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7923264                       # number of overall hits
system.cpu.icache.overall_hits::total         7923264                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1115125                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1115125                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1115125                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1115125                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1115125                       # number of overall misses
system.cpu.icache.overall_misses::total       1115125                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15322207492                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15322207492                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15322207492                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15322207492                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15322207492                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15322207492                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9038389                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9038389                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9038389                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9038389                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9038389                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9038389                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123377                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.123377                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.123377                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.123377                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.123377                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.123377                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13740.349729                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13740.349729                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13740.349729                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13740.349729                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13740.349729                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13740.349729                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        10877                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    36.136213                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        62547                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        62547                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        62547                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        62547                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        62547                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        62547                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1052578                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1052578                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1052578                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1052578                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1052578                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1052578                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12612158993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12612158993                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12612158993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12612158993                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12612158993                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12612158993                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116456                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.116456                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.116456                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.160935                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.160935                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.160935                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         8504                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.007408                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          27369                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         8519                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         3.212701                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5106816403500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.007408                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375463                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375463                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        27369                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        27369                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        27371                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        27371                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        27371                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        27371                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9373                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         9373                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9373                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         9373                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9373                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         9373                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    104966500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    104966500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    104966500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    104966500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    104966500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    104966500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        36742                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        36742                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        36744                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        36744                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        36744                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        36744                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.255103                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.255103                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.255089                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.255089                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.255089                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.255089                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11198.815747                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11198.815747                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11198.815747                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11198.815747                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11198.815747                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11198.815747                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1896                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1896                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9373                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9373                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9373                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         9373                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9373                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         9373                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     86220500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     86220500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     86220500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     86220500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     86220500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     86220500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.255103                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.255103                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.255089                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.255089                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.255089                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.255089                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9198.815747                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9198.815747                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9198.815747                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       107843                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       12.947477                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         134583                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       107858                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.247779                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5099863447000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.947477                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.809217                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.809217                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       134601                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       134601                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       134601                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       134601                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       134601                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       134601                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       108812                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       108812                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       108812                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       108812                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       108812                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       108812                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1371802000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1371802000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1371802000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1371802000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1371802000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1371802000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       243413                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       243413                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       243413                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       243413                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       243413                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       243413                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.447026                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.447026                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.447026                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12607.083778                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12607.083778                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12607.083778                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        34946                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        34946                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       108812                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       108812                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       108812                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       108812                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       108812                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       108812                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1154178000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1154178000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1154178000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.447026                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.447026                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.447026                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10607.083778                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10607.083778                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10607.083778                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1657617                       # number of replacements
system.cpu.dcache.tagsinuse                511.997737                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19103102                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1658129                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.520878                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               27986000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997737                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     11006955                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11006955                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8090467                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8090467                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19097422                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19097422                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19097422                       # number of overall hits
system.cpu.dcache.overall_hits::total        19097422                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2237002                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2237002                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       318492                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       318492                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2555494                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2555494                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2555494                       # number of overall misses
system.cpu.dcache.overall_misses::total       2555494                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32016735000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32016735000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9683080495                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9683080495                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41699815495                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41699815495                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41699815495                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41699815495                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13243957                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13243957                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8408959                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8408959                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21652916                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21652916                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21652916                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21652916                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.168907                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.168907                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037875                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037875                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118021                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118021                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118021                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118021                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14312.340803                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14312.340803                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30402.900214                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30402.900214                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16317.712151                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16317.712151                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16317.712151                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16317.712151                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       383482                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42249                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.076712                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1559520                       # number of writebacks
system.cpu.dcache.writebacks::total           1559520                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       866015                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       866015                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        26449                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        26449                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       892464                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       892464                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       892464                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       892464                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370987                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1370987                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292043                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       292043                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1663030                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1663030                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1663030                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1663030                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17418217500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17418217500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8839751495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8839751495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26257968995                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26257968995                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26257968995                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26257968995                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97350275500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97350275500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2525993500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2525993500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99876269000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99876269000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103518                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103518                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034730                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034730                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076804                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076804                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076804                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076804                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12704.874299                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12704.874299                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30268.664186                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30268.664186                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.233505                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.233505                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.233505                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.233505                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                113549                       # number of replacements
system.cpu.l2cache.tagsinuse             64828.327724                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3928640                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                177472                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.136675                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50064.846561                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker     9.159250                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.124586                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3285.119507                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11469.077820                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.763929                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000140                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.050127                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.175004                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.989202                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       102263                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7285                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1032873                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333038                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2475459                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1596362                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1596362                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          310                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          310                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       153914                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       153914                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       102263                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         7285                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1032873                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1486952                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2629373                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       102263                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         7285                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1032873                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1486952                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2629373                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           49                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16879                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36894                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        53827                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4124                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4124                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133799                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133799                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           49                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16879                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       170693                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        187626                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           49                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16879                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       170693                       # number of overall misses
system.cpu.l2cache.overall_misses::total       187626                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4543000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       320500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1178779000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2492461998                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3676104498                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17587000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17587000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6908700500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6908700500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4543000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       320500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1178779000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9401162498                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10584804998                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4543000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       320500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1178779000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9401162498                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10584804998                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       102312                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7290                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1049752                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1369932                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2529286                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1596362                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1596362                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4434                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4434                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287713                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287713                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       102312                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         7290                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1049752                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1657645                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2816999                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       102312                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         7290                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1049752                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1657645                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2816999                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000686                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016079                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026931                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021281                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.930086                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.930086                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.465043                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.465043                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000686                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016079                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102973                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.066605                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000686                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016079                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102973                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.066605                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        64100                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69837.016411                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67557.380550                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68294.805544                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4264.548982                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4264.548982                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51634.918796                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51634.918796                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        64100                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69837.016411                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55076.438389                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56414.382857                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        64100                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69837.016411                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55076.438389                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56414.382857                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102866                       # number of writebacks
system.cpu.l2cache.writebacks::total           102866                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           49                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16876                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36893                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        53823                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4124                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4124                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133799                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133799                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           49                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16876                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       170692                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       187622                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           49                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16876                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       170692                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       187622                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       257504                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    968789302                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2034070067                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3007046918                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42432097                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42432097                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5258255507                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5258255507                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       257504                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    968789302                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7292325574                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8265302425                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       257504                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    968789302                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7292325574                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8265302425                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89237875000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89237875000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2360777500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2360777500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91598652500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91598652500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026931                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021280                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.930086                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.930086                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.465043                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.465043                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102973                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.066604                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102973                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.066604                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55134.309137                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55869.180796                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10289.063288                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10289.063288                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39299.662232                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39299.662232                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42722.128594                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44052.949148                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42722.128594                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44052.949148                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------