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|
---------- Begin Simulation Statistics ----------
sim_seconds 5.136818 # Number of seconds simulated
sim_ticks 5136817990000 # Number of ticks simulated
final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 178524 # Simulator instruction rate (inst/s)
host_op_rate 352888 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2247974016 # Simulator tick rate (ticks/s)
host_mem_usage 798352 # Number of bytes of host memory used
host_seconds 2285.09 # Real time elapsed on the host
sim_insts 407944006 # Number of instructions simulated
sim_ops 806380994 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1073088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10819392 # Number of bytes read from this memory
system.physmem.bytes_read::total 14368384 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1073088 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1073088 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9566592 # Number of bytes written to this memory
system.physmem.bytes_written::total 9566592 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38633 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16767 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169053 # Number of read requests responded to by this memory
system.physmem.num_reads::total 224506 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 149478 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149478 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 481331 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 208901 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2106244 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2797137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 208901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 208901 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1862358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1862358 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1862358 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 481331 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 208901 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2106244 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4659495 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 224506 # Total number of read requests seen
system.physmem.writeReqs 149478 # Total number of write requests seen
system.physmem.cpureqs 388421 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 14368384 # Total number of bytes read from memory
system.physmem.bytesWritten 9566592 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 14368384 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 9566592 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 103 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4169 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 13472 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 14748 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 12720 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 14632 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 13467 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 14703 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 13182 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 14524 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 13510 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 15204 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 14041 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 14883 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 13300 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 14411 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 12663 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 14943 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 8673 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 8057 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 10082 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 8656 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 10024 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 8415 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 9887 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 8846 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 10505 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 9296 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 10166 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 8640 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 9822 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 8034 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 10163 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 164 # Number of times wr buffer was full causing retry
system.physmem.totGap 5136817938000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 224506 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 149642 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 4169 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 176041 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 21421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8452 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2802 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2098 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1307 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1298 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1186 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1137 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1093 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 856 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 418 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 228 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 5671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 6355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 6462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 6480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6488 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 6496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 6497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 6498 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 3338682949 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7589868949 # Sum of mem lat for all requests
system.physmem.totBusLat 897612000 # Total cycles spent in databus access
system.physmem.totBankLat 3353574000 # Total cycles spent in bank access
system.physmem.avgQLat 14878.07 # Average queueing delay per request
system.physmem.avgBankLat 14944.43 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 33822.49 # Average memory access latency
system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 11.19 # Average write queue length over time
system.physmem.readRowHits 197567 # Number of row buffer hits during reads
system.physmem.writeRowHits 87961 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes
system.physmem.avgGap 13735394.93 # Average gap between requests
system.iocache.replacements 47579 # number of replacements
system.iocache.tagsinuse 0.116428 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47595 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4991841370000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.116428 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.007277 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.007277 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses
system.iocache.demand_misses::total 47634 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses
system.iocache.overall_misses::total 47634 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143641932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 143641932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8950549160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 8950549160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 9094191092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9094191092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 9094191092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9094191092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157157.474836 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 157157.474836 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191578.535103 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 191578.535103 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190918.064660 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190918.064660 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 54662 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 7510 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 7.278562 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47634 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47634 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47634 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47634 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96083990 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 96083990 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6518807893 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 6518807893 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 6614891883 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 6614891883 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105124.715536 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 105124.715536 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139529.278532 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 139529.278532 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.numCycles 447901761 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 86252881 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 86252881 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1115345 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 81384938 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 79240101 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79240101 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 163642808 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4755358 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 112288 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 62866127 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 37152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 52962 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9042653 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 488997 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 3194 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 257883656 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.262433 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.418145 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 94667319 36.71% 36.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1563412 0.61% 37.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71921029 27.89% 65.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 936098 0.36% 65.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1601572 0.62% 66.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2435088 0.94% 67.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1080780 0.42% 67.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1378788 0.53% 68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 82299570 31.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 257883656 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.192571 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.951525 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31254353 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 60335803 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 159451505 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3240373 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3601622 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 838158125 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3601622 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 34003643 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 37352024 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 10890553 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 159616474 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 12419340 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 834485567 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19816 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5811427 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4758263 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 7797 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 996045264 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1811616758 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1811616222 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 964358369 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 31686888 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 460019 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 467360 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 28800044 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17105540 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10151316 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1164746 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 891886 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 828333374 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1249979 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 823307593 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 149787 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 22280168 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33846252 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 197115 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 257883656 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.192554 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.383898 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 71395205 27.69% 27.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15462696 6.00% 33.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10317630 4.00% 37.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7483312 2.90% 40.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 75909298 29.44% 70.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3861835 1.50% 71.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72513968 28.12% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 788170 0.31% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 151542 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 257883656 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 365240 34.17% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 553441 51.78% 85.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 150145 14.05% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 311438 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 795721586 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 17876340 2.17% 98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9398229 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 823307593 # Type of FU issued
system.cpu.iq.rate 1.838143 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1068826 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001298 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1905849140 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 851873423 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 818806890 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 220 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 824064883 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1642369 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 3123872 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 22910 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11412 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1729878 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1932382 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12176 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3601622 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 26144135 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2117005 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 829583353 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 307079 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17105540 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10151316 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 719112 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1614713 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 12810 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11412 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 656230 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 596856 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1253086 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 821409782 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17457108 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1897810 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 26622226 # number of memory reference insts executed
system.cpu.iew.exec_branches 83220659 # Number of branches executed
system.cpu.iew.exec_stores 9165118 # Number of stores executed
system.cpu.iew.exec_rate 1.833906 # Inst execution rate
system.cpu.iew.wb_sent 820945177 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 818806944 # cumulative count of insts written-back
system.cpu.iew.wb_producers 639956313 # num instructions producing a value
system.cpu.iew.wb_consumers 1045834424 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.828095 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.611910 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 23092364 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1052862 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1120067 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 254282034 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 3.171207 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.854640 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 82542979 32.46% 32.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11813450 4.65% 37.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3859102 1.52% 38.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74953678 29.48% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2443754 0.96% 69.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1483333 0.58% 69.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 886403 0.35% 69.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70916473 27.89% 97.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5382862 2.12% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 254282034 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407944006 # Number of instructions committed
system.cpu.commit.committedOps 806380994 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 22403103 # Number of memory references committed
system.cpu.commit.loads 13981665 # Number of loads committed
system.cpu.commit.membars 473467 # Number of memory barriers committed
system.cpu.commit.branches 82194070 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 735324556 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5382862 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1078294199 # The number of ROB reads
system.cpu.rob.rob_writes 1662567045 # The number of ROB writes
system.cpu.timesIdled 1221565 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 190018105 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9825731637 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407944006 # Number of Instructions Simulated
system.cpu.committedOps 806380994 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407944006 # Number of Instructions Simulated
system.cpu.cpi 1.097949 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.097949 # CPI: Total CPI of All Threads
system.cpu.ipc 0.910789 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.910789 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1507043995 # number of integer regfile reads
system.cpu.int_regfile_writes 976998949 # number of integer regfile writes
system.cpu.fp_regfile_reads 54 # number of floating regfile reads
system.cpu.misc_regfile_reads 264734619 # number of misc regfile reads
system.cpu.misc_regfile_writes 402509 # number of misc regfile writes
system.cpu.icache.replacements 1054256 # number of replacements
system.cpu.icache.tagsinuse 510.988943 # Cycle average of tags in use
system.cpu.icache.total_refs 7923866 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1054768 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.512425 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 56004276000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.988943 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998025 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998025 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7923866 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7923866 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7923866 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7923866 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7923866 # number of overall hits
system.cpu.icache.overall_hits::total 7923866 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1118784 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1118784 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1118784 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1118784 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1118784 # number of overall misses
system.cpu.icache.overall_misses::total 1118784 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15167301487 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15167301487 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15167301487 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15167301487 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15167301487 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15167301487 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9042650 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9042650 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9042650 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9042650 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9042650 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9042650 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123723 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123723 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123723 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123723 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123723 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123723 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13556.952447 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13556.952447 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13556.952447 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13556.952447 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 9830 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 33.664384 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61527 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 61527 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 61527 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 61527 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 61527 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 61527 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1057257 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1057257 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1057257 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1057257 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1057257 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1057257 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12498307487 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12498307487 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12498307487 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12498307487 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12498307487 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12498307487 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116919 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116919 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116919 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11821.446902 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11821.446902 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 9287 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.016215 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 26989 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 9300 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.902043 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5102704183500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016215 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376013 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.376013 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27015 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 27015 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27017 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 27017 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27017 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 27017 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10179 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 10179 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10179 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 10179 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10179 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 10179 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 111301500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 111301500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 111301500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 111301500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 111301500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 111301500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37194 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 37194 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37196 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 37196 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37196 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 37196 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.273673 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.273673 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.273658 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.273658 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.273658 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.273658 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10934.423814 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10934.423814 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10934.423814 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10934.423814 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 1896 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1896 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10179 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10179 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10179 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 10179 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10179 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 10179 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 90943500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 90943500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 90943500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 90943500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 90943500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 90943500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.273673 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.273673 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.273658 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.273658 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.273658 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8934.423814 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 108224 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 12.929654 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 137412 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 108239 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.269524 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5100455706500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.929654 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808103 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.808103 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137417 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 137417 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137417 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 137417 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137417 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 137417 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109249 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 109249 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109249 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 109249 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109249 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 109249 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1361810000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1361810000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1361810000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 1361810000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1361810000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 1361810000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 246666 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 246666 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 246666 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 246666 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 246666 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 246666 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.442903 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.442903 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.442903 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.442903 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.442903 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.442903 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12465.194189 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.194189 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.194189 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12465.194189 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 34685 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 34685 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109249 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109249 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109249 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 109249 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109249 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 109249 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1143312000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1143312000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1143312000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442903 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.442903 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.442903 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442903 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10465.194189 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1662857 # number of replacements
system.cpu.dcache.tagsinuse 511.994597 # Cycle average of tags in use
system.cpu.dcache.total_refs 19099158 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1663369 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.482214 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.994597 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 11001158 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11001158 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8092803 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8092803 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19093961 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19093961 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19093961 # number of overall hits
system.cpu.dcache.overall_hits::total 19093961 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2250786 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2250786 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 319407 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 319407 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2570193 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2570193 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2570193 # number of overall misses
system.cpu.dcache.overall_misses::total 2570193 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32047872500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32047872500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644777995 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9644777995 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41692650495 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41692650495 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41692650495 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41692650495 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13251944 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13251944 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8412210 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8412210 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21664154 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21664154 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21664154 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21664154 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169846 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.169846 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037969 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037969 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.118638 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.118638 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118638 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118638 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14238.524898 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14238.524898 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30195.887989 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30195.887989 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16221.603006 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16221.603006 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16221.603006 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 397855 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 42661 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.325965 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1564276 # number of writebacks
system.cpu.dcache.writebacks::total 1564276 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 877119 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 877119 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25009 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25009 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 902128 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 902128 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 902128 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 902128 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1373667 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1373667 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294398 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 294398 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1668065 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1668065 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1668065 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1668065 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17358648500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17358648500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800545995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800545995 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26159194495 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26159194495 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26159194495 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26159194495 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296699500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296699500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470652500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470652500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767352000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767352000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034997 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034997 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076997 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076997 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076997 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076997 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.722364 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.722364 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29893.362030 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29893.362030 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15682.359198 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15682.359198 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15682.359198 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15682.359198 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 113558 # number of replacements
system.cpu.l2cache.tagsinuse 64830.425237 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3942801 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 177506 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.212213 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50104.773483 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 12.386832 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133410 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3229.258620 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 11483.872893 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.764538 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000189 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.049275 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.175230 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989234 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101071 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7595 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 1037956 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1335698 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2482320 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1600857 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1600857 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 332 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 332 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 156999 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 156999 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 101071 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 7595 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1037956 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1492697 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2639319 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 101071 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 7595 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1037956 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1492697 # number of overall hits
system.cpu.l2cache.overall_hits::total 2639319 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 16768 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 36730 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 53551 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3897 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3897 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133267 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133267 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 16768 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169997 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 186818 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 47 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 16768 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169997 # number of overall misses
system.cpu.l2cache.overall_misses::total 186818 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3237000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 711500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1007074500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2398448998 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3409471998 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17990000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 17990000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840285000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6840285000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3237000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 711500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1007074500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9238733998 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10249756998 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3237000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 711500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1007074500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9238733998 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10249756998 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101118 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7601 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1054724 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1372428 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2535871 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1600857 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1600857 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4229 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4229 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 290266 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 290266 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101118 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 7601 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1054724 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1662694 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2826137 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101118 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 7601 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1054724 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1662694 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2826137 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000465 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000789 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015898 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026763 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021117 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.921494 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.921494 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459120 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.459120 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000465 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000789 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015898 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102242 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.066104 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000465 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000789 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015898 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102242 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.066104 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68872.340426 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 118583.333333 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60059.309399 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65299.455432 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 63667.755934 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4616.371568 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4616.371568 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51327.673017 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51327.673017 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68872.340426 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 118583.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60059.309399 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54346.453161 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54864.932705 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68872.340426 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 118583.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60059.309399 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54346.453161 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54864.932705 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 102811 # number of writebacks
system.cpu.l2cache.writebacks::total 102811 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 47 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16767 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36728 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 53548 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3897 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3897 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133267 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133267 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 47 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16767 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169995 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 186815 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 47 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16767 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169995 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 186815 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2640091 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 634512 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 794953055 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1935935400 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2734163058 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 40037376 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 40037376 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5118804681 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5118804681 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2640091 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 634512 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 794953055 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7054740081 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7852967739 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2640091 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 634512 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 794953055 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7054740081 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7852967739 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187414000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187414000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308511500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308511500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495925500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495925500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026761 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921494 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921494 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459120 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.066103 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.066103 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 105752 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47411.764478 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52710.068613 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51060.040674 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10273.896844 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10273.896844 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38410.144154 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38410.144154 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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