path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.126140                       # Number of seconds simulated
sim_ticks                                5126139641000                       # Number of ticks simulated
final_tick                               5126139641000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128755                       # Simulator instruction rate (inst/s)
host_op_rate                                   254500                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1618610313                       # Simulator tick rate (ticks/s)
host_mem_usage                                 809248                       # Number of bytes of host memory used
host_seconds                                  3167.00                       # Real time elapsed on the host
sim_insts                                   407767906                       # Number of instructions simulated
sim_ops                                     806002026                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1038720                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10766272                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11837632                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1038720                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1038720                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9565696                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9565696                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16230                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168223                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                184963                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149464                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149464                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               202632                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2100269                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5531                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2309268                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          202632                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             202632                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1866062                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1866062                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1866062                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           762                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              202632                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2100269                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5531                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4175331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        184963                       # Number of read requests accepted
system.physmem.writeReqs                       149464                       # Number of write requests accepted
system.physmem.readBursts                      184963                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     149464                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11826048                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11584                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9564672                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11837632                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9565696                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      181                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48781                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               12059                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11374                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11651                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11200                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11713                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11071                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11625                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11816                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11540                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11598                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11427                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11449                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11382                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12463                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11321                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11093                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10213                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9339                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9470                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9072                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9457                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9178                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9173                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8997                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8928                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9204                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9473                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8827                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9527                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9857                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9294                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9439                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           9                       # Number of times write queue was full causing retry
system.physmem.totGap                    5126139591500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  184963                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149464                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170238                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11784                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1972                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       468                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2243                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7778                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7827                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7815                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     9638                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11733                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9934                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8512                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8974                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9035                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7803                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7671                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       94                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       62                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       46                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       39                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        71880                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      297.588425                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.048684                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     320.988013                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27629     38.44%     38.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17400     24.21%     62.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7428     10.33%     72.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4118      5.73%     78.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2845      3.96%     82.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1999      2.78%     85.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1307      1.82%     87.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1141      1.59%     88.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8013     11.15%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          71880                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7347                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.150402                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      560.379075                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7346     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7347                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7347                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.341364                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.592949                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.054942                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6299     85.74%     85.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              77      1.05%     86.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             192      2.61%     89.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              82      1.12%     90.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             130      1.77%     92.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             203      2.76%     95.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              23      0.31%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               7      0.10%     95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               7      0.10%     95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.11%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               4      0.05%     95.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               6      0.08%     95.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             243      3.31%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               7      0.10%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.12%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              11      0.15%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.01%     99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.01%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             7      0.10%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            16      0.22%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7347                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1972823732                       # Total ticks spent queuing
system.physmem.totMemAccLat                5437486232                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    923910000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10676.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29426.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.31                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     152120                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110229                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.32                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.75                       # Row buffer hit rate for writes
system.physmem.avgGap                     15328127.19                       # Average gap between requests
system.physmem.pageHitRate                      78.49                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  270149040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  147402750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 721570200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                485345520                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           334814035920                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           129415070025                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2962157471250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3428011044705                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.732438                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4927750166228                       # Time in different power states
system.physmem_0.memoryStateTime::REF    171172820000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27209465022                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  273263760                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  149102250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 719721600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                483077520                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           334814035920                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           129328302060                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2962233583500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3428001086610                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.730496                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4927884080230                       # Time in different power states
system.physmem_1.memoryStateTime::REF    171172820000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     27082630770                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86515320                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86515320                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            846562                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79887008                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77941063                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.564128                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1538368                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             179519                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        448780162                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27109366                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      427484272                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86515320                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79479431                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     417767954                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1778202                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     144572                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                59542                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        198505                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          291                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8932158                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                424030                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4890                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          446169387                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.890848                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.050446                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                281281763     63.04%     63.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2130107      0.48%     63.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72126905     16.17%     79.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1545484      0.35%     80.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2095217      0.47%     80.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2290541      0.51%     81.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1479828      0.33%     81.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1850907      0.41%     81.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81368635     18.24%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            446169387                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192779                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.952547                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 23013230                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             265986736                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 147854773                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               8425547                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 889101                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              835878661                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 889101                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 26336765                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               222825660                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12982234                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 152266315                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              30869312                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              832551989                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                449261                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12787861                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 146326                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               14734321                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           994655089                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1807638707                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1111268111                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               319                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963888503                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 30766581                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             460676                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         463553                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43190500                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17070475                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10019861                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1311535                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1113253                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  827301854                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1181846                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 822527972                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            224018                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22481665                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33938360                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         142118                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     446169387                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.843533                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.419200                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           262457891     58.82%     58.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13818111      3.10%     61.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9771246      2.19%     64.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7528828      1.69%     65.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            73243364     16.42%     82.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4832116      1.08%     83.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72756563     16.31%     99.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1182673      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              578595      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       446169387                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2475977     76.35%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 605774     18.68%     95.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                161247      4.97%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            283294      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             794512938     96.59%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150315      0.02%     96.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                126079      0.02%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  84      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18183253      2.21%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9272009      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              822527972                       # Type of FU issued
system.cpu.iq.rate                           1.832808                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     3242998                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003943                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2094691886                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         850977244                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818130626                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                450                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          165                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              825487451                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     225                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1857982                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3083761                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14419                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13953                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1600409                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207227                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         67958                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 889101                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               204671978                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10002497                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           828483700                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            158761                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17070475                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10019861                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             692471                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 393140                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8758574                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13953                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         479614                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       507057                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               986671                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             821011839                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17813350                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1389357                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26873346                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83150160                       # Number of branches executed
system.cpu.iew.exec_stores                    9059996                       # Number of stores executed
system.cpu.iew.exec_rate                     1.829430                       # Inst execution rate
system.cpu.iew.wb_sent                      820539763                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818130791                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639922411                       # num instructions producing a value
system.cpu.iew.wb_consumers                1048802840                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.823010                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610146                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22357422                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1039727                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            857347                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    442798070                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.820247                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.674846                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    272013186     61.43%     61.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11121974      2.51%     63.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3639430      0.82%     64.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74586618     16.84%     81.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2447768      0.55%     82.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1626880      0.37%     82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1002961      0.23%     82.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70975924     16.03%     98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5383329      1.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    442798070                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407767906                       # Number of instructions committed
system.cpu.commit.committedOps              806002026                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22406164                       # Number of memory references committed
system.cpu.commit.loads                      13986712                       # Number of loads committed
system.cpu.commit.membars                      468149                       # Number of memory barriers committed
system.cpu.commit.branches                   82157432                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 734850257                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155439                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171613      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783160302     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144896      0.02%     97.21% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121618      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13984129      1.73%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8419452      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806002026                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5383329                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1265696040                       # The number of ROB reads
system.cpu.rob.rob_writes                  1660107630                       # The number of ROB writes
system.cpu.timesIdled                          283975                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2610775                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9803496536                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407767906                       # Number of Instructions Simulated
system.cpu.committedOps                     806002026                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.100577                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.100577                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.908614                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.908614                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1090426394                       # number of integer regfile reads
system.cpu.int_regfile_writes               654841654                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       165                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415713185                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321659378                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264880270                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 399890                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1655948                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995019                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18959511                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1656460                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.445801                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995019                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          204                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87653092                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87653092                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10818266                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10818266                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8075018                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8075018                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        63136                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         63136                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      18893284                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18893284                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18956420                       # number of overall hits
system.cpu.dcache.overall_hits::total        18956420                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1801440                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1801440                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334795                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334795                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406500                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406500                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2136235                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2136235                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2542735                       # number of overall misses
system.cpu.dcache.overall_misses::total       2542735                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  26875877500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  26875877500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  13801276738                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  13801276738                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  40677154238                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  40677154238                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  40677154238                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  40677154238                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12619706                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12619706                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8409813                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8409813                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       469636                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       469636                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21029519                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21029519                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21499155                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21499155                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142748                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142748                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039810                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039810                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865564                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.865564                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101583                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101583                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118271                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118271                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14919.107769                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14919.107769                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.067065                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.067065                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19041.516611                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19041.516611                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15997.402104                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15997.402104                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       467524                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           95                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             52009                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.989290                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           95                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1557810                       # number of writebacks
system.cpu.dcache.writebacks::total           1557810                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       835579                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       835579                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44644                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44644                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       880223                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       880223                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       880223                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       880223                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       965861                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       965861                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290151                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290151                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403017                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       403017                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1256012                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1256012                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1659029                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1659029                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13873                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13873                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616769                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       616769                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13275179500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  13275179500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12396951239                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12396951239                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6045548500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6045548500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25672130739                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25672130739                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31717679239                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31717679239                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793653500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793653500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2614977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2614977500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100408631000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100408631000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076536                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076536                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034501                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034501                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858148                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858148                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059726                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059726                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077167                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077167                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.399556                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.399556                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42725.860807                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42725.860807                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15000.728257                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15000.728257                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20439.399257                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20439.399257                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19118.218692                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19118.218692                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.505766                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.505766                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188494.017156                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188494.017156                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.791394                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.791394                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        71018                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.855051                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       110090                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        71033                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.549843                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 197734009500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.855051                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.990941                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.990941                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       436469                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       436469                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       110104                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       110104                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       110104                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       110104                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       110104                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       110104                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        72087                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        72087                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        72087                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        72087                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        72087                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        72087                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    888705500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    888705500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    888705500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    888705500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    888705500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    888705500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       182191                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       182191                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       182191                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       182191                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       182191                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       182191                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395667                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395667                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395667                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395667                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12328.235327                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12328.235327                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12328.235327                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12328.235327                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        17880                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        17880                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        72087                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        72087                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        72087                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        72087                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        72087                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        72087                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    816618500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    816618500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    816618500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    816618500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395667                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395667                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395667                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395667                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11328.235327                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11328.235327                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11328.235327                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11328.235327                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            972475                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.589862                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7892622                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            972987                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.111745                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147937650500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.589862                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995293                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995293                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          274                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          134                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9905522                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9905522                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7892622                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7892622                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7892622                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7892622                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7892622                       # number of overall hits
system.cpu.icache.overall_hits::total         7892622                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1039533                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1039533                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1039533                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1039533                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1039533                       # number of overall misses
system.cpu.icache.overall_misses::total       1039533                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14506630997                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14506630997                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14506630997                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14506630997                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14506630997                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14506630997                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8932155                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8932155                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8932155                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8932155                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8932155                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8932155                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116381                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116381                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116381                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116381                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116381                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116381                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13954.949960                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13954.949960                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13954.949960                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13954.949960                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13954.949960                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13954.949960                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6454                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           21                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               314                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    20.554140                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           21                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66166                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        66166                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        66166                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        66166                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        66166                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        66166                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       973367                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       973367                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       973367                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       973367                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       973367                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       973367                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12880264497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12880264497                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12880264497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12880264497                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12880264497                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12880264497                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108973                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108973                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108973                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108973                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13232.690750                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13232.690750                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13232.690750                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13232.690750                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        13962                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.017494                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        24005                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        13975                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.717710                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5100174829000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.017494                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376093                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376093                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        92555                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        92555                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24014                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        24014                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24016                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        24016                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24016                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        24016                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14841                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        14841                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14841                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        14841                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14841                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        14841                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    170100000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    170100000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    170100000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    170100000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    170100000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    170100000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38855                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        38855                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38857                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        38857                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38857                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        38857                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.381959                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.381959                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.381939                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.381939                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.381939                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.381939                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11461.491813                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11461.491813                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11461.491813                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11461.491813                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11461.491813                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11461.491813                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         2319                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         2319                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14841                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14841                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14841                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        14841                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14841                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        14841                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    155259000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    155259000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    155259000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    155259000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    155259000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    155259000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.381959                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.381959                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.381939                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.381939                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.381939                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.381939                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10461.491813                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10461.491813                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10461.491813                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10461.491813                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112328                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64826.279220                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4884469                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176125                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.732968                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50541.510277                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    13.632944                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.140332                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3105.306836                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.688831                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.771202                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000208                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047383                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.170375                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989171                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63797                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          708                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3407                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5556                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54082                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.973465                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43431157                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43431157                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1578009                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1578009                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          321                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          321                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154224                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154224                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       956701                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       956701                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        65553                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12091                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332425                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1410069                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        65553                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12091                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       956701                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1486649                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2520994                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        65553                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12091                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       956701                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1486649                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2520994                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1786                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1786                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133488                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133488                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16231                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16231                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           61                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            6                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35709                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35776                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16231                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169197                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185495                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           61                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16231                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169197                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185495                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23220500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     23220500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10274230500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10274230500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1348223000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1348223000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      5829000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       513000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3059963500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3066305500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5829000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       513000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1348223000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13334194000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  14688759000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5829000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       513000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1348223000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13334194000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  14688759000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1578009                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1578009                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2107                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2107                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287712                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287712                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       972932                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       972932                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        65614                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12097                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1368134                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1445845                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        65614                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12097                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       972932                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1655846                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2706489                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        65614                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12097                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       972932                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1655846                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2706489                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.847651                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.847651                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463964                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.463964                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016683                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016683                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000496                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026101                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024744                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000496                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016683                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102182                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068537                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000930                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000496                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016683                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102182                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068537                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13001.399776                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13001.399776                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76967.446512                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76967.446512                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83064.691023                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83064.691023                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        85500                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85691.660366                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85708.449799                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        85500                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83064.691023                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78808.690461                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79186.819052                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 95557.377049                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        85500                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83064.691023                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78808.690461                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79186.819052                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102797                       # number of writebacks
system.cpu.l2cache.writebacks::total           102797                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            3                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            3                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          107                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          107                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1786                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1786                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133488                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133488                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16230                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16230                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            6                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35706                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35773                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16230                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169194                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185491                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16230                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169194                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185491                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13873                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13873                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616769                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616769                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37836000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37836000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8939350500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8939350500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1185827000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1185827000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       453000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2703742500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2709414500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       453000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1185827000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11643093000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12834592000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5219000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       453000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1185827000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11643093000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12834592000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257448500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257448500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2455427500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2455427500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92712876000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92712876000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.847651                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.847651                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463964                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463964                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016682                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026098                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024742                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102180                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068536                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000930                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000496                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016682                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102180                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068536                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21184.770437                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21184.770437                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66967.446512                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66967.446512                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73063.894023                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75722.357587                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75739.090935                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68815.046633                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69192.532252                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 85557.377049                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        75500                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73063.894023                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68815.046633                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69192.532252                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.497472                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.497472                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176993.260290                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176993.260290                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.259287                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.259287                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         602896                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3032324                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13873                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13873                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1727482                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      1093519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2562                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2562                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287721                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       973367                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1456602                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1641                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2917513                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6205490                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31703                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       168231                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9322937                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62267648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207474745                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       922624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5343616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          276008633                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      220316                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6258702                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.033424                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.179742                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            6049509     96.66%     96.66% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             209193      3.34%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6258702                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4609709481                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       573000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1461362367                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3096027096                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      22269484                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     108175907                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               222102                       # Transaction distribution
system.iobus.trans_dist::ReadResp              222102                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57708                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57708                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1641                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1641                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       464350                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3282                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3282                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  562902                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       238452                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3272880                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3911656                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           242679087                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           453362000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50182000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1641000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47580                       # number of replacements
system.iocache.tags.tagsinuse                0.091366                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4993241946000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.091366                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005710                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.005710                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428715                       # Number of tag accesses
system.iocache.tags.data_accesses              428715                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          915                       # number of demand (read+write) misses
system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
system.iocache.overall_misses::total              915                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    143595677                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    143595677                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5513463410                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5513463410                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    143595677                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    143595677                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    143595677                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    143595677                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          915                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             915                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          915                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            915                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 156935.166120                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.775043                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118010.775043                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 156935.166120                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156935.166120                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 156935.166120                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          915                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     97845677                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3177463410                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3177463410                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     97845677                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97845677                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     97845677                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 106935.166120                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.775043                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.775043                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 106935.166120                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106935.166120                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 106935.166120                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              602896                       # Transaction distribution
system.membus.trans_dist::ReadResp             655806                       # Transaction distribution
system.membus.trans_dist::WriteReq              13873                       # Transaction distribution
system.membus.trans_dist::WriteResp             13873                       # Transaction distribution
system.membus.trans_dist::Writeback            149464                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9883                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2535                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2080                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133195                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133194                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         52918                       # Transaction distribution
system.membus.trans_dist::MessageReq             1641                       # Transaction distribution
system.membus.trans_dist::MessageResp            1641                       # Transaction distribution
system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3282                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3282                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464350                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769188                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       486631                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1720185                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141820                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1865287                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6564                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238452                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538373                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18388288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20165113                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23186717                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1616                       # Total snoops (count)
system.membus.snoop_fanout::samples           1013692                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001619                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040202                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 1012051     99.84%     99.84% # Request fanout histogram
system.membus.snoop_fanout::2                    1641      0.16%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             1013692                       # Request fanout histogram
system.membus.reqLayer0.occupancy           354973500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388325000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3282000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1016908044                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                9500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1641000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2204699193                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           86072153                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------