path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.144266                       # Number of seconds simulated
sim_ticks                                5144265998000                       # Number of ticks simulated
final_tick                               5144265998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 171354                       # Simulator instruction rate (inst/s)
host_op_rate                                   338701                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2161855241                       # Simulator tick rate (ticks/s)
host_mem_usage                                 817304                       # Number of bytes of host memory used
host_seconds                                  2379.56                       # Real time elapsed on the host
sim_insts                                   407746267                       # Number of instructions simulated
sim_ops                                     805959101                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1040896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10728128                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11801664                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1040896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1040896                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9535488                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9535488                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16264                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167627                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                184401                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148992                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148992                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            771                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               202341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2085454                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5511                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2294140                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          202341                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             202341                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1853615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1853615                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1853615                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           771                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              202341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2085454                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5511                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4147754                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        184401                       # Number of read requests accepted
system.physmem.writeReqs                       148992                       # Number of write requests accepted
system.physmem.readBursts                      184401                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     148992                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11790400                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11264                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9534208                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11801664                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9535488                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      176                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48430                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11512                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10865                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12624                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11646                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11360                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11063                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11424                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11380                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11354                       # Per bank write bursts
system.physmem.perBankRdBursts::9               10854                       # Per bank write bursts
system.physmem.perBankRdBursts::10              10623                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11335                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12163                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12460                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11874                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11688                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9762                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9087                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9770                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9357                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9485                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8994                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9154                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8718                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8812                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9056                       # Per bank write bursts
system.physmem.perBankWrBursts::10               8954                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9300                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9801                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9709                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9528                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9485                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
system.physmem.totGap                    5144265948500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  184401                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148992                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    169976                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11589                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1867                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        53                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2270                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8228                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     8294                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     9520                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8743                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9904                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    10060                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7460                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      152                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      120                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      170                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      122                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       21                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        73109                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      291.681517                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.230147                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     313.360710                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          28156     38.51%     38.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17755     24.29%     62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7676     10.50%     73.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4351      5.95%     79.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2926      4.00%     83.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2405      3.29%     86.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1356      1.85%     88.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1112      1.52%     89.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7372     10.08%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          73109                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7269                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.343238                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      563.383377                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7268     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7269                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7269                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.494153                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.676401                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       12.977803                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6209     85.42%     85.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             177      2.43%     87.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              31      0.43%     88.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             190      2.61%     90.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              15      0.21%     91.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             151      2.08%     93.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             110      1.51%     94.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               9      0.12%     94.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              21      0.29%     95.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              27      0.37%     95.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               5      0.07%     95.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.07%     95.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             236      3.25%     98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.11%     98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               6      0.08%     99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              36      0.50%     99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               3      0.04%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             5      0.07%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.21%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7269                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2113024695                       # Total ticks spent queuing
system.physmem.totMemAccLat                5567243445                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    921125000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11469.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30219.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.39                       # Average write queue length when enqueuing
system.physmem.readRowHits                     150283                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109804                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.58                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.70                       # Row buffer hit rate for writes
system.physmem.avgGap                     15430035.87                       # Average gap between requests
system.physmem.pageHitRate                      78.05                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  271774440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  148289625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 716609400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                481638960                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           133079069070                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2969819271000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3440514616095                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.806670                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4940481054222                       # Time in different power states
system.physmem_0.memoryStateTime::REF    171778100000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     32006683778                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  280929600                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  153285000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 720337800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                483699600                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           335997963600                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           133106515425                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2969795195250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3440537926275                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.811201                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4940433568236                       # Time in different power states
system.physmem_1.memoryStateTime::REF    171778100000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32047173014                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86512376                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86512376                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            844809                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79880541                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77944216                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.575974                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1537356                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             178131                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        465431904                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27316222                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      427457339                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86512376                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79481572                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     433294653                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1774328                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     174290                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                61780                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        197089                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           61                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          797                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8939505                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                424296                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5201                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          461932056                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.826209                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.017418                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                297044979     64.30%     64.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2134462      0.46%     64.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72126640     15.61%     80.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1546779      0.33%     80.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2100235      0.45%     81.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2289900      0.50%     81.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1474676      0.32%     81.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1857009      0.40%     82.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81357376     17.61%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            461932056                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185875                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.918410                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 23107773                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             281695317                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 147794197                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               8447605                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 887164                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              835787144                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 887164                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 26441875                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               229504552                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       14337084                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 152214834                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              38546547                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              832466923                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                458085                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12798467                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 221946                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               22321415                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           994552862                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1807469855                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1111168371                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               379                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             963838514                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 30714343                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             460142                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         463176                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  43334873                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17067493                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10022220                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1319734                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1116337                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  827242342                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1181786                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 822485271                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            216558                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22465018                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33877646                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         141871                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     461932056                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.780533                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.400914                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           278202681     60.23%     60.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13844974      3.00%     63.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9781174      2.12%     65.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7532969      1.63%     66.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            73227075     15.85%     82.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4827596      1.05%     83.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72754467     15.75%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1183000      0.26%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              578120      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       461932056                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2482095     76.42%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 605940     18.66%     95.07% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                160087      4.93%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            284904      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             794458238     96.59%     96.63% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149904      0.02%     96.65% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                126188      0.02%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 113      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18188915      2.21%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9277009      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              822485271                       # Type of FU issued
system.cpu.iq.rate                           1.767144                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     3248122                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003949                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2110366769                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         850901074                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818087590                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 508                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                586                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          178                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              825448239                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     250                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1862376                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3081864                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14686                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14021                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1600056                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207186                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         68323                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 887164                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               205274699                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              15795611                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           828424128                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            165882                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17067493                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10022220                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             692366                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 393655                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              14549719                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14021                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         476392                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506422                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               982814                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             820971747                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17818623                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1389098                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26886211                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83147027                       # Number of branches executed
system.cpu.iew.exec_stores                    9067588                       # Number of stores executed
system.cpu.iew.exec_rate                     1.763892                       # Inst execution rate
system.cpu.iew.wb_sent                      820497311                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818087768                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639862073                       # num instructions producing a value
system.cpu.iew.wb_consumers                1048693225                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.757696                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610152                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22343285                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1039914                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            855258                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    458562995                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.757576                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.649246                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    287777749     62.76%     62.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11132608      2.43%     65.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3641047      0.79%     65.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74579710     16.26%     82.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2448796      0.53%     82.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1627078      0.35%     83.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1001834      0.22%     83.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70969693     15.48%     98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5384480      1.17%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    458562995                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407746267                       # Number of instructions committed
system.cpu.commit.committedOps              805959101                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22407791                       # Number of memory references committed
system.cpu.commit.loads                      13985627                       # Number of loads committed
system.cpu.commit.membars                      468163                       # Number of memory barriers committed
system.cpu.commit.branches                   82155343                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 734813827                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155420                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171757      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783115943     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144574      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121605      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13983042      1.73%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8422164      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         805959101                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5384480                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1281402583                       # The number of ROB reads
system.cpu.rob.rob_writes                  1659991505                       # The number of ROB writes
system.cpu.timesIdled                          284256                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3499848                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9823097505                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407746267                       # Number of Instructions Simulated
system.cpu.committedOps                     805959101                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.141474                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.141474                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.876060                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.876060                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1090398458                       # number of integer regfile reads
system.cpu.int_regfile_writes               654801015                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       178                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415698435                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321644299                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264872577                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400155                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1656886                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.993571                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18963252                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1657398                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.441580                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.993571                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87668549                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87668549                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10819943                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10819943                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8077328                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8077328                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        63083                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         63083                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      18897271                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18897271                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18960354                       # number of overall hits
system.cpu.dcache.overall_hits::total        18960354                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1800618                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1800618                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       335187                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       335187                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406619                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406619                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2135805                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2135805                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2542424                       # number of overall misses
system.cpu.dcache.overall_misses::total       2542424                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29915350500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29915350500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21131383234                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21131383234                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  51046733734                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  51046733734                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  51046733734                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  51046733734                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12620561                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12620561                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8412515                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8412515                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       469702                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       469702                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21033076                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21033076                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21502778                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21502778                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142673                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142673                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039844                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039844                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865696                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.865696                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101545                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101545                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118237                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118237                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16613.935049                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16613.935049                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63043.564440                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63043.564440                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23900.465508                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23900.465508                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20077.978234                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20077.978234                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       549742                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             52309                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.509511                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1559463                       # number of writebacks
system.cpu.dcache.writebacks::total           1559463                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       834370                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       834370                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44863                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44863                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       879233                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       879233                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       879233                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       879233                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       966248                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       966248                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290324                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290324                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403128                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       403128                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1256572                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1256572                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1659700                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1659700                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602897                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       602897                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13882                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13882                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616779                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       616779                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14275238000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  14275238000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19179377736                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19179377736                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6821935500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6821935500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33454615736                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  33454615736                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40276551236                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  40276551236                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793888500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793888500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2616393000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2616393000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100410281500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100410281500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076561                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034511                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034511                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858263                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858263                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059743                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059743                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077185                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077185                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        86946                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.839570                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        92503                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        86961                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.063730                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.839570                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.989973                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.989973                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       449092                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       449092                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92507                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92507                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92507                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92507                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92507                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92507                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        88026                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        88026                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        88026                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        88026                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        88026                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        88026                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1095128000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1095128000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1095128000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1095128000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1095128000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1095128000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       180533                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       180533                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       180533                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       180533                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       180533                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       180533                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.487590                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.487590                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.487590                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.487590                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        22750                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        22750                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        88026                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        88026                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        88026                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        88026                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        88026                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        88026                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1007102000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1007102000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1007102000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1007102000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.487590                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.487590                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.487590                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.487590                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            979952                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.399185                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7892668                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            980464                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.049931                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      150322947500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.399185                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994920                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994920                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          274                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          128                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9920034                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9920034                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7892668                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7892668                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7892668                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7892668                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7892668                       # number of overall hits
system.cpu.icache.overall_hits::total         7892668                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1046827                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1046827                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1046827                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1046827                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1046827                       # number of overall misses
system.cpu.icache.overall_misses::total       1046827                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15679887484                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15679887484                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15679887484                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15679887484                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15679887484                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15679887484                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8939495                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8939495                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8939495                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8939495                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8939495                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8939495                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.117101                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.117101                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.117101                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.117101                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.117101                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.117101                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14978.489745                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14978.489745                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        13392                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          244                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               457                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    29.304158                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    81.333333                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66288                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        66288                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        66288                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        66288                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        66288                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        66288                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       980539                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       980539                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       980539                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       980539                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       980539                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       980539                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13806283989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13806283989                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13806283989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13806283989                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13806283989                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13806283989                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109686                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.109686                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109686                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.109686                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        19284                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.025119                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        17613                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        19298                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     0.912685                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.025119                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376570                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376570                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        95741                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        95741                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        17618                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        17618                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        17620                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        17620                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        17620                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        17620                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        20167                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        20167                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        20167                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        20167                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        20167                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        20167                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    233184000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    233184000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    233184000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    233184000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    233184000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    233184000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        37785                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        37785                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        37787                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        37787                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        37787                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        37787                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.533730                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.533730                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.533702                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.533702                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.533702                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.533702                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         3197                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         3197                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        20167                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        20167                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        20167                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        20167                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        20167                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        20167                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    213017000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    213017000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    213017000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    213017000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    213017000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    213017000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.533730                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.533730                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.533702                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.533702                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.533702                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.533702                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111670                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64798.131266                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4919632                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           175949                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.960557                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.940071                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139536                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3193.810391                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.770836                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000167                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048734                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.169002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.988741                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64279                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          676                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3413                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5955                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54192                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.980820                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43682151                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43682151                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1585410                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1585410                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          346                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          346                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       155314                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       155314                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       964131                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       964131                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        75809                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        15497                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332951                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1424257                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        75809                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        15497                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       964131                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1488265                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2543702                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        75809                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        15497                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       964131                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1488265                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2543702                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1462                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1462                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132872                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132872                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16267                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16267                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           62                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35699                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35766                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           62                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16267                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168571                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        184905                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           62                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16267                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168571                       # number of overall misses
system.cpu.l2cache.overall_misses::total       184905                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     58198000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     58198000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16980826000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16980826000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2184446000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2184446000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      9139000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       679500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4828291000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   4838109500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9139000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       679500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2184446000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  21809117000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  24003381500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9139000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       679500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2184446000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  21809117000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  24003381500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1585410                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1585410                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1808                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1808                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288186                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288186                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       980398                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       980398                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        75871                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        15502                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1368650                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1460023                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        75871                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        15502                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       980398                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1656836                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2728607                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        75871                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        15502                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       980398                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1656836                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2728607                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.808628                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.808628                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.461063                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.461063                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016592                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016592                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000817                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000323                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026083                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024497                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000817                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000323                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016592                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101743                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067765                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000817                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000323                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016592                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101743                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067765                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39807.113543                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39807.113543                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127798.377386                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127798.377386                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134286.961333                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134286.961333                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147403.225806                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       135900                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135250.035015                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135271.193312                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147403.225806                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       135900                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134286.961333                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129376.446720                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 129814.669695                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147403.225806                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       135900                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134286.961333                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129376.446720                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 129814.669695                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102325                       # number of writebacks
system.cpu.l2cache.writebacks::total           102325                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            2                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          104                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          104                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1462                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1462                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132872                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132872                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16264                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16264                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           62                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35697                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35764                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16264                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168569                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       184900                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           62                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16264                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168569                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       184900                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602897                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602897                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13882                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13882                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616779                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616779                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    104470500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    104470500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15652106000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15652106000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2021465000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2021465000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       629500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4471847000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4480995500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       629500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2021465000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20123953000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  22154566500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8519000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       629500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2021465000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20123953000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  22154566500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257667000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257667000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2456737500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2456737500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92714404500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92714404500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808628                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808628                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461063                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461063                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016589                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026082                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024496                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101742                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067764                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000817                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000323                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016589                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101742                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067764                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       125900                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5491514                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2726446                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        94920                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1211                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1211                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         602897                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3061240                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13882                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13882                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1734407                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      1095490                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2269                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2269                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       288196                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       288196                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       980539                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1478351                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1645                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2939753                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6208049                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        41124                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       194511                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9383437                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62745472                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207643157                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1196736                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      6311744                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          277897109                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      226924                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6316816                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.030269                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.203509                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            6163711     97.58%     97.58% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             115005      1.82%     99.40% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              38100      0.60%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6316816                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4646513967                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       659789                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1472350908                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3097364534                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      30265969                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     132091893                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               222097                       # Transaction distribution
system.iobus.trans_dist::ReadResp              222097                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57711                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57711                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1645                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1645                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       464358                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3290                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3290                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  562906                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       238456                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6580                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3272852                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3921096                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                77000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           241306768                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           453367000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1645000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47574                       # number of replacements
system.iocache.tags.tagsinuse                0.116041                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4999338704000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116041                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007253                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007253                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
system.iocache.tags.data_accesses              428661                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
system.iocache.overall_misses::total              909                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144457672                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144457672                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6056832096                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6056832096                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    144457672                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    144457672                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    144457672                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    144457672                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 158919.331133                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 158919.331133                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 158919.331133                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           604                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   52                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.615385                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     99007672                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3720832096                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3720832096                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     99007672                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     99007672                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     99007672                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 108919.331133                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 108919.331133                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              602897                       # Transaction distribution
system.membus.trans_dist::ReadResp             655826                       # Transaction distribution
system.membus.trans_dist::WriteReq              13882                       # Transaction distribution
system.membus.trans_dist::WriteResp             13882                       # Transaction distribution
system.membus.trans_dist::Writeback            148992                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9700                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2190                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1729                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132608                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132605                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         52937                       # Transaction distribution
system.membus.trans_dist::MessageReq             1645                       # Transaction distribution
system.membus.trans_dist::MessageResp            1645                       # Transaction distribution
system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3290                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3290                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464358                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769200                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       484156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1717730                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141814                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1862834                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6580                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238456                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538397                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18322112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20098965                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23120585                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1616                       # Total snoops (count)
system.membus.snoop_fanout::samples           1012128                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001625                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040282                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 1010483     99.84%     99.84% # Request fanout histogram
system.membus.snoop_fanout::2                    1645      0.16%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             1012128                       # Request fanout histogram
system.membus.reqLayer0.occupancy           355014500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388301500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3290000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1012808227                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               10000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1645000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2201176288                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           86060868                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------