blob: 8fd17006a0cd8a3b20ef24aacdced52e140eeb58 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
|
---------- Begin Simulation Statistics ----------
sim_seconds 5.133932 # Number of seconds simulated
sim_ticks 5133932129000 # Number of ticks simulated
final_tick 5133932129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 157497 # Simulator instruction rate (inst/s)
host_op_rate 311329 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1982921852 # Simulator tick rate (ticks/s)
host_mem_usage 759792 # Number of bytes of host memory used
host_seconds 2589.07 # Real time elapsed on the host
sim_insts 407772261 # Number of instructions simulated
sim_ops 806052921 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2442496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1029568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10759232 # Number of bytes read from this memory
system.physmem.bytes_read::total 14235520 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1029568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1029568 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9509568 # Number of bytes written to this memory
system.physmem.bytes_written::total 9509568 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38164 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16087 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168113 # Number of read requests responded to by this memory
system.physmem.num_reads::total 222430 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 148587 # Number of write requests responded to by this memory
system.physmem.num_writes::total 148587 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 475755 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 200542 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2095710 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2772830 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 200542 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 200542 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1852297 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1852297 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1852297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 475755 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 200542 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2095710 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4625127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 222430 # Number of read requests accepted
system.physmem.writeReqs 148587 # Number of write requests accepted
system.physmem.readBursts 222430 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 148587 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 14231616 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3904 # Total number of bytes read from write queue
system.physmem.bytesWritten 9508480 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 14235520 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 9509568 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 61 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1723 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 14853 # Per bank write bursts
system.physmem.perBankRdBursts::1 13635 # Per bank write bursts
system.physmem.perBankRdBursts::2 14415 # Per bank write bursts
system.physmem.perBankRdBursts::3 13770 # Per bank write bursts
system.physmem.perBankRdBursts::4 14136 # Per bank write bursts
system.physmem.perBankRdBursts::5 13341 # Per bank write bursts
system.physmem.perBankRdBursts::6 13755 # Per bank write bursts
system.physmem.perBankRdBursts::7 13953 # Per bank write bursts
system.physmem.perBankRdBursts::8 13590 # Per bank write bursts
system.physmem.perBankRdBursts::9 13369 # Per bank write bursts
system.physmem.perBankRdBursts::10 13469 # Per bank write bursts
system.physmem.perBankRdBursts::11 13962 # Per bank write bursts
system.physmem.perBankRdBursts::12 14252 # Per bank write bursts
system.physmem.perBankRdBursts::13 14454 # Per bank write bursts
system.physmem.perBankRdBursts::14 13844 # Per bank write bursts
system.physmem.perBankRdBursts::15 13571 # Per bank write bursts
system.physmem.perBankWrBursts::0 10225 # Per bank write bursts
system.physmem.perBankWrBursts::1 9089 # Per bank write bursts
system.physmem.perBankWrBursts::2 9605 # Per bank write bursts
system.physmem.perBankWrBursts::3 9165 # Per bank write bursts
system.physmem.perBankWrBursts::4 9475 # Per bank write bursts
system.physmem.perBankWrBursts::5 8866 # Per bank write bursts
system.physmem.perBankWrBursts::6 9032 # Per bank write bursts
system.physmem.perBankWrBursts::7 9363 # Per bank write bursts
system.physmem.perBankWrBursts::8 8843 # Per bank write bursts
system.physmem.perBankWrBursts::9 8764 # Per bank write bursts
system.physmem.perBankWrBursts::10 9099 # Per bank write bursts
system.physmem.perBankWrBursts::11 9352 # Per bank write bursts
system.physmem.perBankWrBursts::12 9596 # Per bank write bursts
system.physmem.perBankWrBursts::13 9639 # Per bank write bursts
system.physmem.perBankWrBursts::14 9447 # Per bank write bursts
system.physmem.perBankWrBursts::15 9010 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 5133932076000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 222430 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 148587 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 174915 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 21440 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 6913 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2946 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2079 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1580 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1438 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1083 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 864 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 749 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 676 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 638 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 567 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 550 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 538 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 516 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 6034 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 6271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 6300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 6343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 6600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 6598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 6691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 7044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 7025 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 7044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 7124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 7641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 7124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 7239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 7407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 7483 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 69161 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 343.214933 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 150.395098 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 1078.627974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-67 31181 45.08% 45.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-131 10634 15.38% 60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-195 6892 9.97% 70.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-259 4363 6.31% 76.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-323 2774 4.01% 80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-387 2145 3.10% 83.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-451 1632 2.36% 86.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-515 1184 1.71% 87.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-579 1083 1.57% 89.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-643 997 1.44% 90.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-707 641 0.93% 91.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-771 593 0.86% 92.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-835 458 0.66% 93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-899 430 0.62% 93.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-963 348 0.50% 94.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1027 543 0.79% 95.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1091 251 0.36% 95.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1155 231 0.33% 95.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1219 148 0.21% 96.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1283 131 0.19% 96.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1347 159 0.23% 96.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1411 414 0.60% 97.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1475 146 0.21% 97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1539 132 0.19% 97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1603 102 0.15% 97.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1667 88 0.13% 97.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1731 59 0.09% 97.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1795 56 0.08% 98.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1859 31 0.04% 98.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1923 34 0.05% 98.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1987 24 0.03% 98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2051 33 0.05% 98.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2115 20 0.03% 98.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2179 49 0.07% 98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2243 19 0.03% 98.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2307 13 0.02% 98.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2371 10 0.01% 98.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2435 32 0.05% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2499 8 0.01% 98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2563 7 0.01% 98.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2691 29 0.04% 98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2755 12 0.02% 98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2819 12 0.02% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2883 3 0.00% 98.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2947 32 0.05% 98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3011 7 0.01% 98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3075 13 0.02% 98.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3139 8 0.01% 98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3203 25 0.04% 98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3267 5 0.01% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3395 4 0.01% 98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3459 26 0.04% 98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3523 2 0.00% 98.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3587 7 0.01% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3651 5 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3715 31 0.04% 98.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3779 9 0.01% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3907 7 0.01% 98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3971 28 0.04% 98.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4035 5 0.01% 98.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4099 17 0.02% 98.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4163 2 0.00% 98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4227 24 0.03% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4355 2 0.00% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4419 1 0.00% 98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4483 22 0.03% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4675 3 0.00% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4739 28 0.04% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4803 2 0.00% 99.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4931 2 0.00% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4995 23 0.03% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5059 3 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5123 3 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5187 3 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5251 26 0.04% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5443 1 0.00% 99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5507 22 0.03% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5571 5 0.01% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5635 4 0.01% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5699 2 0.00% 99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5763 26 0.04% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5827 3 0.00% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5955 1 0.00% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6019 25 0.04% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6083 6 0.01% 99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6147 3 0.00% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6211 5 0.01% 99.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 25 0.04% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6339 2 0.00% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 3 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 26 0.04% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6595 3 0.00% 99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 76 0.11% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6723 4 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6851 6 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 1 0.00% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7043 6 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7107 6 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7171 11 0.02% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7235 3 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7427 2 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7747 3 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8003 2 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8195 14 0.02% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8579 3 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9152-9155 3 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9792-9795 3 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9856-9859 4 0.01% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10112-10115 2 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10243 2 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11968-11971 3 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12096-12099 4 0.01% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12611 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12992-12995 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13440-13443 2 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13888-13891 6 0.01% 99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13955 2 0.00% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14211 3 0.00% 99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14272-14275 5 0.01% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14595 5 0.01% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14656-14659 3 0.00% 99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14720-14723 2 0.00% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14912-14915 20 0.03% 99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14976-14979 9 0.01% 99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15107 5 0.01% 99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15232-15235 3 0.00% 99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15296-15299 4 0.01% 99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15363 14 0.02% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15552-15555 4 0.01% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15683 5 0.01% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15808-15811 5 0.01% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15875 3 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16000-16003 3 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16131 2 0.00% 99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16192-16195 4 0.01% 99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16256-16259 9 0.01% 99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16320-16323 5 0.01% 99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16387 42 0.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 69161 # Bytes accessed per row activation
system.physmem.totQLat 5163279754 # Total ticks spent queuing
system.physmem.totMemAccLat 9388468504 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1111845000 # Total ticks spent in databus transfers
system.physmem.totBankLat 3113343750 # Total ticks spent accessing banks
system.physmem.avgQLat 23219.42 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 14000.80 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 42220.22 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.77 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.77 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing
system.physmem.readRowHits 193089 # Number of row buffer hits during reads
system.physmem.writeRowHits 108689 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
system.physmem.avgGap 13837457.79 # Average gap between requests
system.physmem.pageHitRate 81.35 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.14 # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput 5101771 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 662370 # Transaction distribution
system.membus.trans_dist::ReadResp 662362 # Transaction distribution
system.membus.trans_dist::WriteReq 13778 # Transaction distribution
system.membus.trans_dist::WriteResp 13778 # Transaction distribution
system.membus.trans_dist::Writeback 148587 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2227 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1742 # Transaction distribution
system.membus.trans_dist::ReadExReq 179504 # Transaction distribution
system.membus.trans_dist::ReadExResp 179502 # Transaction distribution
system.membus.trans_dist::MessageReq 1643 # Transaction distribution
system.membus.trans_dist::MessageResp 1643 # Transaction distribution
system.membus.trans_dist::BadAddressError 8 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475070 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721244 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132462 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 132462 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1856992 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18315904 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20107877 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5429184 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5429184 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 25543633 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 25543633 # Total data (bytes)
system.membus.snoop_data_through_bus 648512 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 250559500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 583301000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 1608447497 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 3153020380 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer4.occupancy 429468745 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 47576 # number of replacements
system.iocache.tags.tagsinuse 0.103982 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 4992954297000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103982 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
system.iocache.overall_misses::total 47631 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149420946 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 149420946 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11534885027 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 11534885027 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 11684305973 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 11684305973 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 11684305973 # number of overall miss cycles
system.iocache.overall_miss_latency::total 11684305973 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164018.601537 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 164018.601537 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 246893.943215 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 246893.943215 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 245308.852911 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 245308.852911 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 245308.852911 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 173314 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10321 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 16.792365 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102021946 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 102021946 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9103892537 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9103892537 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9205914483 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9205914483 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9205914483 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111988.963776 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111988.963776 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 194860.713549 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 194860.713549 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193275.691944 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 193275.691944 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.throughput 638153 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 225567 # Transaction distribution
system.iobus.trans_dist::ReadResp 225567 # Transaction distribution
system.iobus.trans_dist::WriteReq 57606 # Transaction distribution
system.iobus.trans_dist::WriteResp 57606 # Transaction distribution
system.iobus.trans_dist::MessageReq 1643 # Transaction distribution
system.iobus.trans_dist::MessageResp 1643 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 569632 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 3276232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3276232 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3917850 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 424362228 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 53078255 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.branchPred.lookups 85592238 # Number of BP lookups
system.cpu.branchPred.condPredicted 85592238 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 882873 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 79245732 # Number of BTB lookups
system.cpu.branchPred.BTBHits 77532748 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.838390 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1439092 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 180819 # Number of incorrect RAS predictions.
system.cpu.numCycles 453841851 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 25587982 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 422693278 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85592238 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 78971840 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 162652701 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3982002 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 104057 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 71419426 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 42857 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 89331 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 200 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 8481476 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 385696 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 2322 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 262951613 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.174902 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.411090 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 100714901 38.30% 38.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1542522 0.59% 38.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71823019 27.31% 66.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 902488 0.34% 66.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1566536 0.60% 67.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2391041 0.91% 68.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1017988 0.39% 68.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1324647 0.50% 68.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 81668471 31.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 262951613 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.188595 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.931367 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 29471400 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 68588335 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 158500700 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3336119 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3055059 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 832519072 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 997 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3055059 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 32166739 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 43365867 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 12492763 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 158788078 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 13083107 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 829619005 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 21424 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6060149 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 5145730 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 991238350 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1800229618 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1106821161 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 116 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 963974807 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 27263541 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 455448 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 461036 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 29565034 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 16718678 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 9823839 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1099301 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 921701 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 824848453 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1187045 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 820941370 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 145995 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 19149103 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 29112205 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 132366 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 262951613 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.122024 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.401319 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 76573555 29.12% 29.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15783174 6.00% 35.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10543493 4.01% 39.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7363188 2.80% 41.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 75733020 28.80% 70.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3745069 1.42% 72.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72294186 27.49% 99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 768319 0.29% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 147609 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 262951613 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 346888 33.04% 33.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 241 0.02% 33.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 2034 0.19% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.25% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 547279 52.12% 85.37% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 153573 14.63% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 309747 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 793469361 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 149710 0.02% 96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 124599 0.02% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 17668051 2.15% 98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9219902 1.12% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 820941370 # Type of FU issued
system.cpu.iq.rate 1.808871 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1050015 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001279 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1906138377 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 845194990 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 817033315 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 821681548 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1692176 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 2727781 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18489 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12047 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1402321 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1931655 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 11924 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3055059 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 31495600 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2151607 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 826035498 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 247681 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 16718678 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 9823839 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 691406 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1620111 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 12282 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12047 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 498908 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 509123 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1008031 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 819536653 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17366589 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1404716 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 26403509 # number of memory reference insts executed
system.cpu.iew.exec_branches 83090404 # Number of branches executed
system.cpu.iew.exec_stores 9036920 # Number of stores executed
system.cpu.iew.exec_rate 1.805776 # Inst execution rate
system.cpu.iew.wb_sent 819134916 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 817033367 # cumulative count of insts written-back
system.cpu.iew.wb_producers 638560375 # num instructions producing a value
system.cpu.iew.wb_consumers 1043850178 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.800260 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.611736 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 19875138 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1054679 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 892733 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 259896554 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 3.101438 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.863911 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 88349043 33.99% 33.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11862829 4.56% 38.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3832305 1.47% 40.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74754047 28.76% 68.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2383630 0.92% 69.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1474941 0.57% 70.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 857586 0.33% 70.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70848784 27.26% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5533389 2.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 259896554 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407772261 # Number of instructions committed
system.cpu.commit.committedOps 806052921 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 22412414 # Number of memory references committed
system.cpu.commit.loads 13990896 # Number of loads committed
system.cpu.commit.membars 474709 # Number of memory barriers committed
system.cpu.commit.branches 82160310 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 734896243 # Number of committed integer instructions.
system.cpu.commit.function_calls 1155289 # Number of function calls committed.
system.cpu.commit.bw_lim_events 5533389 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1080212949 # The number of ROB reads
system.cpu.rob.rob_writes 1654925831 # The number of ROB writes
system.cpu.timesIdled 1261862 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 190890238 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9814027971 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407772261 # Number of Instructions Simulated
system.cpu.committedOps 806052921 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407772261 # Number of Instructions Simulated
system.cpu.cpi 1.112979 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.112979 # CPI: Total CPI of All Threads
system.cpu.ipc 0.898490 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.898490 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1088746320 # number of integer regfile reads
system.cpu.int_regfile_writes 653799671 # number of integer regfile writes
system.cpu.fp_regfile_reads 52 # number of floating regfile reads
system.cpu.cc_regfile_reads 415603862 # number of cc regfile reads
system.cpu.cc_regfile_writes 321491324 # number of cc regfile writes
system.cpu.misc_regfile_reads 264059604 # number of misc regfile reads
system.cpu.misc_regfile_writes 402440 # number of misc regfile writes
system.cpu.toL2Bus.throughput 53738291 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 3018879 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3018337 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1585586 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2261 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2261 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 334835 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 288140 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919324 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6124632 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18318 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159709 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8221983 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61414400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207642981 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 603136 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5731328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 275391845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 275366117 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 522624 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4046374411 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 603000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1442983054 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3140518579 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 13344744 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 105297384 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 959142 # number of replacements
system.cpu.icache.tags.tagsinuse 509.299647 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 7468451 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 959654 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 7.782441 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 147611306250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 509.299647 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.994726 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.994726 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7468451 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7468451 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7468451 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7468451 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7468451 # number of overall hits
system.cpu.icache.overall_hits::total 7468451 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1013022 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1013022 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1013022 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1013022 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1013022 # number of overall misses
system.cpu.icache.overall_misses::total 1013022 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14172498740 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14172498740 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14172498740 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14172498740 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14172498740 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14172498740 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 8481473 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 8481473 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 8481473 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 8481473 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 8481473 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 8481473 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119439 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.119439 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.119439 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.119439 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.119439 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.119439 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13990.316834 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13990.316834 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13990.316834 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13990.316834 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13990.316834 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 172 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 26.023256 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53298 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 53298 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 53298 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 53298 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 53298 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 53298 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959724 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 959724 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 959724 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 959724 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 959724 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 959724 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11694537694 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11694537694 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11694537694 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11694537694 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11694537694 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11694537694 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113155 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.113155 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113155 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.113155 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12185.313376 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12185.313376 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12185.313376 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12185.313376 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements 8004 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 6.959011 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 21893 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 8020 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.729800 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5103903665500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.959011 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.434938 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.434938 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21891 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 21891 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21893 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 21893 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21893 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 21893 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8894 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 8894 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8894 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 8894 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8894 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 8894 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 101842497 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 101842497 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 101842497 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 101842497 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 101842497 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 101842497 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30785 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 30785 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30787 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 30787 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30787 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 30787 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.288907 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.288907 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.288888 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.288888 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.288888 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.288888 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11450.696762 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11450.696762 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11450.696762 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11450.696762 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11450.696762 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 2197 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 2197 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8894 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8894 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8894 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 8894 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 84047009 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 84047009 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 84047009 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 84047009 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 84047009 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 84047009 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.288907 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.288907 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.288888 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.288888 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.288888 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9449.854846 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9449.854846 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9449.854846 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 14.134079 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 90874 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.315737 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 4994243678000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.134079 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.883380 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.883380 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 90874 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 90874 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 90874 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 90874 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 90874 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 90874 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70157 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 70157 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70157 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 70157 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70157 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 70157 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 871654701 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 871654701 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 871654701 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 871654701 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 871654701 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 871654701 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161031 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 161031 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161031 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 161031 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161031 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 161031 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435674 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435674 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435674 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435674 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435674 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435674 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12424.343986 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12424.343986 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12424.343986 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12424.343986 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12424.343986 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 24645 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 24645 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70157 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70157 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70157 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 70157 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70157 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 70157 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 731216933 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 731216933 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 731216933 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 731216933 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 731216933 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 731216933 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435674 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435674 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435674 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435674 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10422.579828 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10422.579828 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10422.579828 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1657437 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.988912 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18989388 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1657949 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.453542 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 39724250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.988912 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999978 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999978 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10890920 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10890920 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8095777 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8095777 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 18986697 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18986697 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18986697 # number of overall hits
system.cpu.dcache.overall_hits::total 18986697 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2234479 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2234479 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 316198 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 316198 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2550677 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2550677 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2550677 # number of overall misses
system.cpu.dcache.overall_misses::total 2550677 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33004921637 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 33004921637 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12257889032 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 12257889032 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 45262810669 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 45262810669 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 45262810669 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 45262810669 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13125399 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13125399 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8411975 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8411975 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21537374 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21537374 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21537374 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21537374 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170241 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.170241 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037589 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037589 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.118430 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.118430 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118430 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118430 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14770.745949 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14770.745949 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38766.497676 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38766.497676 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17745.410598 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17745.410598 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17745.410598 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 397669 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 42042 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.458851 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1558744 # number of writebacks
system.cpu.dcache.writebacks::total 1558744 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864490 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 864490 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25919 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25919 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 890409 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 890409 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 890409 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 890409 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369989 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1369989 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290279 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 290279 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1660268 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1660268 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1660268 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1660268 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17836083706 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17836083706 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11362753211 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11362753211 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29198836917 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29198836917 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29198836917 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29198836917 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364613500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364613500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538583500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538583500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903197000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903197000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034508 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034508 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077088 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077088 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077088 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13019.143735 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13019.143735 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39144.248158 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39144.248158 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17586.821475 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17586.821475 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 111632 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64821.705622 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3786761 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 175570 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 21.568383 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50709.515998 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.756367 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126012 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3028.517183 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.790063 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.773766 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000118 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046212 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169003 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989101 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7222 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 943511 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1333169 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2348748 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1585586 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1585586 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 155047 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 155047 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 64846 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 7222 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 943511 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1488216 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2503795 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 64846 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 7222 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 943511 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1488216 # number of overall hits
system.cpu.l2cache.overall_hits::total 2503795 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 16089 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 36006 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 52161 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133062 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133062 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 16089 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169068 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 185223 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 16089 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169068 # number of overall misses
system.cpu.l2cache.overall_misses::total 185223 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5260500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1277797734 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2940044940 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4223492924 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17900790 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 17900790 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9477459899 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9477459899 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5260500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 1277797734 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12417504839 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 13700952823 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5260500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 1277797734 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12417504839 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 13700952823 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64907 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7227 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 959600 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1369175 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2400909 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1585586 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1585586 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1776 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1776 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 288109 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64907 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 7227 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 959600 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1657284 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2689018 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64907 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 7227 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 959600 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1657284 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2689018 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000940 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000692 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016766 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026298 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021726 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823198 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823198 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461846 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.461846 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000940 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000692 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016766 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102015 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.068881 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000940 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000692 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016766 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102015 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.068881 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86237.704918 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77950 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79420.581391 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81654.305949 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80970.321198 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12244.042408 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12244.042408 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71225.893937 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71225.893937 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73970.040562 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86237.704918 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77950 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79420.581391 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73446.807433 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73970.040562 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 101920 # number of writebacks
system.cpu.l2cache.writebacks::total 101920 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16087 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36005 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 52158 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1462 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1462 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133062 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133062 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16087 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169067 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 185220 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16087 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169067 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 185220 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4502000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075523016 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2491735810 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3572087076 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15586943 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15586943 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7807116101 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7807116101 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4502000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075523016 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10298851911 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11379203177 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4502000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075523016 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10298851911 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11379203177 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251387000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251387000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372677500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372677500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624064500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624064500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026297 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021724 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823198 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823198 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461846 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461846 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.068880 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000940 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000692 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016764 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102015 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.068880 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66856.655436 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69205.271768 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68485.890487 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.383721 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.383721 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.769844 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.769844 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73803.278689 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66856.655436 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60915.802084 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61436.147160 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|