path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.130109                       # Number of seconds simulated
sim_ticks                                5130108675000                       # Number of ticks simulated
final_tick                               5130108675000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 175723                       # Simulator instruction rate (inst/s)
host_op_rate                                   347336                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2210269457                       # Simulator tick rate (ticks/s)
host_mem_usage                                 810456                       # Number of bytes of host memory used
host_seconds                                  2321.03                       # Real time elapsed on the host
sim_insts                                   407858109                       # Number of instructions simulated
sim_ops                                     806179275                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1044544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10779584                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11857088                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1044544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1044544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9583168                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9583168                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           67                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16321                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168431                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                185267                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149737                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149737                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            836                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               203611                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2101239                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5527                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2311274                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          203611                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             203611                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1868024                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1868024                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1868024                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           836                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              203611                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2101239                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5527                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4179299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        185267                       # Number of read requests accepted
system.physmem.writeReqs                       149737                       # Number of write requests accepted
system.physmem.readBursts                      185267                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     149737                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11846656                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10432                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9581440                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11857088                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9583168                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      163                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48775                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11590                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11256                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12288                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11911                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11840                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11665                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10867                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10808                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11222                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11056                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11302                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11775                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11547                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12196                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11932                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11849                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10246                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9545                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9025                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8913                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9024                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9097                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8779                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8697                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8886                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9043                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9545                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9380                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9802                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9849                       # Per bank write bursts
system.physmem.perBankWrBursts::14              10052                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9827                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
system.physmem.totGap                    5130108625500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  185267                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149737                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170610                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11668                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2033                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        56                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        36                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2978                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7955                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7943                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7727                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7793                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     9624                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9979                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10405                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9975                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8508                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7701                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      257                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      195                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      134                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      150                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      163                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       93                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       42                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        9                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        72239                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      296.626919                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.108811                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     319.147383                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27668     38.30%     38.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17613     24.38%     62.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7498     10.38%     73.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4242      5.87%     78.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2823      3.91%     82.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1928      2.67%     85.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1515      2.10%     87.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1131      1.57%     89.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7821     10.83%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          72239                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7351                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.179159                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      561.374907                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7350     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7351                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7351                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.365937                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.603384                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.112022                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6287     85.53%     85.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              96      1.31%     86.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             185      2.52%     89.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              82      1.12%     90.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             111      1.51%     91.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             202      2.75%     94.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              31      0.42%     95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              14      0.19%     95.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              14      0.19%     95.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              10      0.14%     95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               9      0.12%     95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               5      0.07%     95.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             246      3.35%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               8      0.11%     99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               4      0.05%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               8      0.11%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               2      0.03%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             7      0.10%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.03%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            14      0.19%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.01%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             2      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             3      0.04%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7351                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1992019456                       # Total ticks spent queuing
system.physmem.totMemAccLat                5462719456                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    925520000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10761.62                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29511.62                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.87                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.79                       # Average write queue length when enqueuing
system.physmem.readRowHits                     151846                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110728                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.95                       # Row buffer hit rate for writes
system.physmem.avgGap                     15313574.24                       # Average gap between requests
system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  269393040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  146990250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 719355000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                475152480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           129448929735                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2964510370500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3430643592525                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.727957                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4931666056220                       # Time in different power states
system.physmem_0.memoryStateTime::REF    171305420000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27131976280                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  276733800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  150995625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 724448400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                494968320                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           335073401520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           129698055360                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2964291831000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3430710434025                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.740988                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4931307220986                       # Time in different power states
system.physmem_1.memoryStateTime::REF    171305420000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     27495924014                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86802866                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86802866                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            898884                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79915985                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78142205                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.780444                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1557172                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             181109                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        449354840                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27419696                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      428691862                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86802866                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79699377                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     417944649                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1884104                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     141232                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                57475                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        210217                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           60                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          747                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9135683                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                451645                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5364                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          446716128                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.893620                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.051973                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                281460190     63.01%     63.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2138894      0.48%     63.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72152839     16.15%     79.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1576063      0.35%     79.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2129707      0.48%     80.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2325949      0.52%     80.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1505469      0.34%     81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1859854      0.42%     81.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81567163     18.26%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            446716128                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.193172                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.954016                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 22817532                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             264818622                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150719822                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7418100                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 942052                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              837890793                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 942052                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25656597                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               222831809                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12884327                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154608390                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              29792953                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834381209                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                449377                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12218260                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 146025                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               14738284                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           996692347                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1812155414                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1113986633                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               357                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964101925                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32590420                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             461964                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         466029                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  38550499                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17267645                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10120270                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1295034                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1078818                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  828854264                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1188467                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823634023                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            239226                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23863451                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     35922872                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         148640                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     446716128                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.843753                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.418621                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           262749029     58.82%     58.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13824325      3.09%     61.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9784338      2.19%     64.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7058515      1.58%     65.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74344613     16.64%     82.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4389971      0.98%     83.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72797188     16.30%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1191150      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              576999      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       446716128                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1965794     71.96%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 607707     22.24%     94.20% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                158405      5.80%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            286388      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795396124     96.57%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150331      0.02%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                127202      0.02%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  98      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18333764      2.23%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9340116      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823634023                       # Type of FU issued
system.cpu.iq.rate                           1.832926                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2731906                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003317                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2096954851                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         853918294                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819080568                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 454                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                494                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          158                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              826079323                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     218                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1864091                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3276332                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        15288                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14318                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1695886                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207587                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         71306                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 942052                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               204779875                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               9950427                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           830042731                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            154301                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17267645                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10120270                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             698404                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 395340                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8703386                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14318                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         517416                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       531852                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1049268                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822011733                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17933627                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1492341                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27049256                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83240327                       # Number of branches executed
system.cpu.iew.exec_stores                    9115629                       # Number of stores executed
system.cpu.iew.exec_rate                     1.829315                       # Inst execution rate
system.cpu.iew.wb_sent                      821506514                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819080726                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640638640                       # num instructions producing a value
system.cpu.iew.wb_consumers                1049832937                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.822793                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610229                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        23734474                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1039827                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            910229                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    443141458                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.819237                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.674506                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    272292366     61.45%     61.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11181272      2.52%     63.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3605802      0.81%     64.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74611152     16.84%     81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2465682      0.56%     82.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1626284      0.37%     82.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       958421      0.22%     82.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70995563     16.02%     98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5404916      1.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    443141458                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407858109                       # Number of instructions committed
system.cpu.commit.committedOps              806179275                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22415696                       # Number of memory references committed
system.cpu.commit.loads                      13991312                       # Number of loads committed
system.cpu.commit.membars                      468143                       # Number of memory barriers committed
system.cpu.commit.branches                   82176077                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735014201                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155537                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171593      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783328307     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144946      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121298      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13988731      1.74%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8424384      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806179275                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5404916                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1267572015                       # The number of ROB reads
system.cpu.rob.rob_writes                  1663421472                       # The number of ROB writes
system.cpu.timesIdled                          288126                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2638712                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9810859930                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407858109                       # Number of Instructions Simulated
system.cpu.committedOps                     806179275                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.101743                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.101743                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.907653                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.907653                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1091670765                       # number of integer regfile reads
system.cpu.int_regfile_writes               655627629                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       158                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416000684                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321879904                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265310647                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400047                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1661478                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.997539                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19061070                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1661990                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.468824                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.997539                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          225                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          272                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88124232                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88124232                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10914055                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10914055                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8079827                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8079827                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64080                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64080                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      18993882                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18993882                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19057962                       # number of overall hits
system.cpu.dcache.overall_hits::total        19057962                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1815960                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1815960                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334906                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334906                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406730                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406730                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2150866                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2150866                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2557596                       # number of overall misses
system.cpu.dcache.overall_misses::total       2557596                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  27033028000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  27033028000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  13819339247                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  13819339247                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  40852367247                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  40852367247                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  40852367247                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  40852367247                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12730015                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12730015                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8414733                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8414733                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       470810                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       470810                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21144748                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21144748                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21615558                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21615558                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142652                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142652                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039800                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039800                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863894                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.863894                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101721                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101721                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118322                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118322                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14886.356528                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14886.356528                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41263.337316                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41263.337316                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18993.450660                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18993.450660                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15972.955559                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15972.955559                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       469124                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             51580                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.095076                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1562865                       # number of writebacks
system.cpu.dcache.writebacks::total           1562865                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       845003                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       845003                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44547                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44547                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       889550                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       889550                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       889550                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       889550                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       970957                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       970957                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290359                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290359                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       403239                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       403239                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1261316                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1261316                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1664555                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1664555                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13333994500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  13333994500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12420799750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12420799750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6058828500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6058828500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25754794250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25754794250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31813622750                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31813622750                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97793670000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97793670000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2615433000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2615433000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100409103000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100409103000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076273                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076273                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034506                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034506                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856479                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856479                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059652                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059652                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077007                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077007                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13732.837294                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13732.837294                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42777.388509                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42777.388509                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15025.403049                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15025.403049                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20418.986400                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20418.986400                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19112.389047                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19112.389047                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.533133                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.533133                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188499.675676                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188499.675676                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162798.028766                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162798.028766                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        72618                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    14.793557                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       113213                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        72633                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.558699                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5097094340500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.793557                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.924597                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.924597                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       447394                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       447394                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113219                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       113219                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113219                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       113219                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113219                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       113219                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        73652                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        73652                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        73652                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        73652                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        73652                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        73652                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    910717000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    910717000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    910717000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    910717000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    910717000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    910717000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       186871                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       186871                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       186871                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       186871                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       186871                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       186871                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.394133                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.394133                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.394133                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.394133                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12365.136045                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12365.136045                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12365.136045                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12365.136045                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        18815                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        18815                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        73652                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        73652                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        73652                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        73652                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        73652                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        73652                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    837065000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    837065000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    837065000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    837065000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.394133                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.394133                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.394133                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.394133                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11365.136045                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11365.136045                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11365.136045                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            991040                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.607437                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8073267                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            991552                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.142051                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147914027500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.607437                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.995327                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.995327                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          105                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10127588                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10127588                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8073267                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8073267                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8073267                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8073267                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8073267                       # number of overall hits
system.cpu.icache.overall_hits::total         8073267                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1062411                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1062411                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1062411                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1062411                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1062411                       # number of overall misses
system.cpu.icache.overall_misses::total       1062411                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14792091486                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14792091486                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14792091486                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14792091486                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14792091486                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14792091486                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9135678                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9135678                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9135678                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9135678                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9135678                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9135678                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116293                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116293                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116293                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116293                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116293                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116293                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.134725                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13923.134725                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13923.134725                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.134725                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13923.134725                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         7978                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               382                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    20.884817                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70501                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        70501                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        70501                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        70501                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        70501                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        70501                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991910                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       991910                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       991910                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       991910                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       991910                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       991910                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13114232487                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13114232487                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13114232487                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13114232487                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13114232487                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13114232487                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108575                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108575                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108575                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108575                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13221.191930                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13221.191930                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13221.191930                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        15565                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.022675                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        26231                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        15578                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.683849                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5102115273500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.022675                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.376417                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.376417                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            7                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses       101828                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses       101828                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26240                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        26240                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26242                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        26242                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26242                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        26242                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        16448                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        16448                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        16448                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        16448                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        16448                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        16448                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    193358500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    193358500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    193358500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    193358500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    193358500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    193358500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        42688                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        42688                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        42690                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        42690                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        42690                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        42690                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.385307                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.385307                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.385289                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.385289                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.385289                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.385289                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11755.745379                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11755.745379                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11755.745379                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11755.745379                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11755.745379                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         3018                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         3018                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        16448                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        16448                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        16448                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        16448                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        16448                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        16448                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    176910500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    176910500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    176910500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    176910500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    176910500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    176910500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.385307                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.385307                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.385289                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.385289                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.385289                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10755.745379                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10755.745379                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10755.745379                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112892                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64819.691770                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4938747                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176773                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.938356                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50529.309735                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.322898                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.136173                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3138.561208                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11131.361756                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.771016                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000310                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047891                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.169851                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989070                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63881                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          774                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3319                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5177                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54573                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.974747                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43864381                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43864381                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1584698                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1584698                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          310                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          310                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154215                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154215                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       975190                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       975190                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        67279                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        13917                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1337816                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1419012                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        67279                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        13917                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       975190                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1492031                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2548417                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        67279                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        13917                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       975190                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1492031                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2548417                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1787                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1787                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133737                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133737                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16323                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16323                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           67                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35675                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35747                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           67                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16323                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169412                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185807                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           67                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16323                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169412                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185807                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23917000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     23917000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10298204500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10298204500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1359330500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1359330500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      6177500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       415000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3065419500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3072012000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6177500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       415000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1359330500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13363624000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  14729547000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6177500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       415000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1359330500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13363624000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  14729547000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1584698                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1584698                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2097                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         2097                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287952                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287952                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       991513                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       991513                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        67346                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        13922                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1373491                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1454759                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        67346                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        13922                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       991513                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1661443                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2734224                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        67346                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        13922                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       991513                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1661443                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2734224                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.852170                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.852170                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.464442                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.464442                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016463                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016463                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000359                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.025974                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024572                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000359                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016463                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101967                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067956                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000995                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000359                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016463                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101967                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067956                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 13383.883604                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 13383.883604                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77003.405939                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77003.405939                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83277.001777                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83277.001777                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        83000                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85926.264891                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85937.617143                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83277.001777                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78882.393219                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79273.369679                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92201.492537                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        83000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83277.001777                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78882.393219                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79273.369679                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       103070                       # number of writebacks
system.cpu.l2cache.writebacks::total           103070                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           90                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total           90                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1787                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1787                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133737                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133737                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16321                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16321                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           67                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35671                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35743                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           67                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16321                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169408                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185801                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           67                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16321                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169408                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185801                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602896                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602896                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13875                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13875                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616771                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616771                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37875000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37875000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8960834500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8960834500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195971500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195971500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       365000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2711142000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2717014500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       365000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195971500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11671976500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12873820500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5507500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       365000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195971500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11671976500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12873820500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90257461500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90257461500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2455867500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2455867500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92713329000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92713329000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.852170                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.852170                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.464442                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.464442                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016461                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.025971                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024570                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067954                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000995                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000359                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016461                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101964                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067954                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21194.739787                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21194.739787                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67003.405939                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67003.405939                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73278.077324                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76004.092961                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76015.289707                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82201.492537                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        73000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73278.077324                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68898.614587                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69288.219654                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.519035                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.519035                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176999.459459                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176999.459459                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.506314                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.506314                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         602896                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3059319                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13875                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13875                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1734439                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      1113474                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2547                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2547                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287963                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287963                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       991910                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1465068                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1642                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           22                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2973341                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6222105                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        35861                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       172954                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9404261                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63456832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208155201                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1084160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5514304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278210497                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      220375                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6313792                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.033219                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.179209                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            6104051     96.68%     96.68% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             209741      3.32%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6313792                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4643672976                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       564000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1489388443                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3104272690                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      24683477                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     110523908                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               222096                       # Transaction distribution
system.iobus.trans_dist::ReadResp              222096                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57708                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57708                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1642                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1642                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       464350                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3284                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3284                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  562892                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6660                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       238452                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3272836                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3914184                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8775000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           242657095                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           453362000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47574                       # number of replacements
system.iocache.tags.tagsinuse                0.103760                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4993210499000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103760                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006485                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.006485                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
system.iocache.tags.data_accesses              428661                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
system.iocache.overall_misses::total              909                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    141558677                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    141558677                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5512975418                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5512975418                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    141558677                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    141558677                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    141558677                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    141558677                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 155730.117712                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118000.330009                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118000.330009                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 155730.117712                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 155730.117712                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 155730.117712                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           548                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   46                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.913043                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     96108677                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3176975418                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3176975418                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     96108677                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     96108677                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     96108677                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 105730.117712                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68000.330009                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68000.330009                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105730.117712                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 105730.117712                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              602896                       # Transaction distribution
system.membus.trans_dist::ReadResp             655847                       # Transaction distribution
system.membus.trans_dist::WriteReq              13875                       # Transaction distribution
system.membus.trans_dist::WriteResp             13875                       # Transaction distribution
system.membus.trans_dist::Writeback            149737                       # Transaction distribution
system.membus.trans_dist::CleanEvict            10183                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2524                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2074                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133454                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133450                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         52973                       # Transaction distribution
system.membus.trans_dist::MessageReq             1642                       # Transaction distribution
system.membus.trans_dist::MessageResp            1642                       # Transaction distribution
system.membus.trans_dist::BadAddressError           22                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3284                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3284                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464350                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769192                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       487788                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           44                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721374                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141823                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141823                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1866481                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238452                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538381                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18425216                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20202049                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23223657                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1607                       # Total snoops (count)
system.membus.snoop_fanout::samples           1014551                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001618                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040197                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 1012909     99.84%     99.84% # Request fanout histogram
system.membus.snoop_fanout::2                    1642      0.16%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             1014551                       # Request fanout histogram
system.membus.reqLayer0.occupancy           354940000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388594500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3284000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1018302522                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               27500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1642000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2206598693                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           86075861                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------