path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.136862                       # Number of seconds simulated
sim_ticks                                5136862311000                       # Number of ticks simulated
final_tick                               5136862311000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 202420                       # Simulator instruction rate (inst/s)
host_op_rate                                   400133                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2548945395                       # Simulator tick rate (ticks/s)
host_mem_usage                                 760276                       # Number of bytes of host memory used
host_seconds                                  2015.29                       # Real time elapsed on the host
sim_insts                                   407935752                       # Number of instructions simulated
sim_ops                                     806383618                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide      2490880                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1078272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10788032                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14361024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1078272                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1078272                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9547840                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9547840                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38920                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           53                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168563                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                224391                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149185                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149185                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       484903                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            660                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               209909                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2100121                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2795680                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          209909                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             209909                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1858691                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1858691                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1858691                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       484903                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           660                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              209909                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2100121                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4654371                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        224391                       # Total number of read requests seen
system.physmem.writeReqs                       149185                       # Total number of write requests seen
system.physmem.cpureqs                         388105                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     14361024                       # Total number of bytes read from memory
system.physmem.bytesWritten                   9547840                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               14361024                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                9547840                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      135                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               3903                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 14157                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 13127                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 13393                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 16573                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 13535                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 12962                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 13580                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 16342                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 13760                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 13186                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                13242                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                15501                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                13187                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                12719                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                13259                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                15733                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  9129                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  8570                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  8702                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                 11948                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  8746                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  8430                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  8914                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                 11741                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  8779                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  8505                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 8628                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                10975                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 8406                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 8212                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 8505                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                10995                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                         794                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    5136862258500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  224391                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                 149979                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 3903                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    173046                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     19422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      7578                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      3497                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      3020                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      2415                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      1930                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1866                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      1777                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1691                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1016                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      933                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      828                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      817                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      915                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      867                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      221                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      5322                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      5660                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      6306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      6395                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      6433                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      6455                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      6463                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      6468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      6472                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6486                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     1165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                      827                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                      181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     4730288859                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                9241012609                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1121280000                       # Total cycles spent in databus access
system.physmem.totBankLat                  3389443750                       # Total cycles spent in bank access
system.physmem.avgQLat                       21093.25                       # Average queueing delay per request
system.physmem.avgBankLat                    15114.17                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  41207.43                       # Average memory access latency
system.physmem.avgRdBW                           2.80                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   2.80                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   1.86                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                        12.83                       # Average write queue length over time
system.physmem.readRowHits                     193267                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    105785                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.18                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  70.91                       # Row buffer hit rate for writes
system.physmem.avgGap                     13750514.64                       # Average gap between requests
system.iocache.replacements                     47583                       # number of replacements
system.iocache.tagsinuse                     0.137403                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47599                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4991910569000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.137403                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.008588                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.008588                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          912                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              912                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47632                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47632                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47632                       # number of overall misses
system.iocache.overall_misses::total            47632                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144324932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    144324932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10020383160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  10020383160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  10164708092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  10164708092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  10164708092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  10164708092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          912                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            912                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47632                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47632                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47632                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47632                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158251.021930                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 158251.021930                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214477.379281                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 214477.379281                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213400.824908                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 213400.824908                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213400.824908                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 213400.824908                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        133472                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                12161                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.975413                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46673                       # number of writebacks
system.iocache.writebacks::total                46673                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          912                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          912                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47632                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47632                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47632                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47632                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96878242                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     96878242                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7589579568                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   7589579568                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7686457810                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   7686457810                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7686457810                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   7686457810                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106226.142544                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 106226.142544                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162448.192808                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 162448.192808                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 161371.720902                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 161371.720902                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.branchPred.lookups                86190273                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86190273                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1107531                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             81286866                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                79207834                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.442352                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
system.cpu.numCycles                        448143159                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27503051                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      425930482                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86190273                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79207834                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     163575255                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 4699027                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     119359                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               63002200                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                36275                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         56191                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          501                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9012986                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                485449                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    3601                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          257845073                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.261142                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.418049                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 94696195     36.73%     36.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1566516      0.61%     37.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71918479     27.89%     65.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   936665      0.36%     65.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1597376      0.62%     66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2419164      0.94%     67.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1071712      0.42%     67.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1371295      0.53%     68.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 82267671     31.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            257845073                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.192328                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.950434                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 31188651                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              60472166                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 159373926                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3258089                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3552241                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              837743575                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   790                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3552241                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 33924496                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37350938                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       11010617                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 159571112                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              12435669                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834099694                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 18960                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                5861549                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4743149                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             8341                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           995593221                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1810589255                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1810588751                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               504                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964361742                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 31231472                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             459351                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         467339                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  28773559                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17056832                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10125853                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1239786                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           991765                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  827988990                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1249374                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823075347                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            149433                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        21943198                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33340930                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         196529                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     257845073                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.192131                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.383978                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            71377289     27.68%     27.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15522092      6.02%     33.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10290654      3.99%     37.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7462079      2.89%     40.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75909573     29.44%     70.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3836908      1.49%     71.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72514603     28.12%     99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              779740      0.30%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              152135      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       257845073                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  361447     33.94%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 553013     51.93%     85.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                150537     14.13%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            311265      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795546265     96.66%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17838711      2.17%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9379106      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823075347                       # Type of FU issued
system.cpu.iq.rate                           1.836635                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1064997                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001294                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905340193                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         851191548                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    818612199                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 185                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                230                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              823828994                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      85                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1638396                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3078783                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        22684                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11490                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1711608                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1932396                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         11890                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3552241                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                26088999                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2114690                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           829238364                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            319607                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17056832                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10125853                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             718701                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1615260                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11047                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11490                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         650165                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       594804                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1244969                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             821209157                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17428424                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1866189                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26576192                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83198528                       # Number of branches executed
system.cpu.iew.exec_stores                    9147768                       # Number of stores executed
system.cpu.iew.exec_rate                     1.832471                       # Inst execution rate
system.cpu.iew.wb_sent                      820748086                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     818612249                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 639805768                       # num instructions producing a value
system.cpu.iew.wb_consumers                1045573656                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.826676                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611918                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22746956                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1052843                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1113134                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    254292832                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.171083                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.853965                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     82512721     32.45%     32.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11810250      4.64%     37.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3911409      1.54%     38.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74946899     29.47%     68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2433458      0.96%     69.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1482000      0.58%     69.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       941049      0.37%     70.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70920641     27.89%     97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5334405      2.10%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    254292832                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407935752                       # Number of instructions committed
system.cpu.commit.committedOps              806383618                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22392291                       # Number of memory references committed
system.cpu.commit.loads                      13978046                       # Number of loads committed
system.cpu.commit.membars                      473511                       # Number of memory barriers committed
system.cpu.commit.branches                   82192705                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735323034                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5334405                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1078010714                       # The number of ROB reads
system.cpu.rob.rob_writes                  1661832245                       # The number of ROB writes
system.cpu.timesIdled                         1221118                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190298086                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9825578883                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407935752                       # Number of Instructions Simulated
system.cpu.committedOps                     806383618                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407935752                       # Number of Instructions Simulated
system.cpu.cpi                               1.098563                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.098563                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.910280                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.910280                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1506729750                       # number of integer regfile reads
system.cpu.int_regfile_writes               976791944                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
system.cpu.misc_regfile_reads               264623965                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402412                       # number of misc regfile writes
system.cpu.icache.replacements                1049766                       # number of replacements
system.cpu.icache.tagsinuse                510.907265                       # Cycle average of tags in use
system.cpu.icache.total_refs                  7899601                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1050278                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.521438                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56071908000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.907265                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.997866                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.997866                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      7899601                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7899601                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7899601                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7899601                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7899601                       # number of overall hits
system.cpu.icache.overall_hits::total         7899601                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1113380                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1113380                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1113380                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1113380                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1113380                       # number of overall misses
system.cpu.icache.overall_misses::total       1113380                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15333448488                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15333448488                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15333448488                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15333448488                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15333448488                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15333448488                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9012981                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9012981                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9012981                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9012981                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9012981                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9012981                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123531                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.123531                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.123531                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.123531                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.123531                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.123531                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.981253                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13771.981253                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.981253                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13771.981253                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.981253                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13771.981253                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        13782                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               303                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    45.485149                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60842                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        60842                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        60842                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        60842                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        60842                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        60842                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1052538                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1052538                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1052538                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1052538                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1052538                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1052538                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12613347488                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12613347488                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12613347488                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12613347488                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12613347488                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12613347488                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116780                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116780                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116780                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.116780                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116780                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.116780                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.745469                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.745469                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.745469                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.745469                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.745469                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.745469                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements         9783                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.014217                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          28141                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs         9798                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.872117                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5106728958500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.014217                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375889                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375889                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        28140                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        28140                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        28142                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        28142                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        28142                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        28142                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        10689                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        10689                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        10689                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        10689                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        10689                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        10689                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    118046500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    118046500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    118046500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    118046500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    118046500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    118046500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38829                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        38829                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38831                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        38831                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38831                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        38831                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.275284                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.275284                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.275270                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.275270                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.275270                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.275270                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11043.736552                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11043.736552                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11043.736552                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11043.736552                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11043.736552                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11043.736552                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1993                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1993                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        10689                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        10689                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        10689                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        10689                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        10689                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        10689                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     96668500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     96668500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     96668500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     96668500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     96668500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     96668500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.275284                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.275284                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.275270                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.275270                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.275270                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.275270                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9043.736552                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9043.736552                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9043.736552                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9043.736552                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9043.736552                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9043.736552                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       108113                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       13.301181                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         134692                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       108129                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.245660                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5100502305500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.301181                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.831324                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.831324                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       134692                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       134692                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       134692                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       134692                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       134692                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       134692                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       109183                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       109183                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       109183                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       109183                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       109183                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       109183                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1366356000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1366356000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1366356000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1366356000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1366356000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1366356000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       243875                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       243875                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       243875                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       243875                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       243875                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       243875                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.447701                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.447701                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.447701                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.447701                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.447701                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.447701                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12514.365790                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12514.365790                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12514.365790                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12514.365790                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12514.365790                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12514.365790                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        35577                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        35577                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       109183                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       109183                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       109183                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       109183                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       109183                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       109183                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1147990000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1147990000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1147990000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1147990000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1147990000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1147990000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.447701                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.447701                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.447701                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.447701                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.447701                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.447701                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10514.365790                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10514.365790                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10514.365790                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1659590                       # number of replacements
system.cpu.dcache.tagsinuse                511.997640                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19085008                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1660102                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.496286                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               27985000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997640                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10993134                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10993134                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8086930                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8086930                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19080064                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19080064                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19080064                       # number of overall hits
system.cpu.dcache.overall_hits::total        19080064                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2235074                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2235074                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       318068                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       318068                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2553142                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2553142                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2553142                       # number of overall misses
system.cpu.dcache.overall_misses::total       2553142                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32122708000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32122708000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9628285992                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9628285992                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  41750993992                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  41750993992                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  41750993992                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  41750993992                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13228208                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13228208                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8404998                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8404998                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21633206                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21633206                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21633206                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21633206                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.168963                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.168963                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037843                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037843                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118020                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118020                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118020                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118020                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14372.100432                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14372.100432                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30271.155828                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30271.155828                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16352.789618                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16352.789618                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16352.789618                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16352.789618                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       398716                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42426                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.397916                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1560986                       # number of writebacks
system.cpu.dcache.writebacks::total           1560986                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       863566                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       863566                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25004                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        25004                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       888570                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       888570                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       888570                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       888570                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1371508                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1371508                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       293064                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       293064                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1664572                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1664572                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1664572                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1664572                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17458468000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17458468000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8785727992                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8785727992                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26244195992                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26244195992                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26244195992                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26244195992                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97297948500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97297948500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2473076000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2473076000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99771024500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99771024500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103681                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103681                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034868                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034868                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076945                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.076945                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076945                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076945                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12729.395673                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12729.395673                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29978.871482                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29978.871482                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.332722                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.332722                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15766.332722                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15766.332722                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                113184                       # number of replacements
system.cpu.l2cache.tagsinuse             64838.652063                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3931021                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                177284                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 22.173580                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 50168.170279                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker    13.493195                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.133179                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3227.427363                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  11429.428047                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.765506                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000206                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.049247                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.174399                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.989359                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       101466                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         8114                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst      1033385                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333616                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2476581                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1598556                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1598556                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          335                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          335                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       156370                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       156370                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       101466                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         8114                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst      1033385                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1489986                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2632951                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       101466                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         8114                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst      1033385                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1489986                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2632951                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           53                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16850                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        36691                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        53601                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         3625                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         3625                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132809                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132809                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           53                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16850                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169500                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        186410                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           53                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            7                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16850                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169500                       # number of overall misses
system.cpu.l2cache.overall_misses::total       186410                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4666500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       459000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1174285000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2521513999                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3700924499                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17158500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17158500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6838563000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   6838563000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4666500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       459000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1174285000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9360076999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10539487499                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4666500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       459000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1174285000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9360076999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10539487499                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       101519                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         8121                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1050235                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1370307                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2530182                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1598556                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1598556                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         3960                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         3960                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       289179                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       289179                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       101519                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         8121                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1050235                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1659486                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2819361                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       101519                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         8121                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1050235                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1659486                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2819361                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000522                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000862                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016044                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026776                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021185                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.915404                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.915404                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.459262                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.459262                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000522                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000862                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016044                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102140                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.066118                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000522                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000862                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016044                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102140                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.066118                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88047.169811                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65571.428571                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69690.504451                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68722.956556                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69045.810694                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4733.379310                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4733.379310                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51491.713664                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51491.713664                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88047.169811                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65571.428571                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69690.504451                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55221.693209                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56539.281686                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88047.169811                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65571.428571                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69690.504451                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55221.693209                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56539.281686                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102512                       # number of writebacks
system.cpu.l2cache.writebacks::total           102512                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            3                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           53                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16848                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36690                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        53598                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3625                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         3625                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132809                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132809                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           53                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16848                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169499                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       186407                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           53                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16848                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169499                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       186407                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4003602                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       370512                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    964285581                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2065462567                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3034122262                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     37079107                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     37079107                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5200762570                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5200762570                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4003602                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       370512                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    964285581                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7266225137                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8234884832                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4003602                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       370512                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    964285581                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7266225137                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8234884832                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89188560000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89188560000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2310705000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2310705000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91499265000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91499265000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000522                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000862                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016042                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026775                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021183                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.915404                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.915404                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.459262                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.459262                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000522                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000862                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016042                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102139                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.066117                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000522                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000862                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016042                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102139                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.066117                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52930.285714                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57234.424323                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56294.973208                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56608.870891                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10228.719172                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10228.719172                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39159.714854                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39159.714854                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52930.285714                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57234.424323                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42868.837793                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44176.907691                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52930.285714                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57234.424323                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42868.837793                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44176.907691                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------