path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.152315                       # Number of seconds simulated
sim_ticks                                5152314519000                       # Number of ticks simulated
final_tick                               5152314519000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 171705                       # Simulator instruction rate (inst/s)
host_op_rate                                   339400                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2173929918                       # Simulator tick rate (ticks/s)
host_mem_usage                                 815744                       # Number of bytes of host memory used
host_seconds                                  2370.05                       # Real time elapsed on the host
sim_insts                                   406948645                       # Number of instructions simulated
sim_ops                                     804394656                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1035840                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10724032                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11792640                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1035840                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1035840                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9542144                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9542144                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           64                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16185                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167563                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                184260                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149096                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149096                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            795                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               201044                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2081401                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5503                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2288804                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          201044                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             201044                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1852011                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1852011                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1852011                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           795                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              201044                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2081401                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5503                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4140816                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        184260                       # Number of read requests accepted
system.physmem.writeReqs                       149096                       # Number of write requests accepted
system.physmem.readBursts                      184260                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     149096                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11779776                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     12864                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9541120                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11792640                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9542144                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      201                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          58140                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11261                       # Per bank write bursts
system.physmem.perBankRdBursts::1               10600                       # Per bank write bursts
system.physmem.perBankRdBursts::2               12322                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11592                       # Per bank write bursts
system.physmem.perBankRdBursts::4               11482                       # Per bank write bursts
system.physmem.perBankRdBursts::5               10950                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11082                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11124                       # Per bank write bursts
system.physmem.perBankRdBursts::8               10622                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11032                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11540                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11373                       # Per bank write bursts
system.physmem.perBankRdBursts::12              12384                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12480                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11990                       # Per bank write bursts
system.physmem.perBankRdBursts::15              12225                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9586                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9015                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9694                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9483                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9592                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9320                       # Per bank write bursts
system.physmem.perBankWrBursts::6                9057                       # Per bank write bursts
system.physmem.perBankWrBursts::7                9053                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8752                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9410                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9210                       # Per bank write bursts
system.physmem.perBankWrBursts::11               8755                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9657                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9381                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9483                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9632                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    5152314469500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  184260                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149096                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    169844                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1944                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       460                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       23                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2961                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     8310                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     8291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     9451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     8753                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     9931                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     9927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    11713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     9031                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8382                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8611                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7912                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7665                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7493                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      340                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      204                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      173                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      199                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      118                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      130                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      140                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       99                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       41                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       38                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        73146                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      291.483225                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.242867                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     313.005738                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          28143     38.48%     38.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17778     24.30%     62.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7759     10.61%     73.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4281      5.85%     79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2977      4.07%     83.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2397      3.28%     86.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1373      1.88%     88.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1102      1.51%     89.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7336     10.03%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          73146                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7286                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.261872                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      562.739811                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7285     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7286                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7286                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.461158                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.651895                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.024155                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6243     85.68%     85.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             165      2.26%     87.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              39      0.54%     88.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             177      2.43%     90.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              22      0.30%     91.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             151      2.07%     93.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             106      1.45%     94.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              11      0.15%     94.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              24      0.33%     95.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              33      0.45%     95.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               7      0.10%     95.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               7      0.10%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             220      3.02%     98.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               4      0.05%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               9      0.12%     99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              29      0.40%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               2      0.03%     99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               2      0.03%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             6      0.08%     99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.03%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.01%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            18      0.25%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7286                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2105191048                       # Total ticks spent queuing
system.physmem.totMemAccLat                5556297298                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    920295000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11437.59                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30187.59                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.81                       # Average write queue length when enqueuing
system.physmem.readRowHits                     150243                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    109749                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.61                       # Row buffer hit rate for writes
system.physmem.avgGap                     15455892.41                       # Average gap between requests
system.physmem.pageHitRate                      78.04                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  269634960                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  147122250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 705213600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                484704000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           132970948335                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2974744703250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3445846141035                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.796378                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4948677575724                       # Time in different power states
system.physmem_0.memoryStateTime::REF    172046940000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     31589843276                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  283348800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  154605000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 730438800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                481334400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           336523814640                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           133265512935                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2974486313250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3445925367825                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.811755                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4948236275986                       # Time in different power states
system.physmem_1.memoryStateTime::REF    172046940000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     32026607764                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86360408                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86360408                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            844738                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79711483                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77808056                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.612104                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1540361                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             177639                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        465551291                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27284501                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      426653476                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86360408                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79348417                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     433446162                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1774418                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     139394                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                62229                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        198576                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          774                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8943748                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                426371                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4516                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          462018901                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.822492                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.015475                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                297432046     64.38%     64.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2127313      0.46%     64.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72010980     15.59%     80.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1540927      0.33%     80.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2092821      0.45%     81.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2281981      0.49%     81.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1471602      0.32%     82.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1847080      0.40%     82.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81214151     17.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            462018901                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.185501                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.916448                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 22519839                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             281050355                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150243576                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7317922                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 887209                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              834205750                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 887209                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25305856                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               229987183                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       14520771                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154096496                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              37221386                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              830901673                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                454414                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12058066                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 208457                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               22294259                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           992600987                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1804085973                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1109069164                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               286                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             961883524                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 30717461                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             460427                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         463529                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  38187587                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17040256                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10018392                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1266986                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1072258                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  825691253                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1151613                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 820808364                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            215045                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        22448205                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33824600                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         141893                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     462018901                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.776569                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.399860                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           278841075     60.35%     60.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13664119      2.96%     63.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9689206      2.10%     65.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6979280      1.51%     66.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74151695     16.05%     82.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4284933      0.93%     83.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72644295     15.72%     99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1183606      0.26%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              580692      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       462018901                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1922566     72.06%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     72.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 586085     21.97%     94.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                159449      5.98%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            284230      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             792921370     96.60%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               149961      0.02%     96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                126332      0.02%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  89      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.67% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18051625      2.20%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9274757      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              820808364                       # Type of FU issued
system.cpu.iq.rate                           1.763089                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2668100                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003251                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2106518335                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         849303097                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    816525348                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 438                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                438                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          154                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              823192025                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     209                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1863548                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3085191                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14446                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        13942                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1597044                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2095832                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         68625                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 887209                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               206158213                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              15645218                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826842866                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            165190                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17040277                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10018392                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             682629                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 383889                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents              14436572                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          13942                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         477389                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506444                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               983833                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819298071                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17680302                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1386078                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26745461                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 82993620                       # Number of branches executed
system.cpu.iew.exec_stores                    9065159                       # Number of stores executed
system.cpu.iew.exec_rate                     1.759845                       # Inst execution rate
system.cpu.iew.wb_sent                      818824421                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     816525502                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638690631                       # num instructions producing a value
system.cpu.iew.wb_consumers                1046712832                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.753889                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610187                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        22323770                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1009720                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            855337                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    458653605                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.753817                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.647498                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    288196518     62.84%     62.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11088839      2.42%     65.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3639702      0.79%     66.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74471288     16.24%     82.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2429938      0.53%     82.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1624365      0.35%     83.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1000566      0.22%     83.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70851536     15.45%     98.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5350853      1.17%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    458653605                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            406948645                       # Number of instructions committed
system.cpu.commit.committedOps              804394656                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22376433                       # Number of memory references committed
system.cpu.commit.loads                      13955085                       # Number of loads committed
system.cpu.commit.membars                      448031                       # Number of memory barriers committed
system.cpu.commit.branches                   82000673                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 733377152                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155590                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171815      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        781582591     97.16%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          144575      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121813      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13952498      1.73%     98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8421348      1.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         804394656                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5350853                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1279942872                       # The number of ROB reads
system.cpu.rob.rob_writes                  1656820485                       # The number of ROB writes
system.cpu.timesIdled                          287895                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3532390                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9839075158                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   406948645                       # Number of Instructions Simulated
system.cpu.committedOps                     804394656                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.144005                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.144005                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.874122                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.874122                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1088092002                       # number of integer regfile reads
system.cpu.int_regfile_writes               653524498                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       154                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 414883395                       # number of cc regfile reads
system.cpu.cc_regfile_writes                320972082                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264296844                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400155                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1656669                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.992170                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18961321                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1657181                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.441913                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          65644500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.992170                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999985                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87667052                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87667052                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10819019                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10819019                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8076374                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8076374                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        63037                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         63037                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      18895393                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18895393                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18958430                       # number of overall hits
system.cpu.dcache.overall_hits::total        18958430                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1802297                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1802297                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       335310                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       335310                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406421                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406421                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2137607                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2137607                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2544028                       # number of overall misses
system.cpu.dcache.overall_misses::total       2544028                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  30111588500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  30111588500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21132348722                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21132348722                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  51243937222                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  51243937222                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  51243937222                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  51243937222                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12621316                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12621316                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8411684                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8411684                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       469458                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       469458                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21033000                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21033000                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21502458                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21502458                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142798                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142798                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039862                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039862                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.865724                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.865724                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101631                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101631                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118313                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118313                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16707.339856                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16707.339856                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63023.317891                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 63023.317891                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23972.571769                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23972.571769                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20142.835386                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20142.835386                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       552183                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             52307                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.556579                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1558965                       # number of writebacks
system.cpu.dcache.writebacks::total           1558965                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       836189                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       836189                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44847                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44847                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       881036                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       881036                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       881036                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       881036                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       966108                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       966108                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290463                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290463                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402928                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402928                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1256571                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1256571                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1659499                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1659499                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13902                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       587362                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14275784000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  14275784000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19192933722                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19192933722                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6799517500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6799517500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33468717722                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  33468717722                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  40268235222                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  40268235222                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  98146130000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  98146130000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2778950500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2778950500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925080500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925080500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076546                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076546                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034531                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034531                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.858283                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.858283                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059743                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059743                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077177                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077177                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14776.592265                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14776.592265                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66077.034672                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66077.034672                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16875.266797                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16875.266797                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26634.959522                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26634.959522                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24265.296467                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24265.296467                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.298853                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.298853                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199895.734427                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199895.734427                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.732301                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.732301                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        70093                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.821930                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       109512                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        70108                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.562047                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.821930                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988871                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988871                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       432670                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       432670                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       109535                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       109535                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       109535                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       109535                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       109535                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       109535                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        71200                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        71200                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        71200                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        71200                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        71200                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        71200                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    922231500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    922231500                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    922231500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    922231500                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    922231500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    922231500                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       180735                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       180735                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       180735                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       180735                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       180735                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       180735                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.393947                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.393947                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.393947                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.393947                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12952.689607                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12952.689607                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12952.689607                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12952.689607                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        21274                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        21274                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        71200                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        71200                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        71200                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        71200                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        71200                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        71200                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    851031500                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    851031500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    851031500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    851031500                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.393947                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.393947                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.393947                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.393947                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11952.689607                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11952.689607                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11952.689607                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            977286                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.169987                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7899726                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            977798                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.079098                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      150383300500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.169987                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994473                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994473                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          126                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9921613                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9921613                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7899726                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7899726                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7899726                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7899726                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7899726                       # number of overall hits
system.cpu.icache.overall_hits::total         7899726                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1044015                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1044015                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1044015                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1044015                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1044015                       # number of overall misses
system.cpu.icache.overall_misses::total       1044015                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  15702934482                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  15702934482                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  15702934482                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  15702934482                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  15702934482                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  15702934482                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8943741                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8943741                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8943741                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8943741                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8943741                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8943741                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116731                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116731                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116731                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116731                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116731                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116731                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15040.908878                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15040.908878                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15040.908878                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15040.908878                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15040.908878                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15040.908878                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        15272                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          183                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               489                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    31.231084                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    91.500000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks       977286                       # number of writebacks
system.cpu.icache.writebacks::total            977286                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        66143                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        66143                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        66143                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        66143                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        66143                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        66143                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       977872                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       977872                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       977872                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       977872                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       977872                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       977872                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13831418488                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13831418488                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13831418488                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13831418488                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13831418488                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13831418488                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109336                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.109336                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109336                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.109336                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14144.405902                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14144.405902                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14144.405902                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14144.405902                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        13564                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.033276                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        24089                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        13580                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.773859                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.033276                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.377080                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.377080                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        91534                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        91534                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        24087                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        24087                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        24089                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        24089                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        24089                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        24089                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14452                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        14452                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14452                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        14452                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14452                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        14452                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176436500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176436500                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176436500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    176436500                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176436500                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    176436500                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        38539                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        38539                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        38541                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        38541                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        38541                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        38541                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.374997                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.374997                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.374977                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.374977                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.374977                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.374977                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12208.448658                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12208.448658                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12208.448658                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12208.448658                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12208.448658                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12208.448658                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         2638                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         2638                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14452                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14452                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14452                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        14452                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14452                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        14452                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161984500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161984500                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161984500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161984500                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161984500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161984500                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.374997                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.374997                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.374977                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.374977                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.374977                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.374977                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11208.448658                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11208.448658                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11208.448658                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11208.448658                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111860                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64806.586551                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4895189                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176141                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.791309                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50665.329006                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    16.461622                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139358                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3133.882078                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.774487                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.773092                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000251                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.047819                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.167706                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.988870                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64281                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          693                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6102                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54081                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.980850                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43507450                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43507450                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      1582877                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      1582877                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       976140                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       976140                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          326                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          326                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       155489                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       155489                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       961542                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       961542                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        64982                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12040                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1332604                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1409626                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64982                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12040                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       961542                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1488093                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2526657                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64982                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12040                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       961542                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1488093                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2526657                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1472                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1472                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       132824                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       132824                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16188                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16188                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           64                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35686                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35755                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           64                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16188                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168510                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        184767                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           64                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16188                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168510                       # number of overall misses
system.cpu.l2cache.overall_misses::total       184767                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     60587500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     60587500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16987974500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16987974500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2174639000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2174639000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      9238000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       665000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   4801016500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   4810919500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      9238000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       665000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2174639000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  21788991000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  23973533000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      9238000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       665000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2174639000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  21788991000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  23973533000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      1582877                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      1582877                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       976140                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       976140                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1798                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1798                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288313                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288313                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       977730                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       977730                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        65046                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12045                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1368290                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1445381                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        65046                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12045                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       977730                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1656603                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2711424                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        65046                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12045                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       977730                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1656603                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2711424                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.818687                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.818687                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.460694                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.460694                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016557                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016557                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.000984                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000415                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026081                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024737                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000984                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000415                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016557                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101720                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068144                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000984                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000415                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016557                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101720                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068144                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41159.986413                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41159.986413                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127898.380564                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127898.380564                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134336.483815                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134336.483815                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker       133000                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134535.013731                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134552.356314                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134336.483815                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129303.845469                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 129750.079830                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 144343.750000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       133000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134336.483815                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129303.845469                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 129750.079830                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102429                       # number of writebacks
system.cpu.l2cache.writebacks::total           102429                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            2                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            2                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            9                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1472                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1472                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       132824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16185                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16185                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           64                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35684                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35753                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           64                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16185                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168508                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       184762                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           64                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16185                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168508                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       184762                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       573460                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       573460                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13902                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13902                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       587362                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       587362                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    105285000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    105285000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  15659734500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  15659734500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2012557000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2012557000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       615000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4444414500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4453627500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       615000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2012557000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20104149000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  22125919000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8598000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       615000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2012557000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20104149000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  22125919000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90977838000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90977838000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2619015000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2619015000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  93596853000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  93596853000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.818687                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.818687                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.460694                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.460694                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016554                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026079                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024736                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101719                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068142                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000984                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000415                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016554                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101719                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068142                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71525.135870                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71525.135870                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117898.380564                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117898.380564                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124347.049737                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124549.223742                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124566.539871                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119306.792556                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119753.623581                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       123000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124347.049737                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119306.792556                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119753.623581                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.225613                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.225613                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.238671                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.238671                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.222926                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.222926                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5440647                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2708460                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        66609                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1238                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1238                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq         573460                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3006256                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13902                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13902                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      1731980                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       976140                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       117314                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2288                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2288                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       288324                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       288324                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       977872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1455461                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1647                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            4                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2931742                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6148479                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31127                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       166003                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9277351                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    125047680                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207509531                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       939712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5524480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          339021403                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      218907                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3519115                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.019900                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.161788                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3460821     98.34%     98.34% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              46556      1.32%     99.67% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              11738      0.33%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3519115                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5581131973                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       669284                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1468639319                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3067775714                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      21694467                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     106870358                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               212021                       # Transaction distribution
system.iobus.trans_dist::ReadResp              212021                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57726                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57726                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1647                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1647                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       400004                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       444236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95258                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3294                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  542788                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       200002                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       228398                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027816                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6588                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3262802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3986644                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                43000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy             10458500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               146500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy              1029000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                94000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                58500                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                32500                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            300003000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1174000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              212500                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            24569000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           241170809                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1085500                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           433230000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50170000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1647000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47574                       # number of replacements
system.iocache.tags.tagsinuse                0.140720                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4999394542000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.140720                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008795                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.008795                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
system.iocache.tags.data_accesses              428661                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          909                       # number of demand (read+write) misses
system.iocache.demand_misses::total               909                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          909                       # number of overall misses
system.iocache.overall_misses::total              909                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    150240673                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    150240673                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   6073165136                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   6073165136                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    150240673                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    150240673                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    150240673                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    150240673                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          909                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             909                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          909                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            909                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 165281.268427                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129990.692123                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129990.692123                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 165281.268427                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165281.268427                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 165281.268427                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs          1090                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                  104                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    10.480769                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          909                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          909                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          909                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          909                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          909                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          909                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    104790673                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3737165136                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3737165136                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    104790673                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    104790673                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    104790673                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115281.268427                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79990.692123                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79990.692123                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 115281.268427                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 115281.268427                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              573460                       # Transaction distribution
system.membus.trans_dist::ReadResp             626303                       # Transaction distribution
system.membus.trans_dist::WriteReq              13902                       # Transaction distribution
system.membus.trans_dist::WriteResp             13902                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       149096                       # Transaction distribution
system.membus.trans_dist::CleanEvict             9693                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2236                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1746                       # Transaction distribution
system.membus.trans_dist::ReadExReq            132555                       # Transaction distribution
system.membus.trans_dist::ReadExResp           132550                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         52847                       # Transaction distribution
system.membus.trans_dist::MessageReq             1647                       # Transaction distribution
system.membus.trans_dist::MessageResp            1647                       # Transaction distribution
system.membus.trans_dist::BadAddressError            4                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3294                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       444236                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       730488                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       484035                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio            8                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1658767                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141815                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141815                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1803876                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6588                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       228398                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1460973                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18319744                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20009115                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23030743                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1647                       # Total snoops (count)
system.membus.snoop_fanout::samples            982714                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001676                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040904                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  981067     99.83%     99.83% # Request fanout histogram
system.membus.snoop_fanout::2                    1647      0.17%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total              982714                       # Request fanout histogram
system.membus.reqLayer0.occupancy           338956500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           369067500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3986356                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1013629759                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy                5500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            2339356                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2140696281                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           85836693                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------