path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.154115                       # Number of seconds simulated
sim_ticks                                5154115247000                       # Number of ticks simulated
final_tick                               5154115247000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 128017                       # Simulator instruction rate (inst/s)
host_op_rate                                   253040                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1617614851                       # Simulator tick rate (ticks/s)
host_mem_usage                                 806232                       # Number of bytes of host memory used
host_seconds                                  3186.24                       # Real time elapsed on the host
sim_insts                                   407894468                       # Number of instructions simulated
sim_ops                                     806246903                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         4480                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1047104                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10813376                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11893632                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1047104                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1047104                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9584064                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9584064                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           70                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16361                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168959                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                185838                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149751                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149751                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            869                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               203159                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2098008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5501                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2307599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          203159                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             203159                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1859497                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1859497                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1859497                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           869                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              203159                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2098008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5501                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4167097                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        185838                       # Number of read requests accepted
system.physmem.writeReqs                       149751                       # Number of write requests accepted
system.physmem.readBursts                      185838                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     149751                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11883456                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10176                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9582144                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11893632                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9584064                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      159                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          48492                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11738                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11323                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11916                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11912                       # Per bank write bursts
system.physmem.perBankRdBursts::4               12271                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11705                       # Per bank write bursts
system.physmem.perBankRdBursts::6               10605                       # Per bank write bursts
system.physmem.perBankRdBursts::7               10992                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11596                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11415                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11752                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11610                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11474                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12022                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11655                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11693                       # Per bank write bursts
system.physmem.perBankWrBursts::0               10141                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9357                       # Per bank write bursts
system.physmem.perBankWrBursts::2                8826                       # Per bank write bursts
system.physmem.perBankWrBursts::3                8882                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9347                       # Per bank write bursts
system.physmem.perBankWrBursts::5                9205                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8767                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8936                       # Per bank write bursts
system.physmem.perBankWrBursts::8                9149                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9192                       # Per bank write bursts
system.physmem.perBankWrBursts::10              10057                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9346                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9689                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9578                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9663                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9586                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
system.physmem.totGap                    5154115197500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  185838                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 149751                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    171307                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1958                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       473                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        54                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2875                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     7881                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     7883                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     7770                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     7889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     7857                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     9606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     9971                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    11760                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    10283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     9854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     8546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9083                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9183                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     7594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      201                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      200                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      177                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      135                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      121                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       85                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       40                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       26                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        72428                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      296.370685                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     175.530831                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     319.820481                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27904     38.53%     38.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17658     24.38%     62.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7456     10.29%     73.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4108      5.67%     78.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2731      3.77%     82.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1986      2.74%     85.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1581      2.18%     87.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1174      1.62%     89.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7830     10.81%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          72428                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7352                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.252992                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      561.335686                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7351     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7352                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7352                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.364663                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.601623                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.168660                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6294     85.61%     85.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              82      1.12%     86.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             194      2.64%     89.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              86      1.17%     90.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              99      1.35%     91.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             218      2.97%     94.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              33      0.45%     95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              11      0.15%     95.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              15      0.20%     95.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               6      0.08%     95.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               3      0.04%     95.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               3      0.04%     95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             253      3.44%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               5      0.07%     99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.04%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               7      0.10%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               4      0.05%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.03%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             3      0.04%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.01%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            15      0.20%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             2      0.03%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.03%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7352                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2003475850                       # Total ticks spent queuing
system.physmem.totMemAccLat                5484957100                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    928395000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10790.00                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29540.00                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.86                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.16                       # Average write queue length when enqueuing
system.physmem.readRowHits                     152313                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110658                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.03                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.89                       # Row buffer hit rate for writes
system.physmem.avgGap                     15358415.20                       # Average gap between requests
system.physmem.pageHitRate                      78.40                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  270738720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  147724500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 721203600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                476027280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           130240416060                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2978219081250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3446716483410                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.731853                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4954469478230                       # Time in different power states
system.physmem_0.memoryStateTime::REF    172107000000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27531969270                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  276816960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  151041000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 727084800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                494164800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           336641292000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           130162900905                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2978287085250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3446740385715                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.736489                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4954592740478                       # Time in different power states
system.physmem_1.memoryStateTime::REF    172107000000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     27415396022                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86789700                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86789700                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            894071                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             80040540                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78122239                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.603338                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1558682                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180590                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        449504376                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27485279                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      428718572                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86789700                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79680921                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     418030666                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1875632                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     150798                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                59488                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        208856                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           90                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          672                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9123295                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                449746                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4755                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          446873665                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.892893                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.051645                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                281625965     63.02%     63.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2138685      0.48%     63.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72155487     16.15%     79.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1568927      0.35%     80.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2122343      0.47%     80.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2325830      0.52%     80.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1507660      0.34%     81.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1867139      0.42%     81.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81561629     18.25%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            446873665                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.193079                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.953758                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 22890187                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             264923803                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150702566                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7419293                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 937816                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              837865741                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 937816                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25728184                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               222903682                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12889746                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154594835                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              29819402                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              834359795                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                448369                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12212745                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 141423                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               14773604                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           996662587                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1812180036                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1114009606                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               309                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964181963                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 32480622                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             461875                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         465908                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  38538990                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17255328                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10136845                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1286418                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1053742                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  828858399                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1188333                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 823669123                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            243637                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23799824                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     35821203                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         147900                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     446873665                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.843181                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.418517                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           262902763     58.83%     58.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13828746      3.09%     61.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             9781500      2.19%     64.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7055144      1.58%     65.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74339132     16.64%     82.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4387820      0.98%     83.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72808347     16.29%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1195469      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              574744      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       446873665                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1974081     71.95%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     2      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.95% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 609151     22.20%     94.16% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                160307      5.84%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            285084      0.03%      0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             795424559     96.57%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150449      0.02%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                127671      0.02%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                  84      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.64% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18333357      2.23%     98.87% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9347919      1.13%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              823669123                       # Type of FU issued
system.cpu.iq.rate                           1.832394                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2743541                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003331                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2097198642                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         853858757                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819128971                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 446                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                432                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          155                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              826127364                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     216                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1863869                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3260732                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        15309                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14369                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1707925                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2207612                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         70919                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 937816                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               204799790                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10007204                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           830046732                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            155850                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17255344                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10136845                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             698572                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 395239                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8760495                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14369                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         514805                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       529588                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1044393                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822053660                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17935902                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1483234                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27057833                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83242296                       # Number of branches executed
system.cpu.iew.exec_stores                    9121931                       # Number of stores executed
system.cpu.iew.exec_rate                     1.828800                       # Inst execution rate
system.cpu.iew.wb_sent                      821550761                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819129126                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 640649566                       # num instructions producing a value
system.cpu.iew.wb_consumers                1049893259                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.822294                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610204                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        23669936                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1040433                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            905908                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    443311497                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.818692                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.674309                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    272449194     61.46%     61.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11181690      2.52%     63.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3605884      0.81%     64.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74618286     16.83%     81.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2464935      0.56%     82.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1628465      0.37%     82.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       954634      0.22%     82.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70998554     16.02%     98.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5409855      1.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    443311497                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407894468                       # Number of instructions committed
system.cpu.commit.committedOps              806246903                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22423531                       # Number of memory references committed
system.cpu.commit.loads                      13994611                       # Number of loads committed
system.cpu.commit.membars                      468283                       # Number of memory barriers committed
system.cpu.commit.branches                   82184111                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735078702                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1156217                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171842      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783387641     97.16%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          145035      0.02%     97.20% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121422      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13992027      1.74%     98.95% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8428920      1.05%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806246903                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5409855                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1267740043                       # The number of ROB reads
system.cpu.rob.rob_writes                  1663415417                       # The number of ROB writes
system.cpu.timesIdled                          288487                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2630711                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9858723524                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407894468                       # Number of Instructions Simulated
system.cpu.committedOps                     806246903                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.102011                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.102011                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.907432                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.907432                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1091775121                       # number of integer regfile reads
system.cpu.int_regfile_writes               655663425                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       155                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416039105                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321913343                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265322894                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400562                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1662098                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.990156                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19068760                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1662610                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.469172                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          40620500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.990156                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999981                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999981                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88153475                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88153475                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10917190                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10917190                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8084600                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8084600                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64210                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64210                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19001790                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19001790                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19066000                       # number of overall hits
system.cpu.dcache.overall_hits::total        19066000                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1815691                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1815691                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334621                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334621                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406397                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406397                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2150312                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2150312                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2556709                       # number of overall misses
system.cpu.dcache.overall_misses::total       2556709                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  27046737500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  27046737500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  13846171242                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  13846171242                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  40892908742                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  40892908742                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  40892908742                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  40892908742                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12732881                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12732881                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8419221                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8419221                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       470607                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       470607                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21152102                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21152102                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21622709                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21622709                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.142599                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.142599                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039745                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039745                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.863559                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.863559                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.101659                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.101659                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118242                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118242                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14896.112554                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14896.112554                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.667932                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.667932                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19017.197849                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19017.197849                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15994.353969                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15994.353969                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       467851                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           84                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             51332                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.114217                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           84                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1563047                       # number of writebacks
system.cpu.dcache.writebacks::total           1563047                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       843909                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       843909                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44439                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44439                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       888348                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       888348                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       888348                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       888348                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       971782                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       971782                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290182                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       290182                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402906                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402906                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1261964                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1261964                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1664870                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1664870                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13356525500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  13356525500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  12439701244                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  12439701244                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   6060856500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   6060856500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25796226744                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  25796226744                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31857083244                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31857083244                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97797423500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97797423500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2624129500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2624129500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100421553000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 100421553000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076321                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076321                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034467                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.856141                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.856141                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059661                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059661                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076996                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076996                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13744.363962                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13744.363962                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42868.617778                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42868.617778                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15042.854909                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15042.854909                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20441.333306                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20441.333306                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19134.877344                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19134.877344                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.301831                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.301831                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188325.642314                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188325.642314                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162796.306744                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162796.306744                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        73546                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    14.805379                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       113695                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        73561                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.545588                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5097093086500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.805379                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.925336                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.925336                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       451096                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       451096                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       113711                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       113711                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       113711                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       113711                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       113711                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       113711                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        74558                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        74558                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        74558                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        74558                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        74558                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        74558                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    932190000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    932190000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    932190000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    932190000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    932190000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    932190000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       188269                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       188269                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       188269                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       188269                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       188269                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       188269                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.396018                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.396018                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.396018                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.396018                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12502.883661                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12502.883661                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12502.883661                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12502.883661                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        13222                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        13222                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        74558                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        74558                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        74558                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        74558                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        74558                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        74558                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    857632000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    857632000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    857632000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    857632000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.396018                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.396018                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.396018                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.396018                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11502.883661                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11502.883661                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11502.883661                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            993321                       # number of replacements
system.cpu.icache.tags.tagsinuse           508.961085                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8058871                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            993832                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.108887                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147914027500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   508.961085                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994065                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994065                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          301                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          113                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10117194                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10117194                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8058871                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8058871                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8058871                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8058871                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8058871                       # number of overall hits
system.cpu.icache.overall_hits::total         8058871                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1064420                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1064420                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1064420                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1064420                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1064420                       # number of overall misses
system.cpu.icache.overall_misses::total       1064420                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14809433489                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14809433489                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14809433489                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14809433489                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14809433489                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14809433489                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9123291                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9123291                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9123291                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9123291                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9123291                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9123291                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.116671                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.116671                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.116671                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.116671                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.116671                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.116671                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13913.148465                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13913.148465                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13913.148465                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13913.148465                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13913.148465                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         6712                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           16                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               348                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    19.287356                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           16                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        70517                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        70517                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        70517                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        70517                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        70517                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        70517                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       993903                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       993903                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       993903                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       993903                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       993903                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       993903                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13139309991                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13139309991                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13139309991                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13139309991                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13139309991                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13139309991                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.108941                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.108941                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.108941                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.108941                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13219.911793                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13219.911793                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13219.911793                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        13951                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.067078                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        26495                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        13966                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.897107                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5104644726500                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.067078                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.379192                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.379192                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           15                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.937500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        97508                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        97508                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26495                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        26495                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26497                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        26497                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26497                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        26497                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        14838                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        14838                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        14838                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        14838                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        14838                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        14838                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    176788000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    176788000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    176788000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    176788000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    176788000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    176788000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41333                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        41333                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41335                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        41335                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41335                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        41335                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.358987                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.358987                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.358969                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.358969                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.358969                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.358969                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11914.543739                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11914.543739                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11914.543739                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11914.543739                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11914.543739                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1499                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1499                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        14838                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        14838                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        14838                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        14838                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        14838                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        14838                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    161950000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    161950000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    161950000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    161950000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    161950000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    161950000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.358987                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.358987                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.358969                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.358969                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.358969                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10914.543739                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10914.543739                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10914.543739                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112938                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64810.238427                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4946164                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176935                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            27.954695                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50458.579366                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    20.514879                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.139418                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3172.056588                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11158.948175                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.769937                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000313                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048402                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.170272                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.988926                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63997                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3372                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5567                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54302                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976517                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43925036                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43925036                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      1577768                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1577768                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       153927                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       153927                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       977435                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       977435                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker        69221                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker        12891                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1338249                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1420361                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        69221                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12891                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       977435                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1492176                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2551723                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        69221                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12891                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       977435                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1492176                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2551723                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1505                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1505                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       134154                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       134154                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        16363                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        16363                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker           70                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker            5                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        35783                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        35858                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           70                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16363                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169937                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        186375                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           70                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16363                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169937                       # number of overall misses
system.cpu.l2cache.overall_misses::total       186375                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     23274500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     23274500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10328890000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10328890000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   1358981500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   1358981500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker      6541000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker       429500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3085479000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   3092449500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      6541000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       429500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1358981500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  13414369000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  14780321000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      6541000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       429500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1358981500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  13414369000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  14780321000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      1577768                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1577768                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1814                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1814                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       288081                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       288081                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       993798                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       993798                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker        69291                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker        12896                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1374032                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1456219                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69291                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12896                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       993798                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1662113                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2738098                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69291                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12896                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       993798                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1662113                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2738098                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.829658                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.829658                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.465682                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.465682                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.016465                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.016465                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker     0.000388                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.026042                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.024624                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000388                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016465                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102242                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068067                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.001010                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000388                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016465                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102242                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068067                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15464.784053                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15464.784053                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76992.784412                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76992.784412                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83052.099248                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83052.099248                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker        85900                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86227.510270                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86241.550003                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79304.203890                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93442.857143                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        85900                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83052.099248                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78937.306178                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79304.203890                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       103084                       # number of writebacks
system.cpu.l2cache.writebacks::total           103084                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           88                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total           88                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1505                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1505                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       134154                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       134154                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        16361                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        16361                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker           70                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker            5                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        35779                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        35854                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           70                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16361                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169933                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       186369                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           70                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16361                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169933                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       186369                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data       602920                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total       602920                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        13934                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        13934                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data       616854                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       616854                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     32097000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     32097000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8987350000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8987350000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   1195241000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   1195241000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker       379500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2728894000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2735114500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       379500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1195241000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11716244000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  12917705500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5841000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       379500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1195241000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11716244000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  12917705500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  90260915500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  90260915500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2463879500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2463879500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  92724795000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  92724795000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.829658                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.829658                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.465682                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.465682                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.016463                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.026039                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.024621                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068065                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001010                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000388                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016463                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102239                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068065                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21326.910299                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21326.910299                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66992.784412                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66992.784412                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73054.275411                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76270.829257                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76284.779941                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83442.857143                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        75900                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73054.275411                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68946.255289                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69312.522469                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.288562                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.288562                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176824.996412                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176824.996412                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150318.867998                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150318.867998                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         602920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3061153                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13934                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13934                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1727529                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      1124352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2232                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2232                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       288090                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       288090                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       993903                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1464872                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::MessageReq         1650                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           12                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2979851                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6223737                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        32716                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       177236                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           9413540                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     63603072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    208211079                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       921280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5280832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278016263                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      218468                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      6317764                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.033210                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.179185                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            6107951     96.68%     96.68% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             209813      3.32%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        6317764                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4638715490                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       577500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1492354491                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3105124685                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      22263487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     111892387                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               222126                       # Transaction distribution
system.iobus.trans_dist::ReadResp              222126                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57753                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57753                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1650                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1650                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       420172                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       464488                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95270                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3300                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3300                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  563058                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       210086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       238530                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027864                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3272994                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3933000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            210087000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           242643106                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           453455000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            50182000                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1650000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47580                       # number of replacements
system.iocache.tags.tagsinuse                0.177808                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47596                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4993210705000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.177808                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.011113                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.011113                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428715                       # Number of tag accesses
system.iocache.tags.data_accesses              428715                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide          915                       # number of demand (read+write) misses
system.iocache.demand_misses::total               915                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          915                       # number of overall misses
system.iocache.overall_misses::total              915                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142818702                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    142818702                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   5513453404                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   5513453404                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    142818702                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    142818702                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    142818702                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    142818702                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          915                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             915                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          915                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            915                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 156086.013115                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 118010.560873                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118010.560873                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 156086.013115                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 156086.013115                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 156086.013115                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs           218                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                   18                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.111111                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        46720                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          915                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          915                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          915                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          915                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     97068702                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   3177453404                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   3177453404                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total     97068702                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide     97068702                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total     97068702                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 106086.013115                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68010.560873                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68010.560873                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 106086.013115                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 106086.013115                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              602920                       # Transaction distribution
system.membus.trans_dist::ReadResp             656038                       # Transaction distribution
system.membus.trans_dist::WriteReq              13934                       # Transaction distribution
system.membus.trans_dist::WriteResp             13934                       # Transaction distribution
system.membus.trans_dist::Writeback            149751                       # Transaction distribution
system.membus.trans_dist::CleanEvict            10203                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2209                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1791                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133869                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133868                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         53130                       # Transaction distribution
system.membus.trans_dist::MessageReq             1650                       # Transaction distribution
system.membus.trans_dist::MessageResp            1650                       # Transaction distribution
system.membus.trans_dist::BadAddressError           12                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        46720                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3300                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3300                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       464488                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       769220                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       488383                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           24                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1722115                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141817                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1867232                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6600                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       238530                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1538437                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18462656                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20239623                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      3015040                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                23261263                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1586                       # Total snoops (count)
system.membus.snoop_fanout::samples           1014957                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.001626                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.040287                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 1013307     99.84%     99.84% # Request fanout histogram
system.membus.snoop_fanout::2                    1650      0.16%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total             1014957                       # Request fanout histogram
system.membus.reqLayer0.occupancy           355040500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           388549500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3300000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1018755770                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               14000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1650000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         2209187226                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer4.occupancy           86115345                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------