path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.155288                       # Number of seconds simulated
sim_ticks                                5155288336500                       # Number of ticks simulated
final_tick                               5155288336500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 187724                       # Simulator instruction rate (inst/s)
host_op_rate                                   369929                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             2268413480                       # Simulator tick rate (ticks/s)
host_mem_usage                                 362380                       # Number of bytes of host memory used
host_seconds                                  2272.64                       # Real time elapsed on the host
sim_insts                                   426629675                       # Number of instructions simulated
sim_ops                                     840716593                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                    15943680                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                1259264                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 12043648                       # Number of bytes written to this memory
system.physmem.num_reads                       249120                       # Number of read requests responded to by this memory
system.physmem.num_writes                      188182                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                        3092684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    244266                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                       2336174                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                       5428858                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        167456                       # number of replacements
system.l2c.tagsinuse                     37822.927931                       # Cycle average of tags in use
system.l2c.total_refs                         3846980                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        202165                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         19.028912                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        26706.608582                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker       11.179185                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        0.034739                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           2430.963092                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           8674.142332                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.407511                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000171                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000001                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.037094                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.132357                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.577132                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker        117941                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          9215                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst             1064505                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data             1335031                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                2526692                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks         1602581                       # number of Writeback hits
system.l2c.Writeback_hits::total              1602581                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data              322                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 322                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            151453                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               151453                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker         117941                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           9215                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst              1064505                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data              1486484                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2678145                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker        117941                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          9215                       # number of overall hits
system.l2c.overall_hits::cpu.inst             1064505                       # number of overall hits
system.l2c.overall_hits::cpu.data             1486484                       # number of overall hits
system.l2c.overall_hits::total                2678145                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker           98                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             19677                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             45243                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                65025                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           2687                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2687                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          141494                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             141494                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker           98                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              19677                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             186737                       # number of demand (read+write) misses
system.l2c.demand_misses::total                206519                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker           98                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker            7                       # number of overall misses
system.l2c.overall_misses::cpu.inst             19677                       # number of overall misses
system.l2c.overall_misses::cpu.data            186737                       # number of overall misses
system.l2c.overall_misses::total               206519                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker      5116000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker       364000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst   1028234500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data   2378237500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     3411952000                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data     39192000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total     39192000                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data   7368603000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   7368603000                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker      5116000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker       364000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst   1028234500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data   9746840500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total     10780555000                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker      5116000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker       364000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst   1028234500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data   9746840500                       # number of overall miss cycles
system.l2c.overall_miss_latency::total    10780555000                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker       118039                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         9222                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst         1084182                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data         1380274                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2591717                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks      1602581                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total          1602581                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         3009                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            3009                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        292947                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           292947                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker       118039                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         9222                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst          1084182                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data          1673221                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2884664                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker       118039                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         9222                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst         1084182                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data         1673221                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2884664                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000830                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000759                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.018149                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.032778                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.892988                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.483002                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.000830                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.000759                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.018149                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.111603                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.000830                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.000759                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.018149                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.111603                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52204.081633                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 52255.653809                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 52565.866543                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 14585.783402                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.141080                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52204.081633                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 52255.653809                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52195.550427                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52204.081633                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 52255.653809                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52195.550427                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              141515                       # number of writebacks
system.l2c.writebacks::total                   141515                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           98                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst        19676                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data        45242                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           65023                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data         2687                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         2687                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data       141494                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        141494                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker           98                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst         19676                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data        186736                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total           206517                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker           98                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst        19676                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data       186736                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total          206517                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      3927500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       280000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst    787879000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data   1825148000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   2617234500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    107845000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    107845000                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5661229500                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5661229500                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      3927500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker       280000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst    787879000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data   7486377500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   8278464000                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      3927500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker       280000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst    787879000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data   7486377500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   8278464000                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59975987000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total  59975987000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1230144500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1230144500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data  61206131500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total  61206131500                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000830                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000759                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.018148                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.032778                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.892988                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.483002                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000830                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000759                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst     0.018148                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data     0.111603                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000830                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000759                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst     0.018148                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data     0.111603                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.640781                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40341.894700                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40135.839226                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.385599                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.640781                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.702917                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40076.530612                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.640781                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.702917                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.iocache.replacements                     47576                       # number of replacements
system.iocache.tagsinuse                     0.159321                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                     47592                       # Sample count of references to valid blocks.
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.warmup_cycle              4996368196000                       # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide     0.159321                       # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide     0.009958                       # Average percentage of cache occupancy
system.iocache.occ_percent::total            0.009958                       # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47631                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47631                       # number of overall misses
system.iocache.overall_misses::total            47631                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    114195932                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    114195932                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6370894160                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total   6370894160                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide   6485090092                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   6485090092                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide   6485090092                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   6485090092                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47631                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47631                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47631                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47631                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125352.285401                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136363.316781                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136152.717600                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136152.717600                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs      68835510                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                11261                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs  6112.735103                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          911                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          911                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47631                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47631                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47631                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66802976                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total     66802976                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3941136864                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   3941136864                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4007939840                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   4007939840                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4007939840                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   4007939840                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73329.282108                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84356.525342                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84145.616090                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.numCycles                        461736319                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 90084371                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           90084371                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1179546                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              84316538                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 81732802                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           29640549                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      447158079                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    90084371                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           81732802                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     169862026                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 5320379                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     145881                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles              102119338                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                37850                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         39504                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          372                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9392758                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                524186                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    5360                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          305948772                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.876024                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.383488                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                136524607     44.62%     44.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1781462      0.58%     45.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72780882     23.79%     68.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   993009      0.32%     69.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1639605      0.54%     69.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  3682017      1.20%     71.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1148071      0.38%     71.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1456036      0.48%     71.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 85943083     28.09%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            305948772                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.195099                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.968427                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 34742596                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              98230101                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 164036692                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4836131                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4103252                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              876669813                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   827                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4103252                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 39030266                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                68185463                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       10584671                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 164072016                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              19973104                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              872862955                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 10194                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12946310                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               3889382                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           874188806                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1710305089                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1710304369                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               720                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             843320455                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 30868344                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             477917                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         485258                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  46626951                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             18944692                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10483519                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1301190                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1038101                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  865973387                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1727922                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 864611178                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            114248                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        26054957                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     37073399                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         207270                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     305948772                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.826000                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.403043                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            99370843     32.48%     32.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            25451279      8.32%     40.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            14262788      4.66%     45.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             9410835      3.08%     48.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            79123808     25.86%     74.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4863158      1.59%     75.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72802263     23.80%     99.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              533166      0.17%     99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              130632      0.04%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       305948772                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  169581      8.02%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1777046     84.08%     92.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                166802      7.89%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            304260      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             829639344     95.96%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     95.99% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25194661      2.91%     98.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9472913      1.10%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              864611178                       # Type of FU issued
system.cpu.iq.rate                           1.872521                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2113429                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.002444                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2037542293                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         893767044                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    854207329                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 316                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                340                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           80                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              866420202                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     145                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1589122                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3614563                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        21772                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12029                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2051269                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      7821662                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          2623                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4103252                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                45514835                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6136303                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           867701309                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            314417                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              18944692                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10483519                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             889203                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                5413874                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12817                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12029                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         702671                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       628126                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1330797                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             862708188                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              24767979                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1902989                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     33996128                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 86527576                       # Number of branches executed
system.cpu.iew.exec_stores                    9228149                       # Number of stores executed
system.cpu.iew.exec_rate                     1.868400                       # Inst execution rate
system.cpu.iew.wb_sent                      862244747                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     854207409                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 668533054                       # num instructions producing a value
system.cpu.iew.wb_consumers                1167360089                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.849990                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.572688                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      426629675                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        840716593                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts        26871696                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1520650                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1183899                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    301861557                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.785107                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863294                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    121093745     40.12%     40.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     14426665      4.78%     44.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4304237      1.43%     46.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     76676312     25.40%     71.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3920373      1.30%     73.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1782325      0.59%     73.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1109784      0.37%     73.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71984231     23.85%     97.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6563885      2.17%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    301861557                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            426629675                       # Number of instructions committed
system.cpu.commit.committedOps              840716593                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       23762376                       # Number of memory references committed
system.cpu.commit.loads                      15330126                       # Number of loads committed
system.cpu.commit.membars                      781563                       # Number of memory barriers committed
system.cpu.commit.branches                   85529575                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 768542107                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6563885                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1162802870                       # The number of ROB reads
system.cpu.rob.rob_writes                  1739294618                       # The number of ROB writes
system.cpu.timesIdled                         2882631                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       155787547                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9848837790                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   426629675                       # Number of Instructions Simulated
system.cpu.committedOps                     840716593                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             426629675                       # Number of Instructions Simulated
system.cpu.cpi                               1.082288                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.082288                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.923968                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.923968                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1404705112                       # number of integer regfile reads
system.cpu.int_regfile_writes               855482985                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        80                       # number of floating regfile reads
system.cpu.misc_regfile_reads               281196998                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 410876                       # number of misc regfile writes
system.cpu.icache.replacements                1083725                       # number of replacements
system.cpu.icache.tagsinuse                510.022776                       # Cycle average of tags in use
system.cpu.icache.total_refs                  8238065                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                1084236                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   7.598037                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle            56617488000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     510.022776                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.996138                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.996138                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst      8238065                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8238065                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8238065                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8238065                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8238065                       # number of overall hits
system.cpu.icache.overall_hits::total         8238065                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1154689                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1154689                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1154689                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1154689                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1154689                       # number of overall misses
system.cpu.icache.overall_misses::total       1154689                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  17243109487                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  17243109487                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  17243109487                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  17243109487                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  17243109487                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  17243109487                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9392754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9392754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9392754                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9392754                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9392754                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9392754                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122934                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.122934                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.122934                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14933.120076                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14933.120076                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14933.120076                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs      2884989                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               300                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs  9616.630000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks         1570                       # number of writebacks
system.cpu.icache.writebacks::total              1570                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69164                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        69164                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        69164                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        69164                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        69164                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        69164                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1085525                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1085525                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1085525                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1085525                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1085525                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1085525                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13103385489                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  13103385489                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13103385489                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  13103385489                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13103385489                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  13103385489                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115570                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115570                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115570                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12071.012173                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12071.012173                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12071.012173                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements        11375                       # number of replacements
system.cpu.itb_walker_cache.tagsinuse        6.006905                       # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs          28918                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs        11386                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs         2.539786                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5142961834000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.006905                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375432                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total     0.375432                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        28987                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        28987                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        28990                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        28990                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        28990                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        28990                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        12232                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        12232                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        12232                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        12232                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        12232                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        12232                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    154656000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    154656000                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    154656000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    154656000                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    154656000                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    154656000                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41219                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        41219                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        41222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        41222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.296756                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.296735                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.296735                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12643.557881                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12643.557881                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12643.557881                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1402                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1402                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        12232                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        12232                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        12232                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        12232                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        12232                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        12232                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    117502000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    117502000                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    117502000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    117502000                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    117502000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    117502000                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.296756                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.296735                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.296735                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9606.115108                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9606.115108                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9606.115108                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements       125889                       # number of replacements
system.cpu.dtb_walker_cache.tagsinuse       12.942075                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs         147310                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs       125903                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs         1.170028                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5108639465000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.942075                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.808880                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total     0.808880                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       147324                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       147324                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       147324                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       147324                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       147324                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       147324                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       126858                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total       126858                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       126858                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total       126858                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       126858                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total       126858                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1765137000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1765137000                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1765137000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total   1765137000                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1765137000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total   1765137000                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       274182                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       274182                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       274182                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       274182                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       274182                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       274182                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.462678                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.462678                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.462678                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13914.274228                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13914.274228                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13914.274228                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        38155                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        38155                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       126858                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       126858                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       126858                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total       126858                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       126858                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total       126858                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1381422000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1381422000                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1381422000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1381422000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1381422000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1381422000                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.462678                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.462678                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.462678                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10889.514260                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1673228                       # number of replacements
system.cpu.dcache.tagsinuse                511.997037                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 19088314                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1673740                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  11.404587                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               34328000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997037                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     10979879                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10979879                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8104687                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8104687                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      19084566                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19084566                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19084566                       # number of overall hits
system.cpu.dcache.overall_hits::total        19084566                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2411794                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2411794                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       318210                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       318210                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2730004                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2730004                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2730004                       # number of overall misses
system.cpu.dcache.overall_misses::total       2730004                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  36160191000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  36160191000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10588613980                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10588613980                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  46748804980                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  46748804980                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  46748804980                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  46748804980                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13391673                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13391673                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8422897                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8422897                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21814570                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21814570                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21814570                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21814570                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180097                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037779                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.125146                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.125146                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14993.067816                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33275.553817                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17124.079298                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17124.079298                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     23292480                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              3427                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  6796.755179                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1561454                       # number of writebacks
system.cpu.dcache.writebacks::total           1561454                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1030426                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1030426                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22364                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        22364                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1052790                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1052790                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1052790                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1052790                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381368                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1381368                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       295846                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       295846                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1677214                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1677214                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1677214                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1677214                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  18158276000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  18158276000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9372225480                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   9372225480                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27530501480                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  27530501480                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27530501480                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27530501480                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208380500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208380500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1393791500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1393791500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86602172000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  86602172000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035124                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076885                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076885                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13145.140180                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31679.405772                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16414.423848                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16414.423848                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------