path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.137972                       # Number of seconds simulated
sim_ticks                                5137971999000                       # Number of ticks simulated
final_tick                               5137971999000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 151274                       # Simulator instruction rate (inst/s)
host_op_rate                                   299020                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1905679647                       # Simulator tick rate (ticks/s)
host_mem_usage                                 770140                       # Number of bytes of host memory used
host_seconds                                  2696.14                       # Real time elapsed on the host
sim_insts                                   407854776                       # Number of instructions simulated
sim_ops                                     806198141                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide      2477120                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         3136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1034624                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10750336                       # Number of bytes read from this memory
system.physmem.bytes_read::total             14265472                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1034624                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1034624                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9529024                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9529024                       # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide        38705                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           49                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16166                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             167974                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                222898                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          148891                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               148891                       # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide       482120                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            610                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               201368                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2092331                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2776479                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          201368                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             201368                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1854627                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1854627                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1854627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide       482120                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           610                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              201368                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2092331                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4631107                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        222898                       # Number of read requests accepted
system.physmem.writeReqs                       148891                       # Number of write requests accepted
system.physmem.readBursts                      222898                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     148891                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 14252672                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     12800                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   9527360                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  14265472                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                9529024                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      200                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1701                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               14548                       # Per bank write bursts
system.physmem.perBankRdBursts::1               13887                       # Per bank write bursts
system.physmem.perBankRdBursts::2               14162                       # Per bank write bursts
system.physmem.perBankRdBursts::3               13520                       # Per bank write bursts
system.physmem.perBankRdBursts::4               14300                       # Per bank write bursts
system.physmem.perBankRdBursts::5               13581                       # Per bank write bursts
system.physmem.perBankRdBursts::6               13426                       # Per bank write bursts
system.physmem.perBankRdBursts::7               13413                       # Per bank write bursts
system.physmem.perBankRdBursts::8               13607                       # Per bank write bursts
system.physmem.perBankRdBursts::9               13662                       # Per bank write bursts
system.physmem.perBankRdBursts::10              13602                       # Per bank write bursts
system.physmem.perBankRdBursts::11              13631                       # Per bank write bursts
system.physmem.perBankRdBursts::12              14336                       # Per bank write bursts
system.physmem.perBankRdBursts::13              14588                       # Per bank write bursts
system.physmem.perBankRdBursts::14              14340                       # Per bank write bursts
system.physmem.perBankRdBursts::15              14095                       # Per bank write bursts
system.physmem.perBankWrBursts::0                9881                       # Per bank write bursts
system.physmem.perBankWrBursts::1                9301                       # Per bank write bursts
system.physmem.perBankWrBursts::2                9417                       # Per bank write bursts
system.physmem.perBankWrBursts::3                9104                       # Per bank write bursts
system.physmem.perBankWrBursts::4                9702                       # Per bank write bursts
system.physmem.perBankWrBursts::5                8858                       # Per bank write bursts
system.physmem.perBankWrBursts::6                8862                       # Per bank write bursts
system.physmem.perBankWrBursts::7                8906                       # Per bank write bursts
system.physmem.perBankWrBursts::8                8978                       # Per bank write bursts
system.physmem.perBankWrBursts::9                9056                       # Per bank write bursts
system.physmem.perBankWrBursts::10               9081                       # Per bank write bursts
system.physmem.perBankWrBursts::11               9102                       # Per bank write bursts
system.physmem.perBankWrBursts::12               9605                       # Per bank write bursts
system.physmem.perBankWrBursts::13               9854                       # Per bank write bursts
system.physmem.perBankWrBursts::14               9646                       # Per bank write bursts
system.physmem.perBankWrBursts::15               9512                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
system.physmem.totGap                    5137971883500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  222898                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 148891                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    173419                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     13832                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      4649                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2839                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      2570                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      4077                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      3447                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      3320                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      2968                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      1935                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     1633                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1479                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1288                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1096                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      836                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      757                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      725                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      696                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      691                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      416                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       25                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1621                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1713                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     6088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     6446                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     6550                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     6593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     6786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     6786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6856                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     8981                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7771                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     9165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8452                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8587                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2877                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     2483                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     2347                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2192                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2164                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2092                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1791                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1568                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1040                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      892                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      750                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      634                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      513                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      284                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      218                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      132                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        49868                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      381.994064                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     221.175651                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     374.202346                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          15813     31.71%     31.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        11064     22.19%     53.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         5080     10.19%     64.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2824      5.66%     69.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1980      3.97%     73.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1284      2.57%     76.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          922      1.85%     78.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          716      1.44%     79.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10185     20.42%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          49868                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          8142                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        27.350037                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      531.765782                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           8141     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            8142                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          8142                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        18.283591                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.627324                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        6.611364                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            6056     74.38%     74.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            1276     15.67%     90.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21             101      1.24%     91.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              41      0.50%     91.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              52      0.64%     92.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              70      0.86%     93.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              65      0.80%     94.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31              71      0.87%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33              51      0.63%     95.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35              44      0.54%     96.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37              56      0.69%     96.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39              33      0.41%     97.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41              34      0.42%     97.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43              29      0.36%     98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45              35      0.43%     98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47              23      0.28%     98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49              19      0.23%     98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51              12      0.15%     99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53              12      0.15%     99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55               9      0.11%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57               6      0.07%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59               7      0.09%     99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               2      0.02%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63              13      0.16%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-65              13      0.16%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::66-67               1      0.01%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::70-71               1      0.01%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-73               4      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::74-75               3      0.04%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-77               2      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-81               1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            8142                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5275412250                       # Total ticks spent queuing
system.physmem.totMemAccLat                9510468500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1113490000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  3121566250                       # Total ticks spent accessing banks
system.physmem.avgQLat                       23688.64                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    14017.04                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42705.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.78                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.02                       # Average write queue length when enqueuing
system.physmem.readRowHits                     186969                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    110725                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   83.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.37                       # Row buffer hit rate for writes
system.physmem.avgGap                     13819590.91                       # Average gap between requests
system.physmem.pageHitRate                      80.11                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               0.14                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                      5100645                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              662331                       # Transaction distribution
system.membus.trans_dist::ReadResp             662323                       # Transaction distribution
system.membus.trans_dist::WriteReq              13764                       # Transaction distribution
system.membus.trans_dist::WriteResp             13764                       # Transaction distribution
system.membus.trans_dist::Writeback            148891                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2168                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1718                       # Transaction distribution
system.membus.trans_dist::ReadExReq            179464                       # Transaction distribution
system.membus.trans_dist::ReadExResp           179461                       # Transaction distribution
system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471038                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475146                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721276                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       133006                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       133006                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1857568                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241802                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550149                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18330624                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20122575                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5463872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total      5463872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            25593019                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               25593019                       # Total data (bytes)
system.membus.snoop_data_through_bus           613952                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           250521000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583253500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1611616249                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               10500                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3152435901                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy          429736248                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47579                       # number of replacements
system.iocache.tags.tagsinuse                0.116331                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992993838000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116331                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007271                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.007271                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428697                       # Number of tag accesses
system.iocache.tags.data_accesses              428697                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          913                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              913                       # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) misses
system.iocache.demand_misses::total             47633                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide        47633                       # number of overall misses
system.iocache.overall_misses::total            47633                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149265435                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    149265435                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11474717915                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total  11474717915                       # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide  11623983350                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  11623983350                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide  11623983350                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  11623983350                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          913                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            913                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide        47633                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           47633                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide        47633                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          47633                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 163488.975904                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 245606.119756                       # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 244032.148930                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 244032.148930                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs        177888                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                14382                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    12.368794                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46668                       # number of writebacks
system.iocache.writebacks::total                46668                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          913                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          913                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total        47633                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide        47633                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total        47633                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101762935                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    101762935                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9043225919                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total   9043225919                       # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9144988854                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9144988854                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609                       # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.iobus.throughput                        637649                       # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq               225561                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225561                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471038                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95266                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95266                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  569590                       # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio        13618                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total       241802                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027848                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total              3276222                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus                 3276222                       # Total data (bytes)
system.iobus.reqLayer0.occupancy              3918904                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8851000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy            20374000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy           425268102                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460167000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            53403752                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                85606951                       # Number of BP lookups
system.cpu.branchPred.condPredicted          85606951                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            878900                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             79252981                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                77536604                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.834306                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1442152                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             179942                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        453123649                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           25513299                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      422793316                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85606951                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           78978756                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     162666775                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 3977899                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     109317                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles               70887668                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                43514                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         89257                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   8479758                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                384207                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    2414                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          262364646                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.182537                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.411732                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                100112047     38.16%     38.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  1537808      0.59%     38.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 71834602     27.38%     66.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                   894624      0.34%     66.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1560586      0.59%     67.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2393199      0.91%     67.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1018516      0.39%     68.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1331320      0.51%     68.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81681944     31.13%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            262364646                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.188926                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.933064                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 29407134                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              68048451                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158512522                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3341909                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                3054630                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              832669874                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                   887                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                3054630                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 32105381                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                42832622                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       12466754                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158806940                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13098319                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              829768905                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 20738                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                6073581                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               5148249                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           991466417                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1800660067                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1107048961                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               106                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964157062                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 27309353                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             454429                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         460129                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  29597584                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             16731616                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores             9822119                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1090956                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores           912656                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  824999655                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1185445                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 821065367                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            147374                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        19153823                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     29264539                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         130709                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     262364646                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         3.129482                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.399412                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            75980319     28.96%     28.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            15750588      6.00%     34.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10556494      4.02%     38.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7365908      2.81%     41.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            75746368     28.87%     70.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3736962      1.42%     72.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72307682     27.56%     99.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              774907      0.30%     99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              145418      0.06%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       262364646                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  352804     33.38%     33.38% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    241      0.02%     33.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                     895      0.08%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 548620     51.91%     85.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                154313     14.60%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            307554      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             793584898     96.65%     96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150109      0.02%     96.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                124066      0.02%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             17676623      2.15%     98.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9222117      1.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              821065367                       # Type of FU issued
system.cpu.iq.rate                           1.812012                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     1056873                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.001287                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1905808819                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         845349453                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    817155578                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 173                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                180                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           48                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              821814606                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                      80                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1693534                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2731831                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        17734                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12108                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1395931                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1932011                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         12232                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                3054630                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                30960729                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2157350                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           826185100                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            241589                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              16731616                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts              9822119                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             690497                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1620390                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12858                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12108                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         495281                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       506440                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1001721                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             819661058                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              17373288                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1404308                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     26412112                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83101028                       # Number of branches executed
system.cpu.iew.exec_stores                    9038824                       # Number of stores executed
system.cpu.iew.exec_rate                     1.808913                       # Inst execution rate
system.cpu.iew.wb_sent                      819257147                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     817155626                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 638657480                       # num instructions producing a value
system.cpu.iew.wb_consumers                1044041746                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.803383                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.611716                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        19877862                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1054736                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            888910                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    259310016                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     3.109013                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.863250                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     87730314     33.83%     33.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11862694      4.57%     38.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3835821      1.48%     39.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74768182     28.83%     68.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2381229      0.92%     69.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1479438      0.57%     70.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       861979      0.33%     70.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     70857593     27.33%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5532766      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    259310016                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            407854776                       # Number of instructions committed
system.cpu.commit.committedOps              806198141                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22425972                       # Number of memory references committed
system.cpu.commit.loads                      13999784                       # Number of loads committed
system.cpu.commit.membars                      474669                       # Number of memory barriers committed
system.cpu.commit.branches                   82177261                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735033306                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1155486                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               5532766                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1079774887                       # The number of ROB reads
system.cpu.rob.rob_writes                  1655221365                       # The number of ROB writes
system.cpu.timesIdled                         1257777                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                       190759003                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9822826051                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   407854776                       # Number of Instructions Simulated
system.cpu.committedOps                     806198141                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             407854776                       # Number of Instructions Simulated
system.cpu.cpi                               1.110993                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.110993                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.900096                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.900096                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1088904390                       # number of integer regfile reads
system.cpu.int_regfile_writes               653903158                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 415697548                       # number of cc regfile reads
system.cpu.cc_regfile_writes                321557341                       # number of cc regfile writes
system.cpu.misc_regfile_reads               264102486                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 402568                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                53587278                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        3014875                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3014340                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13764                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13764                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1579042                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2208                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2208                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       336648                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       289942                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1911181                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6131826                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18757                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       150026                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8211790                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61153920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207959183                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       582080                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5191488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      274886671                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         274861071                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       468864                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4035423910                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       600000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1436807344                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3142634309                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      14495745                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     103414152                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements            955079                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.954947                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             7470392                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            955591                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              7.817562                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147668859250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.954947                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996006                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996006                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses           9435405                       # Number of tag accesses
system.cpu.icache.tags.data_accesses          9435405                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      7470392                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         7470392                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       7470392                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          7470392                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      7470392                       # number of overall hits
system.cpu.icache.overall_hits::total         7470392                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1009362                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1009362                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1009362                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1009362                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1009362                       # number of overall misses
system.cpu.icache.overall_misses::total       1009362                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14063763284                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14063763284                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14063763284                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14063763284                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14063763284                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14063763284                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      8479754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      8479754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      8479754                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      8479754                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      8479754                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      8479754                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119032                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.119032                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.119032                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.119032                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.119032                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.119032                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13933.319546                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13933.319546                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         4512                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               173                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    26.080925                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53711                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        53711                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        53711                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        53711                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        53711                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        53711                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       955651                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       955651                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       955651                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       955651                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       955651                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       955651                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11613116903                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  11613116903                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11613116903                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  11613116903                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11613116903                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  11613116903                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112698                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.112698                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.112698                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         8788                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     5.050842                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        20362                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         8802                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.313338                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     5.050842                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.315678                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.315678                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        69716                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        69716                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20363                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        20363                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20365                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        20365                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20365                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        20365                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9662                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         9662                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9662                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         9662                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9662                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         9662                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    109674498                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    109674498                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    109674498                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    109674498                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    109674498                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    109674498                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30025                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        30025                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30027                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        30027                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30027                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        30027                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.321799                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.321799                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.321777                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.321777                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.321777                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.321777                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         1311                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         1311                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9662                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9662                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9662                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total         9662                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9662                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total         9662                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     90345008                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     90345008                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     90345008                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     90345008                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     90345008                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     90345008                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.321799                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.321799                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.321777                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.321777                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9350.549369                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        67950                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    13.831671                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        92323                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        67966                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.358370                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.831671                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.864479                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.864479                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       391373                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       391373                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92323                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        92323                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92323                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        92323                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92323                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        92323                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68909                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        68909                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68909                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        68909                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68909                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        68909                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    862549215                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    862549215                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    862549215                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    862549215                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    862549215                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    862549215                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       161232                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       161232                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       161232                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       161232                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       161232                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       161232                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.427390                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.427390                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.427390                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        16529                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        16529                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68909                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68909                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68909                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        68909                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68909                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        68909                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    724629911                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    724629911                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    724629911                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.427390                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.427390                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.427390                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1659840                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.996448                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            18992605                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1660352                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.438903                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          40084250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.996448                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          87845319                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         87845319                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     10889826                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        10889826                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8100117                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8100117                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data      18989943                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         18989943                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     18989943                       # number of overall hits
system.cpu.dcache.overall_hits::total        18989943                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2239768                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2239768                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       316527                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       316527                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2556295                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2556295                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2556295                       # number of overall misses
system.cpu.dcache.overall_misses::total       2556295                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  32903838390                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  32903838390                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  11976667737                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  11976667737                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  44880506127                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  44880506127                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  44880506127                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  44880506127                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     13129594                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13129594                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8416644                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8416644                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21546238                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21546238                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21546238                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21546238                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170589                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.170589                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037607                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037607                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.118642                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.118642                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.118642                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.118642                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17556.857142                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17556.857142                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       388578                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             42350                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.175396                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1561202                       # number of writebacks
system.cpu.dcache.writebacks::total           1561202                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       869210                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       869210                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        24502                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        24502                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       893712                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       893712                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       893712                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       893712                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370558                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1370558                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292025                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       292025                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1662583                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1662583                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1662583                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1662583                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17741695710                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  17741695710                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11080104948                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11080104948                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28821800658                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28821800658                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28821800658                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28821800658                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363380000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363380000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536381000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536381000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899761000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899761000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104387                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104387                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034696                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034696                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.077163                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.077163                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12944.870418                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12944.870418                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.316404                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.316404                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           111989                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64821.159717                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3780351                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176044                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.473899                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.121398                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.097025                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2916.382816                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.771976                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000154                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.044500                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.172460                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989092                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64055                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3496                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6269                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53720                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977402                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         34623360                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        34623360                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64539                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7780                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       939362                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1333943                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2345624                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1579042                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1579042                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          315                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          315                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       156902                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       156902                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        64539                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         7780                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       939362                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1490845                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2502526                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        64539                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         7780                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       939362                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1490845                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2502526                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           49                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            4                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16168                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35908                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52129                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1443                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1443                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133016                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133016                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           49                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            4                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16168                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       168924                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185145                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           49                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            4                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16168                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       168924                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185145                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4159750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       369250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1243133741                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2836550442                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4084213183                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17687795                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17687795                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9175416141                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9175416141                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4159750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       369250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1243133741                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12011966583                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13259629324                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4159750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       369250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1243133741                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12011966583                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13259629324                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64588                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7784                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       955530                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1369851                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2397753                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1579042                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1579042                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1758                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1758                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       289918                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       289918                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64588                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         7784                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       955530                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1659769                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2687671                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64588                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         7784                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       955530                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1659769                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2687671                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000514                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016920                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026213                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021741                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820819                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820819                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.458806                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.458806                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000514                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016920                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101776                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.068887                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000514                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016920                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101776                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.068887                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 92312.500000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76888.529255                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78994.943801                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78348.197414                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12257.654193                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12257.654193                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68979.792965                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68979.792965                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71617.539356                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71617.539356                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102223                       # number of writebacks
system.cpu.l2cache.writebacks::total           102223                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           49                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            4                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16166                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35906                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52125                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1443                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1443                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133016                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133016                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           49                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            4                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16166                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       168922                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185141                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           49                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            4                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16166                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       168922                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185141                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       319250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1040184259                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2389977554                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3434033313                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15330925                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15330925                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7506177359                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7506177359                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       319250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1040184259                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9896154913                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10940210672                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       319250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1040184259                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9896154913                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  10940210672                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250256000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250256000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370696500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370696500                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620952500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620952500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026212                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021739                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820819                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820819                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.458806                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.458806                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.068885                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.068885                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------