path: root/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.121937                       # Number of seconds simulated
sim_ticks                                5121937205500                       # Number of ticks simulated
final_tick                               5121937205500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 133395                       # Simulator instruction rate (inst/s)
host_op_rate                                   263673                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1674179733                       # Simulator tick rate (ticks/s)
host_mem_usage                                 798472                       # Number of bytes of host memory used
host_seconds                                  3059.37                       # Real time elapsed on the host
sim_insts                                   408103625                       # Number of instructions simulated
sim_ops                                     806672783                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker         3968                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           1046784                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10762752                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11842240                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1046784                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1046784                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9571648                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9571648                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker           62                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              16356                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             168168                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                185035                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          149557                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               149557                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker            775                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               204373                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2101305                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5535                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2312063                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          204373                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             204373                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1868755                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1868755                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1868755                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           775                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              204373                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2101305                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5535                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4180818                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        185035                       # Number of read requests accepted
system.physmem.writeReqs                       196277                       # Number of write requests accepted
system.physmem.readBursts                      185035                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     196277                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 11833600                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8640                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  12404928                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  11842240                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               12561728                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      135                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2419                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           1772                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               11869                       # Per bank write bursts
system.physmem.perBankRdBursts::1               11279                       # Per bank write bursts
system.physmem.perBankRdBursts::2               11900                       # Per bank write bursts
system.physmem.perBankRdBursts::3               11555                       # Per bank write bursts
system.physmem.perBankRdBursts::4               12140                       # Per bank write bursts
system.physmem.perBankRdBursts::5               11427                       # Per bank write bursts
system.physmem.perBankRdBursts::6               11446                       # Per bank write bursts
system.physmem.perBankRdBursts::7               11418                       # Per bank write bursts
system.physmem.perBankRdBursts::8               11156                       # Per bank write bursts
system.physmem.perBankRdBursts::9               11288                       # Per bank write bursts
system.physmem.perBankRdBursts::10              11167                       # Per bank write bursts
system.physmem.perBankRdBursts::11              11604                       # Per bank write bursts
system.physmem.perBankRdBursts::12              11474                       # Per bank write bursts
system.physmem.perBankRdBursts::13              12255                       # Per bank write bursts
system.physmem.perBankRdBursts::14              11757                       # Per bank write bursts
system.physmem.perBankRdBursts::15              11165                       # Per bank write bursts
system.physmem.perBankWrBursts::0               12900                       # Per bank write bursts
system.physmem.perBankWrBursts::1               13064                       # Per bank write bursts
system.physmem.perBankWrBursts::2               11983                       # Per bank write bursts
system.physmem.perBankWrBursts::3               10698                       # Per bank write bursts
system.physmem.perBankWrBursts::4               10899                       # Per bank write bursts
system.physmem.perBankWrBursts::5               11057                       # Per bank write bursts
system.physmem.perBankWrBursts::6               11263                       # Per bank write bursts
system.physmem.perBankWrBursts::7               11237                       # Per bank write bursts
system.physmem.perBankWrBursts::8               11985                       # Per bank write bursts
system.physmem.perBankWrBursts::9               12151                       # Per bank write bursts
system.physmem.perBankWrBursts::10              12710                       # Per bank write bursts
system.physmem.perBankWrBursts::11              12714                       # Per bank write bursts
system.physmem.perBankWrBursts::12              13328                       # Per bank write bursts
system.physmem.perBankWrBursts::13              13119                       # Per bank write bursts
system.physmem.perBankWrBursts::14              12767                       # Per bank write bursts
system.physmem.perBankWrBursts::15              11952                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    5121937091000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  185035                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 196277                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    170268                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     11906                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2015                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       383                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        39                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2596                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4963                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     9714                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    11101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    11484                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    12594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    13080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    14093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    13730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    14384                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    13174                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    12623                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    11181                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    10537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8939                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8632                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     8525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     8308                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      450                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      334                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      227                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      212                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      169                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      126                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      106                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       89                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       67                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        74867                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      323.753643                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     187.995922                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     341.769329                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          27720     37.03%     37.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17254     23.05%     60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         7564     10.10%     70.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         4205      5.62%     75.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3013      4.02%     79.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2021      2.70%     82.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1360      1.82%     84.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1151      1.54%     85.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        10579     14.13%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          74867                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          7807                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.681312                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      544.837786                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           7806     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            7807                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          7807                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        24.827334                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       20.378246                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       23.718812                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            6359     81.45%     81.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              60      0.77%     82.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              16      0.20%     82.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             274      3.51%     85.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             187      2.40%     88.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39              50      0.64%     88.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43              34      0.44%     89.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              41      0.53%     89.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             177      2.27%     92.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              17      0.22%     92.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              12      0.15%     92.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              13      0.17%     92.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67              35      0.45%     93.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              16      0.20%     93.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               8      0.10%     93.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              51      0.65%     94.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             104      1.33%     95.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               7      0.09%     95.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91              10      0.13%     95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95              27      0.35%     96.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99             148      1.90%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             8      0.10%     98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             6      0.08%     98.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             2      0.03%     98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115            33      0.42%     98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             2      0.03%     98.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123            12      0.15%     98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             3      0.04%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            28      0.36%     99.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             4      0.05%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             6      0.08%     99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            12      0.15%     99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             3      0.04%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155             3      0.04%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             7      0.09%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             8      0.10%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171             2      0.03%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             3      0.04%     99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             4      0.05%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.01%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.03%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.01%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207             4      0.05%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::244-247             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            7807                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1977045500                       # Total ticks spent queuing
system.physmem.totMemAccLat                5443920500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    924500000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10692.51                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29442.51                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           2.42                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        2.45                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.97                       # Average write queue length when enqueuing
system.physmem.readRowHits                     151994                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    151865                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.20                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.34                       # Row buffer hit rate for writes
system.physmem.avgGap                     13432404.67                       # Average gap between requests
system.physmem.pageHitRate                      80.23                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  281753640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  153734625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 725665200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                603294480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           334539922080                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           129490880310                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           2959572897750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             3425368148085                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.764386                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   4923440733500                       # Time in different power states
system.physmem_0.memoryStateTime::REF    171032680000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     27462249000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  284240880                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  155091750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 716547000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                652704480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           334539922080                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           129160456155                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           2959862743500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             3425371705845                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.765080                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   4923925616750                       # Time in different power states
system.physmem_1.memoryStateTime::REF    171032680000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     26978805250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                86925803                       # Number of BP lookups
system.cpu.branchPred.condPredicted          86925803                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            896443                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             80098191                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                78212465                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.645732                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1561001                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             180305                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                        449601109                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           27685322                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      429319828                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    86925803                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           79773466                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     418005810                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1881156                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                     145066                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                56340                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        216419                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles           69                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          534                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                   9181154                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                448969                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                    4854                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          447050138                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.894862                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.052352                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                281515886     62.97%     62.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2210439      0.49%     63.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72204596     16.15%     79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  1602689      0.36%     79.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  2146844      0.48%     80.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  2305649      0.52%     80.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1524322      0.34%     81.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1908424      0.43%     81.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 81631289     18.26%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            447050138                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.193340                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.954891                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 23043701                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             264854286                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 150758526                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               7453047                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 940578                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts              838760021                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                 940578                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 25901615                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               223330945                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       13194802                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 154665359                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              29016839                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              835288144                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                480498                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               12432167                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 195018                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               13714744                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           997792221                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1814468169                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1115407405                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               373                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             964705167                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 33087052                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts             465878                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts         469687                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  39083891                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             17351329                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            10177979                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1302580                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1089364                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  829800190                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             1202669                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 824540368                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            243435                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        23398238                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     36211142                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         151712                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     447050138                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.844402                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.418243                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           262726585     58.77%     58.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            13876357      3.10%     61.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            10104726      2.26%     64.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             6925504      1.55%     65.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            74353941     16.63%     82.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             4450821      1.00%     83.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            72845421     16.29%     99.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1198612      0.27%     99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              568171      0.13%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       447050138                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1991949     71.90%     71.90% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                    123      0.00%     71.91% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                    1473      0.05%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     2      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     71.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                 615411     22.21%     94.17% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                161409      5.83%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass            289852      0.04%      0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             796144481     96.56%     96.59% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               150888      0.02%     96.61% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                125650      0.02%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                 123      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             18436778      2.24%     98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite             9392596      1.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              824540368                       # Type of FU issued
system.cpu.iq.rate                           1.833938                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2770367                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.003360                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2099144137                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         854413357                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    819991210                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 538                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                510                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          185                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              827020625                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     258                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1864655                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      3351077                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        13836                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14513                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1751193                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2224299                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         72996                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 940578                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               205605732                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               9422457                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           831002859                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            153624                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              17351329                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             10177979                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts             705669                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 415252                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8108448                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14513                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         513988                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       533382                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1047370                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             822936172                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              18038480                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1469642                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                     27207078                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 83328554                       # Number of branches executed
system.cpu.iew.exec_stores                    9168598                       # Number of stores executed
system.cpu.iew.exec_rate                     1.830370                       # Inst execution rate
system.cpu.iew.wb_sent                      822433213                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     819991395                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 641244168                       # num instructions producing a value
system.cpu.iew.wb_consumers                1050921658                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.823820                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.610173                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        24200169                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         1050957                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            908606                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    443415424                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.819226                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.675431                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    272547704     61.47%     61.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11191107      2.52%     63.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3581688      0.81%     64.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     74592593     16.82%     81.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2424395      0.55%     82.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1607477      0.36%     82.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       945915      0.21%     82.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     71066294     16.03%     98.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      5458251      1.23%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    443415424                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            408103625                       # Number of instructions committed
system.cpu.commit.committedOps              806672783                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       22427037                       # Number of memory references committed
system.cpu.commit.loads                      14000251                       # Number of loads committed
system.cpu.commit.membars                      475479                       # Number of memory barriers committed
system.cpu.commit.branches                   82225235                       # Number of branches committed
system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 735463006                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1156113                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass       171674      0.02%      0.02% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        783810008     97.17%     97.19% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          145072      0.02%     97.21% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv           121556      0.02%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt             16      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.22% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        13997671      1.74%     98.96% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite        8426786      1.04%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         806672783                       # Class of committed instruction
system.cpu.commit.bw_lim_events               5458251                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1268751952                       # The number of ROB reads
system.cpu.rob.rob_writes                  1665400460                       # The number of ROB writes
system.cpu.timesIdled                          293768                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2550971                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                   9794270972                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   408103625                       # Number of Instructions Simulated
system.cpu.committedOps                     806672783                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.101684                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.101684                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.907702                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.907702                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1092990942                       # number of integer regfile reads
system.cpu.int_regfile_writes               656343554                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       191                       # number of floating regfile reads
system.cpu.cc_regfile_reads                 416454943                       # number of cc regfile reads
system.cpu.cc_regfile_writes                322187827                       # number of cc regfile writes
system.cpu.misc_regfile_reads               265705543                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 400219                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           1658771                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.995092                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            19161993                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1659283                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             11.548357                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          37454250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.995092                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999990                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          201                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88441081                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88441081                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     11011311                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        11011311                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8082990                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8082990                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        64916                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         64916                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      19094301                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         19094301                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     19159217                       # number of overall hits
system.cpu.dcache.overall_hits::total        19159217                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1795762                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1795762                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       334107                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       334107                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       406359                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       406359                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      2129869                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2129869                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2536228                       # number of overall misses
system.cpu.dcache.overall_misses::total       2536228                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  26474085005                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  26474085005                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  12834716256                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  12834716256                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  39308801261                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  39308801261                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  39308801261                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  39308801261                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     12807073                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12807073                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8417097                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8417097                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       471275                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       471275                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21224170                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21224170                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21695445                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21695445                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.140216                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.140216                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.039694                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.039694                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.862255                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.862255                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.100351                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.100351                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.116901                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.116901                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18455.971358                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 15498.922518                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       371080                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             39978                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.282105                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1560107                       # number of writebacks
system.cpu.dcache.writebacks::total           1560107                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       826960                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       826960                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        44237                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        44237                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       871197                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       871197                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       871197                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       871197                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       968802                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       968802                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289870                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       289870                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data       402896                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total       402896                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1258672                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1258672                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1661568                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1661568                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12247021519                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12247021519                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11168468751                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  11168468751                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   5577776251                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   5577776251                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23415490270                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  23415490270                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28993266521                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28993266521                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97397501000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97397501000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2571147000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2571147000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99968648000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  99968648000                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075646                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075646                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034438                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034438                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.854906                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.854906                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059304                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.059304                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076586                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.076586                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements        75411                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse    15.808771                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs       114018                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs        75427                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.511634                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    15.808771                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.988048                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.988048                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses       457557                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses       457557                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       114018                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total       114018                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       114018                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total       114018                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       114018                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total       114018                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        76507                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total        76507                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        76507                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total        76507                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        76507                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total        76507                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    935770692                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    935770692                       # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    935770692                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total    935770692                       # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    935770692                       # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total    935770692                       # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       190525                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total       190525                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       190525                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total       190525                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       190525                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total       190525                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.401559                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.401559                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.401559                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.401559                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.401559                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.401559                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177435                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177435                       # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177435                       # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177435                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177435                       # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177435                       # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks        22022                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total        22022                       # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        76507                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        76507                       # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        76507                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total        76507                       # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        76507                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total        76507                       # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    782624452                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    782624452                       # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    782624452                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    782624452                       # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    782624452                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    782624452                       # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.401559                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.401559                       # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.401559                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.401559                       # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.401559                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.401559                       # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448965                       # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448965                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448965                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448965                       # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           1000352                       # number of replacements
system.cpu.icache.tags.tagsinuse           509.220531                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs             8118136                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1000864                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs              8.111128                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      147684343000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   509.220531                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.994571                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.994571                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          170                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          10182088                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         10182088                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst      8118136                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total         8118136                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst       8118136                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total          8118136                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst      8118136                       # number of overall hits
system.cpu.icache.overall_hits::total         8118136                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1063017                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1063017                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1063017                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1063017                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1063017                       # number of overall misses
system.cpu.icache.overall_misses::total       1063017                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  14764552848                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  14764552848                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  14764552848                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  14764552848                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  14764552848                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  14764552848                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst      9181153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total      9181153                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst      9181153                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total      9181153                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst      9181153                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total      9181153                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.115783                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.115783                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.115783                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.115783                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.115783                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.115783                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13889.291374                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13889.291374                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         7778                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            8                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs               283                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    27.484099                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets            8                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        62082                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        62082                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        62082                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        62082                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        62082                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        62082                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1000935                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1000935                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1000935                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1000935                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1000935                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1000935                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12121618509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  12121618509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12121618509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  12121618509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12121618509                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  12121618509                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.109021                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.109021                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.109021                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.109021                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.109021                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.109021                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements        14419                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     6.299272                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs        25752                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs        14435                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     1.783997                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.299272                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.393704                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.393704                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        97449                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        97449                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        25750                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total        25750                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        25752                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total        25752                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        25752                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total        25752                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        15315                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total        15315                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        15315                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total        15315                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        15315                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total        15315                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    177860993                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total    177860993                       # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    177860993                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total    177860993                       # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    177860993                       # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total    177860993                       # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        41065                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        41065                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        41067                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        41067                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        41067                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        41067                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.372945                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.372945                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.372927                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.372927                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.372927                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.372927                       # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515704                       # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515704                       # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515704                       # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515704                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515704                       # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515704                       # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks         3318                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total         3318                       # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        15315                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        15315                       # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        15315                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total        15315                       # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        15315                       # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total        15315                       # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    147213025                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    147213025                       # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    147213025                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    147213025                       # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    147213025                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    147213025                       # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.372945                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.372945                       # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.372927                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.372927                       # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.372927                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.372927                       # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9612.342475                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9612.342475                       # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9612.342475                       # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9612.342475                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9612.342475                       # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9612.342475                       # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           112445                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64830.405135                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3843138                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           176455                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            21.779706                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    14.644782                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.444532                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3208.377327                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768115                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000223                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000007                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.048956                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.171932                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989233                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        64010                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          596                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3348                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7208                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52806                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.976715                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         35103909                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        35103909                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        69111                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        12768                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       984459                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1335184                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2401522                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1585447                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1585447                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          309                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          309                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       154410                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       154410                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker        69111                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker        12768                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       984459                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1489594                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2555932                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker        69111                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker        12768                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       984459                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1489594                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2555932                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           62                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        16359                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        35824                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        52251                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1504                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1504                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       133327                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       133327                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker           62                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        16359                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       169151                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        185578                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker           62                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        16359                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       169151                       # number of overall misses
system.cpu.l2cache.overall_misses::total       185578                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5303750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       467500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1250815250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2830285496                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4086871996                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17716796                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     17716796                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9290586712                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   9290586712                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5303750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       467500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   1250815250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12120872208                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13377458708                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5303750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       467500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   1250815250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12120872208                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13377458708                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        69173                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        12774                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst      1000818                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1371008                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2453773                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1585447                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1585447                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1813                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1813                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       287737                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       287737                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker        69173                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker        12774                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst      1000818                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1658745                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2741510                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker        69173                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker        12774                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1000818                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1658745                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2741510                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000470                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016346                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026130                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021294                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.829564                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.829564                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463364                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.463364                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000470                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016346                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.101975                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.067692                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000896                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000470                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016346                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.101975                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.067692                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85544.354839                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77916.666667                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76460.373495                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79005.289638                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 78216.148897                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11779.784574                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11779.784574                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69682.710269                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69682.710269                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85544.354839                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77916.666667                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76460.373495                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71657.112332                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72085.369537                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85544.354839                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77916.666667                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76460.373495                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71657.112332                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72085.369537                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       102890                       # number of writebacks
system.cpu.l2cache.writebacks::total           102890                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            3                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data            3                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data            3                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            6                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           62                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16356                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35821                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        52245                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1504                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         1504                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133327                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       133327                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           62                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        16356                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       169148                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       185572                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           62                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        16356                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       169148                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       185572                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4538750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       391500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1045537500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2387984748                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3438452498                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15960982                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15960982                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7616458286                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7616458286                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4538750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       391500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1045537500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10004443034                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11054910784                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4538750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       391500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1045537500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10004443034                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  11054910784                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89282348000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89282348000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2403570000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2403570000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91685918000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91685918000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000470                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016343                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026127                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021292                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.829564                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.829564                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463364                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463364                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000470                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016343                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101973                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.067690                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000896                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000470                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016343                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101973                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.067690                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        65250                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        3074706                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       3074138                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13919                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1585447                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       287746                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       287746                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError           27                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2001753                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6129358                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        31407                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       167702                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8330220                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64052352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207821235                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      1029888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5836480                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          278739955                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       59032                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      4387424                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.010858                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.103635                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            4339785     98.91%     98.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              47639      1.09%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        4387424                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4074051871                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy       567000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1505430236                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3141534733                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy      22981484                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     114826620                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq               225722                       # Transaction distribution
system.iobus.trans_dist::ReadResp              225722                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57753                       # Transaction distribution
system.iobus.trans_dist::WriteResp              11033                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       427356                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27824                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       471672                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95278                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95278                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  570236                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       213678                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2420                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13912                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       242122                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027896                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027896                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  3276590                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy              3915016                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 6000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy              8889000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy               122000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer5.occupancy               891000                       # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer6.occupancy                70000                       # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer7.occupancy                50000                       # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer8.occupancy                26000                       # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer9.occupancy            213679000                       # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy             1014000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer11.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy            20815000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                9000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer18.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy           448363457                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy             1064000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy           460639000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer1.occupancy            52378260                       # Layer occupancy (ticks)
system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                47584                       # number of replacements
system.iocache.tags.tagsinuse                0.079092                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47600                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4992999647000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.079092                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.004943                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.004943                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428751                       # Number of tag accesses
system.iocache.tags.data_accesses              428751                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          919                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              919                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          919                       # number of demand (read+write) misses
system.iocache.demand_misses::total               919                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          919                       # number of overall misses
system.iocache.overall_misses::total              919                       # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149123196                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total    149123196                       # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide  12357582001                       # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total  12357582001                       # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide    149123196                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total    149123196                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide    149123196                       # number of overall miss cycles
system.iocache.overall_miss_latency::total    149123196                       # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide          919                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            919                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          919                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             919                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          919                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            919                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162266.807399                       # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405                       # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405                       # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 162266.807399                       # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 162266.807399                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         70647                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 9165                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     7.708347                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          919                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          919                       # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total        46720                       # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide          919                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          919                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide          919                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          919                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101309696                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total    101309696                       # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide   9928122021                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total   9928122021                       # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide    101309696                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total    101309696                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide    101309696                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total    101309696                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848                       # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751                       # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751                       # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 110239.059848                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 110239.059848                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq              662612                       # Transaction distribution
system.membus.trans_dist::ReadResp             662585                       # Transaction distribution
system.membus.trans_dist::WriteReq              13919                       # Transaction distribution
system.membus.trans_dist::WriteResp             13919                       # Transaction distribution
system.membus.trans_dist::Writeback            149557                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2230                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            1790                       # Transaction distribution
system.membus.trans_dist::ReadExReq            133043                       # Transaction distribution
system.membus.trans_dist::ReadExResp           133041                       # Transaction distribution
system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
system.membus.trans_dist::BadAddressError           27                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471672                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775062                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       476745                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           54                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1723533                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141469                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141469                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1868288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       242122                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550121                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18398848                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     20191091                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6005120                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                26202783                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             1603                       # Total snoops (count)
system.membus.snoop_fanout::samples            384714                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  384714    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              384714                       # Request fanout histogram
system.membus.reqLayer0.occupancy           251770499                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy           583267500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer3.occupancy          1992294999                       # Layer occupancy (ticks)
system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer4.occupancy               33000                       # Layer occupancy (ticks)
system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         3156735730                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
system.membus.respLayer4.occupancy           55013740                       # Layer occupancy (ticks)
system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------