blob: 4862f54d8c7cb26220c97a43ac71dfdaad2d554e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
|
---------- Begin Simulation Statistics ----------
sim_seconds 5.173841 # Number of seconds simulated
sim_ticks 5173840734500 # Number of ticks simulated
final_tick 5173840734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 158571 # Simulator instruction rate (inst/s)
host_op_rate 312487 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1923470418 # Simulator tick rate (ticks/s)
host_mem_usage 368528 # Number of bytes of host memory used
host_seconds 2689.85 # Real time elapsed on the host
sim_insts 426531587 # Number of instructions simulated
sim_ops 840543055 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2458496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1064640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10449152 # Number of bytes read from this memory
system.physmem.bytes_read::total 13975936 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1064640 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1064640 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9180480 # Number of bytes written to this memory
system.physmem.bytes_written::total 9180480 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 38414 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16635 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 163268 # Number of read requests responded to by this memory
system.physmem.num_reads::total 218374 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143445 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143445 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 475178 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 618 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 205774 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2019612 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2701269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 205774 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 205774 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1774403 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1774403 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1774403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 475178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 618 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 205774 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2019612 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4475672 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 107079 # number of replacements
system.l2c.tagsinuse 64844.194000 # Cycle average of tags in use
system.l2c.total_refs 3995584 # Total number of references to valid blocks.
system.l2c.sampled_refs 171337 # Sample count of references to valid blocks.
system.l2c.avg_refs 23.320030 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 50153.806815 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker 12.883885 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker 0.168545 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst 3383.279361 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data 11294.055394 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.765286 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst 0.051625 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data 0.172334 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.989444 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker 110015 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker 8879 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst 1055721 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data 1346083 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2520698 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1613450 # number of Writeback hits
system.l2c.Writeback_hits::total 1613450 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data 329 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 329 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data 163813 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 163813 # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker 110015 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker 8879 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst 1055721 # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data 1509896 # number of demand (read+write) hits
system.l2c.demand_hits::total 2684511 # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker 110015 # number of overall hits
system.l2c.overall_hits::cpu.itb.walker 8879 # number of overall hits
system.l2c.overall_hits::cpu.inst 1055721 # number of overall hits
system.l2c.overall_hits::cpu.data 1509896 # number of overall hits
system.l2c.overall_hits::total 2684511 # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst 16637 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data 34998 # number of ReadReq misses
system.l2c.ReadReq_misses::total 51692 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data 1514 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1514 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data 129215 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 129215 # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst 16637 # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data 164213 # number of demand (read+write) misses
system.l2c.demand_misses::total 180907 # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker 50 # number of overall misses
system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses
system.l2c.overall_misses::cpu.inst 16637 # number of overall misses
system.l2c.overall_misses::cpu.data 164213 # number of overall misses
system.l2c.overall_misses::total 180907 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2626500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.inst 883116000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu.data 1863608490 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 2749714990 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu.data 39367500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 39367500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu.data 6737631498 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 6737631498 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu.dtb.walker 2626500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.inst 883116000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu.data 8601239988 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 9487346488 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu.dtb.walker 2626500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.inst 883116000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu.data 8601239988 # number of overall miss cycles
system.l2c.overall_miss_latency::total 9487346488 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu.dtb.walker 110065 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker 8886 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst 1072358 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data 1381081 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2572390 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1613450 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1613450 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data 1843 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1843 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data 293028 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 293028 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker 110065 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker 8886 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst 1072358 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data 1674109 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2865418 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker 110065 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker 8886 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst 1072358 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data 1674109 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2865418 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000454 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000788 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst 0.015514 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data 0.025341 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.020095 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data 0.821487 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.821487 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data 0.440965 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.440965 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker 0.000454 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker 0.000788 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst 0.015514 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data 0.098090 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.063135 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker 0.000454 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker 0.000788 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst 0.015514 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data 0.098090 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.063135 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52530 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.inst 53081.444972 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu.data 53248.999657 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 53194.207808 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu.data 26002.311757 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 26002.311757 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu.data 52142.796873 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 52142.796873 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52443.224906 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52530 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.inst 53081.444972 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu.data 52378.557045 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52443.224906 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 96778 # number of writebacks
system.l2c.writebacks::total 96778 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.inst 16635 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu.data 34997 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 51689 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu.data 1514 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1514 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu.data 129215 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 129215 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.inst 16635 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu.data 164212 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 180904 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.inst 16635 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu.data 164212 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 180904 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2020500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 280000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.inst 680227000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu.data 1435916999 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 2118444499 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 60967500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 60967500 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5181066001 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5181066001 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2020500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.itb.walker 280000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.inst 680227000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu.data 6616983000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 7299510500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2020500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.itb.walker 280000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.inst 680227000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu.data 6616983000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 7299510500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59191869564 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 59191869564 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211082000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1211082000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu.data 60402951564 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60402951564 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025340 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.020094 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.821487 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.821487 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.440965 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.440965 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.063134 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000454 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000788 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.inst 0.015513 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu.data 0.098089 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.063134 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47568 # number of replacements
system.iocache.tagsinuse 0.202980 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 5000598826000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.202980 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.012686 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.012686 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
system.iocache.overall_misses::total 47623 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135810932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 135810932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6905757160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 6905757160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 7041568092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 7041568092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 7041568092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 7041568092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 150399.703212 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 147811.583048 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 147860.657497 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 147860.657497 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 903 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 903 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47623 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47623 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47623 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47623 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88823000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 88823000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4476002926 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 4476002926 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 4564825926 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4564825926 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 4564825926 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.numCycles 473010428 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 90027775 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 90027775 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1176793 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 84224638 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 81706962 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 31360026 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 446936699 # Number of instructions fetch has processed
system.cpu.fetch.Branches 90027775 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 81706962 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 169789390 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 5321789 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 167863 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 104601282 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 37271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 44086 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9371006 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 537925 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5262 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 310106612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.836098 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.376721 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 140752877 45.39% 45.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1771842 0.57% 45.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 72784841 23.47% 69.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 985545 0.32% 69.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1639332 0.53% 70.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 3672529 1.18% 71.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1138013 0.37% 71.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1446532 0.47% 72.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 85915101 27.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 310106612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.190329 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.944877 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 36504487 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 100689087 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 164100014 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 4706777 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 4106247 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 876222772 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 974 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 4106247 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 40918052 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 44290154 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 10988643 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 163783570 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46019946 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 872439032 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 9880 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 35250675 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3950071 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 31995010 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1394183444 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2488413838 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 2488413278 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1347594272 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 46589165 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 469708 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 477213 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 48119615 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 18916713 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10445823 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1292985 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1005726 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 865744936 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1721292 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 864337925 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 123293 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 26001434 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 53514506 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 205573 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 310106612 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.787228 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.396179 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 102391332 33.02% 33.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 23760486 7.66% 40.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 19024925 6.13% 46.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7818761 2.52% 49.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 80618326 26.00% 75.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3106091 1.00% 76.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72752494 23.46% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 520993 0.17% 99.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 113204 0.04% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 310106612 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 162823 7.80% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1765220 84.55% 92.35% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 159742 7.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 296671 0.03% 0.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 829442170 95.96% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 25162510 2.91% 98.91% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9436574 1.09% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 864337925 # Type of FU issued
system.cpu.iq.rate 1.827313 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2087785 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 2041131934 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 893478671 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 853934886 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 866128931 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1577690 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 3621025 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 20103 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12189 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 2042088 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7821421 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4286 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 4106247 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 27916479 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1927801 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 867466228 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 303428 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 18916713 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10445834 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 882766 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 975199 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12189 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 699297 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 625213 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1324510 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 862446659 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 24735217 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1891265 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 33929559 # number of memory reference insts executed
system.cpu.iew.exec_branches 86496146 # Number of branches executed
system.cpu.iew.exec_stores 9194342 # Number of stores executed
system.cpu.iew.exec_rate 1.823314 # Inst execution rate
system.cpu.iew.wb_sent 861961974 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 853934949 # cumulative count of insts written-back
system.cpu.iew.wb_producers 669649521 # num instructions producing a value
system.cpu.iew.wb_consumers 1918783501 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.805319 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.348997 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 426531587 # The number of committed instructions
system.cpu.commit.commitCommittedOps 840543055 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26818803 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1515717 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1181719 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 306015924 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.746730 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.861261 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 125070317 40.87% 40.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14726015 4.81% 45.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4257326 1.39% 47.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 76646045 25.05% 72.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3895754 1.27% 73.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1793252 0.59% 73.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1102852 0.36% 74.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 71997039 23.53% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6527324 2.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 306015924 # Number of insts commited each cycle
system.cpu.commit.committedInsts 426531587 # Number of instructions committed
system.cpu.commit.committedOps 840543055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 23699431 # Number of memory references committed
system.cpu.commit.loads 15295685 # Number of loads committed
system.cpu.commit.membars 781577 # Number of memory barriers committed
system.cpu.commit.branches 85508404 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 768361520 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 6527324 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1166770942 # The number of ROB reads
system.cpu.rob.rob_writes 1738844954 # The number of ROB writes
system.cpu.timesIdled 2997386 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 162903816 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9874668492 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 426531587 # Number of Instructions Simulated
system.cpu.committedOps 840543055 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 426531587 # Number of Instructions Simulated
system.cpu.cpi 1.108969 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.108969 # CPI: Total CPI of All Threads
system.cpu.ipc 0.901738 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.901738 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2163215430 # number of integer regfile reads
system.cpu.int_regfile_writes 1362691420 # number of integer regfile writes
system.cpu.fp_regfile_reads 63 # number of floating regfile reads
system.cpu.misc_regfile_reads 281069935 # number of misc regfile reads
system.cpu.misc_regfile_writes 403791 # number of misc regfile writes
system.cpu.icache.replacements 1071897 # number of replacements
system.cpu.icache.tagsinuse 510.429584 # Cycle average of tags in use
system.cpu.icache.total_refs 8228054 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1072409 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.672496 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 56932855000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.429584 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996933 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996933 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 8228054 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 8228054 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 8228054 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 8228054 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 8228054 # number of overall hits
system.cpu.icache.overall_hits::total 8228054 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1142948 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1142948 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1142948 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1142948 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1142948 # number of overall misses
system.cpu.icache.overall_misses::total 1142948 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18865193488 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18865193488 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18865193488 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18865193488 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18865193488 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18865193488 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9371002 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9371002 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9371002 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9371002 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9371002 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9371002 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121966 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.121966 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.121966 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.121966 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.121966 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.121966 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16505.732096 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16505.732096 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 3301994 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 8275.674185 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 1600 # number of writebacks
system.cpu.icache.writebacks::total 1600 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70415 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 70415 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 70415 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 70415 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 70415 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 70415 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072533 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1072533 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1072533 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1072533 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1072533 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1072533 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14734319994 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14734319994 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14734319994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14734319994 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14734319994 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14734319994 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114452 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.114452 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.114452 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.itb_walker_cache.replacements 11177 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.030365 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 31227 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 11191 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.790367 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5136145388000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030365 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376898 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.376898 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31228 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 31228 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31231 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 31231 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31231 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 31231 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12057 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 12057 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12057 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 12057 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12057 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 12057 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 192652500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 192652500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 192652500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 192652500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 192652500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 192652500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43285 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 43285 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43288 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 43288 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43288 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 43288 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.278549 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.278549 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.278530 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.278530 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.278530 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.278530 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks 1620 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1620 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12057 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12057 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12057 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 12057 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12057 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 12057 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155859527 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155859527 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155859527 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155859527 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155859527 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155859527 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.278549 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.278549 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.278530 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.278530 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.replacements 116226 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 12.942586 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 138119 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 116242 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.188202 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5112881220000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942586 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808912 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.808912 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138119 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 138119 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138119 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 138119 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138119 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 138119 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117277 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 117277 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117277 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 117277 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117277 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 117277 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2115105000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2115105000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2115105000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 2115105000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2115105000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 2115105000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255396 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 255396 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255396 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 255396 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255396 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 255396 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.459197 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.459197 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.459197 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.459197 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.459197 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.459197 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks 36600 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 36600 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117277 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117277 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117277 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 117277 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117277 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 117277 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1760668506 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1760668506 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1760668506 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.459197 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.459197 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.459197 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1674194 # number of replacements
system.cpu.dcache.tagsinuse 511.997520 # Cycle average of tags in use
system.cpu.dcache.total_refs 19015880 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1674706 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.354757 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.997520 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10936415 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10936415 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8076863 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8076863 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19013278 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19013278 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19013278 # number of overall hits
system.cpu.dcache.overall_hits::total 19013278 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2432524 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2432524 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 317516 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 317516 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2750040 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2750040 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2750040 # number of overall misses
system.cpu.dcache.overall_misses::total 2750040 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 45245018000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 45245018000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10626959991 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10626959991 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 55871977991 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 55871977991 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 55871977991 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 55871977991 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13368939 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13368939 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8394379 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8394379 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21763318 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21763318 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21763318 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21763318 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181953 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.181953 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037825 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037825 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.126361 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.126361 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.126361 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.126361 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18600.029434 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 18600.029434 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33469.053500 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33469.053500 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20316.787389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20316.787389 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 26625491 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4915 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5417.190437 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1573630 # number of writebacks
system.cpu.dcache.writebacks::total 1573630 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1050273 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1050273 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22706 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 22706 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1072979 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1072979 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1072979 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1072979 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382251 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1382251 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294810 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 294810 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1677061 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1677061 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1677061 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1677061 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23310362534 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23310362534 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9362745997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9362745997 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32673108531 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 32673108531 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32673108531 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 32673108531 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207340500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207340500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386118500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386118500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86593459000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 86593459000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103393 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103393 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035120 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035120 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.077059 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.077059 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
|